Commit Graph

1422 Commits

Author SHA1 Message Date
Ville Juven
baea0012e7 mpfs_usb.c: Use kernel memory instead of user memory for DMA
DMA directly to user (virtual) memory won't work, as the DMA engine(s)
don't do address translations, i.e. they require a physical address.

Using kernel heap is fine as it is mapped vaddr=paddr. Also, the USB DMA
engine does not have any alignment requirements.
2023-12-15 18:21:03 -08:00
Ville Juven
fbd8a2127a mpfs_ethernet.c: Remove DMA_ENABLE hack
The hack just opens the entire SoC memory unconditionally, which is not
a good idea.

Test features can be used ad-hoc, they don't need to be supported by the
build.
2023-12-15 18:20:34 -08:00
simbit18
c494ce4a96 Update kconfig2html.c
Fix nuttx coding style
2023-12-14 20:02:52 -08:00
Ville Juven
e03599d9ae libs/log2ceil: Move implementation of log2ceil to a common place
Move log2ceil from riscv_pmp to libc. Also, implement log2floor for
completeness.

These are the run-time alternative to the compile-time macros.
2023-12-14 08:46:12 -08:00
Ville Juven
996625ec58 riscv/arch_elf.c: Handle PCREL_HI20/LO12_I/S relocations correctly
There is a problem with the current elf loader for risc-v: when a pair of
PCREL_HI20 / LO12 relocations are encountered, it is assumed that these
will follow each other immediately, as follows:

label:
	auipc      a0, %pcrel_hi(symbol)    // R_RISCV_PCREL_HI20
	load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S

With this assumption, the hi/lo relocations are both done when a hi20
relocation entry is encountered, first to the current instruction (addr)
and to the next instruction (addr + 4).

However, this assumption is wrong. There is nothing in the elf relocation
specification[1] that mandates this. Thus, the hi/lo relocation always
needs to first fixup the hi-part, and when the lo-part is encountered, it
needs to find the corresponding hi relocation entry, via the given "label".
This necessitates (re-)visiting the relocation entries for the current
section as well as looking for "label" in the symbol table.

The NuttX elf loader does not allow such operations to be done in the
machine specific part, so this patch fixes the relocation issue by
introducing an architecture specific cache for the hi20 relocation and
symbol table entries. When a lo12 relocation is encountered, the cache
can be consulted to find the hi20 part.

[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
2023-12-12 17:32:36 -08:00
Ville Juven
7bcbaa5dc7 riscv_pmp.c: Revert LOG2_CEIL back to run-time log2ceil function
The macro LOG2_CEIL is intended to be used in the pre-processor phase. If
used run-time it will generate a massive amount of extra code (~3.5K) which
is a problem, as the PMP configuration is quite often executed from a first
stage bootloader with a limited amount of code memory.

Code size differences pre- and post:

Memory region         Used Size  Region Size  %age Used
            envm:      112064 B     112384 B     99.72%

Memory region         Used Size  Region Size  %age Used
            envm:      108952 B     112384 B     96.95%
2023-12-12 08:51:14 -08:00
Lee Lup Yuen
614570cdcb arch/riscv: Add support for Bouffalo Lab BL808 SoC (T-Head C906)
This PR adds support for the Bouffalo Lab BL808 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for PINE64 Ox64 SBC.

Most of the code was derived from NuttX for Star64 JH7110. The UART Driver was derived from BL602 NuttX. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64

`Kconfig`: Added ARCH_CHIP_BL808 for BL808 SoC

`include/bl808/chip.h`: BL808 Definitions

`include/bl808/irq.h`: External Interrupts

`src/bl808/chip.h`: Interrupt Stack Macro

`src/bl808/bl808_allocateheap.c`: Kernel Heap

`src/bl808/bl808_head.S`: Linux Header and Boot Code

`src/bl808/bl808_irq.c`: Configure Interrupts

`src/bl808/bl808_irq_dispatch.c`: Dispatch Interrupts

`src/bl808/bl808_memorymap.h`: Memory Map

`src/bl808/bl808_mm_init.c`, `bl808_mm_init.h`: Memory Mgmt

`src/bl808/bl808_pgalloc.c`: Page Allocator

`src/bl808/bl808_serial.c`, `bl808_serial.h`: UART Driver

`src/bl808/bl808_start.c`: Startup Code

`src/bl808/bl808_timerisr.c`: Timer Interrupt

`src/bl808/hardware/bl808_memorymap.h`: PLIC and UART Base Address

`src/bl808/hardware/bl808_plic.h`: PLIC Register Addresses

`src/bl808/hardware/bl808_uart.h`: UART Register Addresses

`src/bl808/Kconfig`: BL808 Config

`src/bl808/Make.defs`: Makefile
2023-12-12 08:50:03 -08:00
Xiang Xiao
ca5a9c711a Remove @ and % tag from all comments
and format the multiple line comments

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-12-11 17:00:10 -03:00
Lee Lup Yuen
0bac2efd0e Extend MMU Flags to 64-bit for T-Head C906 and Svpbmt
Currently RISC-V NuttX supports 32-bit MMU Flags inside a Page Table Entry. This PR extends the MMU Flags to 64-bit, to support T-Head C906 Core and the new RISC-V Svpbmt Extension.

T-Head C906 uses Bits 59 to 63 in a Leaf Page Table Entry to configure the Memory Type: Cacheable / Bufferable / Strongly-Ordered. For the upcoming port of NuttX to PINE64 Ox64 BL808 SBC, we need to set the Memory Type to Strongly-Ordered for I/O Memory, which requires 64-bit MMU Flags.

Details of C906 MMU: https://lupyuen.github.io/articles/plic3#t-head-errata

Newer RISC-V Cores will use the Svpbmt Extension to configure the Memory Type (Cacheable / Strongly-Ordered). Svpbmt uses Bits 61 to 62 in a Leaf Page Table Entry to define the Memory Type. This also requires 64-bit MMU Flags.

Details of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc#svpbmt
2023-12-11 02:10:14 -08:00
anjiahao
94d449e722 arch:Mark key functions to prohibit instrumentation to prevent recursive calls
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 02:06:51 -08:00
anjiahao
7dfbd14eba libc: add instrument api support
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.

We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.

Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
   becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.

use instrument_register to register entry function and exit function.
They will be called by the instrumented function

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 02:06:51 -08:00
Ville Juven
f404cb60b8 mpfs_head.S: Change j/jal to tail call
In order to avoid linker truncation error (address unreachable), making
it a tail call ensures this does not happen.
2023-12-08 14:30:21 +01:00
chao an
a3eb42f469 cmake: split extra library from library group
Signed-off-by: chao an <anchao@xiaomi.com>
2023-12-06 07:56:17 -08:00
Ville Juven
8494fd2097 mpfs/mpfs_corespi.c: Round up divider to prevent overlock of SPI
The divider should be rounded to the next full integer to ensure that
the resulting SPI frequency is <= target frequency, i.e. the SPI is
not overclocked.
2023-11-29 01:47:55 -08:00
Ville Juven
8a2b83c482 mm/kmap: Finalize kmap implementation for RISC-V
After this, RISC-V fully supports the kmap interface.

Due to the current design limitations of having only a single L2 table
per process, the kernel kmap area cannot be mapped via any user page
directory, as they do not contain the page tables to address that range.

So a "kernel address environment" is added, which can do the mapping. The
mapping is reflected to every process as only the root page directory (L1)
is copied to users, which means every change to L2 / L3 tables will be
seen by every user.
2023-11-23 16:38:41 -08:00
Eero Nurkkala
83f5ca6158 risc-v/mpfs: ihc: cleanup DEBUGASSERTs and irq enabling
Replace DEBUGASSERTs with sanity checks. DEBUGASSERT()s are
not necessarily enabled at all, thus risking the functionality
especially in that case. Remove PANICs as well.

Don't enable the ihc irq too early. If enabled, and the master
is already up, the irq is being issued so that the system gets
stuck or is severely slowed down. Master may be already up if
this NuttX hart only is rebooted, for example.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-11-22 08:05:36 -08:00
anjiahao
749655d785 tcbinfo:remove total_num form tcbinfo.
total_num is not required
test:

make -f tools/Makefile.host
cp tools/jlink-nuttx /opt/SEGGER/JLink_V786a/libnuttxplugin.so
JLinkGDBServer -if SWD -speed 5000 -device STM32F429ZI -NoGui 1 -rtos libnuttxplugin

can run normally

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-11-21 21:52:24 -08:00
Eero Nurkkala
1cb879773a risc-v/mpfs/opensbi: update opensbi to version 1.3.1
Version 1.3.1 is the latest tagged version as of November
the 21st, 2023.  This patch prepares the required changes
to make v1.3.1 work.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-11-21 04:04:47 -08:00
chao an
64cf63475c arch/dumponexit: unify dump on exit to common code
remove arch implement and move to common code

Signed-off-by: chao an <anchao@xiaomi.com>
2023-11-15 08:28:25 -08:00
zhanghongyu
fbd0b3d1d7 cmake: move NUTTX_CHIP_ABS_DIR before common src
Some APIs are implemented both in common code and CHIP-specific code,
and the link needs to be based on the implementation in CHIP, so move
NUTTX_CHIP_ABS_DIR before common src.

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2023-11-07 17:39:03 +01:00
Ville Juven
3f3b30e384 riscv_addrenv: Fix static page table mapping (paddr instead of vaddr)
Connecting the static page tables to each other was done with the page
table virtual address (riscv_pgvaddr) when the page table physical address
is needed.
2023-11-02 21:52:23 +08:00
Ville Juven
aacdbf2a3b risc-v/addrenv: Improve the commenting on struct arch_addrenv_s
I can never remember whether the static page table list contains the
table's physical or kernel virtual address.. Add the fact as a comment
there.

Also add the limitations that come from this static page table approach
for Sv32.
2023-11-02 21:52:23 +08:00
Ville Juven
d64f216424 arch/mpfs: Add CONFIG_MPFS_BOARD_PMP option for PMP configuration
This adds option to do PMP configuration via mpfs_board_pmp_setup instead
of just opening up everything. In this case, it is up to the specific
board to implement the PMP configuration in whichever way it sees fit.
2023-10-30 12:26:39 -03:00
Ville Juven
598e1c6512 mpfs_entrypoints.c: Open all memory from PMP for hart before booting
Open PMP before the hart payload starts to execute
2023-10-30 12:26:39 -03:00
Ville Juven
17a7a7bd76 mpfs_opensbi: Remove mpfs_opensbi_pmp_setup
The PMP setup should be done in the board specific code, at a much
earlier stage. Granting all access is a security risk anyway.
2023-10-30 12:26:39 -03:00
SPRESENSE
f3fabc5d32 Revert "make/archive: Use the full path name when matching or storing names in the archive"
This reverts commit 563125fde3.
2023-10-27 22:26:18 +08:00
xuxin19
9112b9e4c0 cmake:add zifencei extension in compile options
this fixes the error opcode `fence.i` by cmake compilation

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2023-10-26 21:01:46 +08:00
xuxin19
e3003f691b cmake:init RISC-V cmake qemu-rv build
cmake currently does not support non-FlatBuild,
need disable ELF and LOADABLE when compiling other defconfigs

```
 cmake -B build -DBOARD_CONFIG=rv-virt/smp64 -GNinja # for rv32:rv-virt/smp
 cmake --build build -t menuconfig
 cmake --build build
 qemu-system-riscv64 -semihosting -M virt,aclint=on -cpu rv64 -smp 8 -bios none -kernel nuttx -nographic
```

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2023-10-26 21:01:46 +08:00
Tiago Medicci Serrano
a2be27ef7d espressif: Update esp-hal-3rdparty version
This version includes a bugfix for the NULL definition.
2023-10-26 20:02:13 +08:00
Stuart Ianna
5fa1819492 arch/risc-v/litex/litex-emac: Add support for phy interrupts.
Add support for PHY interrupts in the architecture layer of the Litex emac driver. Boards need to add handling for interrupt lines, if supported.
2023-10-26 09:02:23 +08:00
chao an
3cadf6642a kernel: replace all usleep to nxsig_usleep in kernel space
syscall cannot be called from kernel space

Signed-off-by: chao an <anchao@xiaomi.com>
2023-10-25 15:46:03 +08:00
Stuart Ianna
ee84ea3875 arch/risc-v/litex/litex_gpio: Fix ISR dispatch when using higher GPIO indexes.
Previously, GPIO interrupts were not correctly mapped to the peripheral base register responsible for the interrupt.

Change the IRQ number calculation so the interrupts work correctly on all GPIO peripheral bases.
2023-10-25 15:42:25 +08:00
Stuart Ianna
ac5800386c arch/risc-v/litex/litex_emac: Add support for KSZ8061 ethernet PHY.
Adds support for using the microchip KSZ8061 ethernet PHY instead of the default DP83848C.
2023-10-25 13:33:03 +08:00
Ville Juven
9c725c4903 arch/risc-v: Simplify pmp_check_region_attrs sanity-checks
For TOR: Any size and 4-byte aligned address is required
For NA4: Only size 4 and 4-byte aligned address is good
For NAPOT: Minimum size is 8 bytes, minimum base alignment is 8 bytes,
           and size must be power-of-two aligned with base

This commit simplifies these checks and removes all the nonsense added
by a misunderstanding of how the MPFS / Polarfire SoC's PMP works.
2023-10-23 13:10:59 -03:00
Ville Juven
8e6b448f47 arch/risc-v: Remove unnecessary PMP kconfig options
These options are just wrong and a result of misunderstanding of the
Polarfire SoC spec. There are no feature limitations in the CPU PMP
implementation -> remove any configuration options added.
2023-10-23 13:10:59 -03:00
Ville Juven
0e75e53cc8 mpfs_head.S: Simplify clearing PMP
Initially clear PMP for all harts, this fixes random warm reset issues.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2023-10-17 20:13:09 +08:00
Ville Juven
3f878d8100 mpfs_ethernet.c: Release tx descriptor and rx buffer properly
Instead of releasing rx descriptor twice and tx buffer twice.
2023-10-16 21:54:31 +08:00
Ville Juven
ee9e41f2dd mpfs_ethernet.c: Fix possible NULL de-reference
Fix case where NULL is de-referenced via tx/rx buffer or descriptor. Only
1 queue is currently set up for each, so the indices 1,2,3 are not valid
and should not be handled.
2023-10-16 21:54:31 +08:00
Ville Juven
64b6ac3d87 mpfs/mpfs_entrypoints.c: Fix potential R_RISCV_JAL linker error
Change bgtz t0, mpfs_opensbi_prepare_hart to tail-call to ensure there
will be no link time error due to the jump offset being too large.
2023-10-16 21:52:01 +08:00
TaiJuWu
1989749850 cpu_pause.c: fix typo
Signed-off-by: TaiJuWu <tjwu1217@gmail.com>
2023-10-14 00:26:31 -04:00
hujun5
061be5f18e refine: move BIT Macro to nuttx/bits.h
The BIT macro is widely used in NuttX,
and to achieve a unified strategy,
we have placed the implementation of the BIT macro
in bits.h to simplify code implementation.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-10-12 14:52:56 +08:00
Ville Juven
d199264dca kmm_map: Fix incorrect function name field 2023-10-09 18:59:43 +03:00
Ville Juven
3e8575c39e riscv-v/pgalloc.h: Return kernel vaddr for kernel RAM paddr
All kernel memory is mapped paddr=vaddr, so it is trivial to give mapping
for kernel memory. Only interesting region should be kernel RAM, so omit
kernel ROM and don't allow re-mapping it.
2023-10-09 18:59:25 +03:00
Xiang Xiao
dfa0283d83 spinlock: Rename spin_islocked to spin_is_locked
align with Linux naming style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-10-06 20:03:19 -04:00
Ville Juven
7901ed0fe3 riscv_addrenv_utils.c: Determine page table flags by type of vaddr
Use kernel page table flags if the mapped virtual address is in kernel
space.
2023-10-05 20:38:35 +08:00
Ville Juven
8c6be8e1f3 riscv/addrenv: Fix the user VMA end address
The end address was off by 1, making it overflow to 0 (u32 value).
2023-09-29 22:34:40 +08:00
Xiang Xiao
cb11747f36 arch: add use_data to g_tcbinfo
to avoid compiler/linker remove it from the final image

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-09-29 08:00:18 +03:00
Ville Juven
7b18f5eb6f risc-v/riscv_addrenv.c: Fix bug where SHM area page tables are not freed
The SHM physically backed memory does not belong to the user process,
but the page table containing the mapping does -> delete the page table
memory regardless.
2023-09-28 22:17:55 +08:00
Ville Juven
2cd1fd1145 risc-v/pgalloc.h: Add SHM area to riscv_uservaddr query
If the vaddr resides within the user's SHM, it is a user memory mapping.
2023-09-28 22:17:55 +08:00
Ville Juven
9be93addea mpfs/mpfs_corespi: Several speed optimizations to the FPGA driver
This is a collection of tweaks / optimizations to the driver to limit
CPU usage as well as interrupt processing times.

The changes are as follows:
- setfrequency is now no-op if the frequency does not change. Accessing
  MPFS_SPI_CONTROL requires synchronization to the FIC domain, which
  takes unnecessary time if nothing changes
- load/unload FIFO loops optimized so !buffer, priv->nbits and i==last are
  only tested once (instead of for every word written in loop).
- Disable the RX interrupt only once (again, FIC domain access is slow)
- In case a spurious MPFS_SPI_DATA_RX interrupt arrives, just wipe the
  whole RX FIFO, instead of trying to read it byte-by-byte
2023-09-28 09:36:07 +08:00