since rwbuffer isn't fully initiailized in mmcsd_slotinitialize.
BTW, if the cache is important for performance, it is better to
implement a general block cache and put in a common location.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This change makes it so that the timeout is set as part of the SDIO_WAITENABLE call instead of the SDIO_EVENTWAIT call. By doing so, you eliminate all opportunity for a race condition.
stm32h7:sdmmc Check if busy ended early
mmcsd:Remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
stm32h7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
stm32f7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
stm32f7:sdmmc WRITE COMPLETE prevent false triggers
stm32h7:sdmmc WRITE COMPLETE prevent false triggers
While testing PR #2989 on the H7 I noticed that the cards
were staying in 1-bit mode. The root cause was that the
scr read path was using DMA without an invlidate.
This was caused by CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT,
but the sdmmc driver, did not use the delayed invalidate
nor would it work on 8 bytes.
The driver fully supported dcache mgt on runt buffers, but
the #ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT blocked it.
Reviewing the PR that added CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
it may have been valid at the time. But after the dcache operations
we fixed. It is not necessary and offers no benefit.
This change reflects that the geometry isn't related to the largest
allocatable unit on the platform.
Calls to read and write block devices are also affected and have
been updated.
The Multiblock write path was missing the
the SDIO_WAITENABLE with SDIOWAIT_WRCOMPLETE.
This could be seen with debugging turned on as
mmcsd_eventwait: ERROR: Awakened with 10
mmcsd_transferready: ERROR: mmcsd_eventwait for transfer ready failed: -5
When CONFIG_MMCSD_MULTIBLOCK_DISABLE is lit, all SD
read/write failed. The function return the number of
blocks in `ret`, set on entry to nsectors. That was
then wiped out by using the ret for the mmcsd_takesem.
Since the code had many path setting return, the choices for
the fix could have been add a new varaible or simple init it
were used. I choose the latter.
- Add missing cancel process when the send command fails
- Make it possible to recover from SD initialization error
- Reduce time in changing transfer mode to 5msec from 500msec.
Replace usleep function instead of up_udelay in other to avoid
blocking other tasks from working.
The SDIO interface structure includes fields with names like recvR1 and others. These cause "Mixed case identifier" errors from nxstyle in all places they are uses.
This change performs a mass substition of recvR with recv_r to correct this coding standard violation.
* Simplify EINTR/ECANCEL error handling
1. Add semaphore uninterruptible wait function
2 .Replace semaphore wait loop with a single uninterruptible wait
3. Replace all sem_xxx to nxsem_xxx
* Unify the void cast usage
1. Remove void cast for function because many place ignore the returned value witout cast
2. Replace void cast for variable with UNUSED macro
drivers/mmcsd: Fixes bug where thread gets deadlocked due to recursive call and addresses comment regarding events.
When initializing the MMCSD, if we are being told there is a card, but we fail to initialize it, we should not re-register for an insertion event as this will immediately cause us to call in again. Instead, we should register for a removal event and wait for the card to be removed and re-inserted.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
The user of this invalidation are mmcsd_sdio currently. The mmcsd_sdio driver makes calls for dcache invalidation through the chip specific architecture function SDIO_DMARECVSETUP(). I changed the arch/arm/stm32f7 chips to use arch_invalidate_dcache_by_addr() instead of arch_invalidate_dcache().
This commit includes additional changes to mmcsd_sdio.c. I created SDIO_DMADELYDINVLDT() (DMA delayed invalidate) to invalidate store-into mode dcaches after the DMA transfer. I have been using SDIO_DMADELYDINVLDT() for several weeks now and it has fixed the problems that I previously reported regarding non-cache aligned buffer invalidation errors (for my store-through dcache). However, it does not permit use of unaligned DMA buffers for store-into mode dcaches.
SDIO_DMADELYDINVLDT() is a NoOp unless the chip specific Kconfig file selects CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT. I have modified all the stm32f7 chips to select it.
In addition to the problems that were previously identified there were a few other bits and pieces outstanding;
* Timing was dependent on CPU speed rather than absolute time
* End of transfer handling was a bit mixed up
* It's possible for data to still be in the FIFO (i.e. not have reached
the card) when a next write is requested, so we need to wait for that to
complete
* Interrupt Status could be carried over from one transfer episode to the
next, corrupting progress
* Multi-descriptor DMA writing simply wasn't implemented, but there were no
indications ... it just failed silently
