sergiotarxz/nuttx
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24 Commits

Author SHA1 Message Date
Huang Qi
e047ab9c70 riscv: Initial support for debug trigger module 
Implement up_debugpoint_add/up_debugpoint_remove for riscv.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2024-07-14 20:32:19 +08:00
Huang Qi
384610b253 riscv: Add indirect CSRs for CLIC 
Add indirect CSR registers for RISC-V Core-Local Interrupt Controller (CLIC) Privileged Architecture Extensions.

Refer to: https://github.com/riscv/riscv-fast-interrupt

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2024-06-21 03:02:59 +08:00
Huang Qi
e5ee04a902 riscv: Add CSRs for CLIC 
Add CSR registers for RISC-V Core-Local Interrupt Controller (CLIC) Privileged Architecture Extensions.

Refer to: https://github.com/riscv/riscv-fast-interrupt

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2024-06-21 03:02:59 +08:00
Huang Qi
8ee461fa0e riscv: Add CSRs for Smcsrind/Sscsrind 
Add CSR registers for RISC-V Indirect CSR Access (Smcsrind/Sscsrind) Extension.

Refer to: https://github.com/riscvarchive/riscv-indirect-csr-access/tree/main

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2024-06-21 03:02:59 +08:00
Inochi Amaoto
3cabc92427 arch/risc-v: add risc-v SSTC extension support 
SSTC extension allows nuttx to implement S-mode timer directly,
which is useful for starting at S-mode.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
 2024-04-27 22:09:22 -03:00
Inochi Amaoto
1ef3767f85 arch/risc-v: unfiy IPI access 
Add ipi process abstract function support.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
 2024-04-27 22:09:22 -03:00
Huang Qi
93d75129de riscv: Add Vector CSRs to csr.h 
The CSR register definitions from RVV 1.0 spec: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-registers

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2024-04-19 00:31:07 +08:00
Huang Qi
9e78b235fe riscv: Add more debug related CSR definitions 
This patch adds more debug related CSR definitions
to arch/risc-v/include/csr.h.

These definitions are from the RISC-V Debug Specification
Version 1.0 rc1 (https://github.com/riscv/riscv-debug-spec).

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2024-04-10 21:10:39 +08:00
Yanfeng Liu
f69f0674f6 arch/risc-v: add status fields for VS and XS 
add defintions for vector extension and additional user-mode
extension fields for MSTATUS and SSTATUS registers.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
 2024-01-28 06:38:25 -08:00
Xiang Xiao
7a209e6ee8 arch/riscv: Align the macro definition in csr.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-02 14:08:37 +03:00
Ville Juven
c15b6701ce RISC-V: Implement option to run NuttX in supervisor mode (S-mode) 
- Add config "ARCH_USE_S_MODE" which controls whether the kernel
  runs in M-mode or S-mode
- Add more MSTATUS and most of the SSTATUS register definitions
- Add more MIP flags for interrupt delegation
- Add handling of interrupts from S-mode
- Add handling of FPU from S-mode
- Add new context handling functions that are not dependent on the trap
  handlers / ecall

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
      thus S-mode is not usable as is, yet.
 2022-04-01 16:19:42 -03:00
Petro Karashchenko
36b0b95eb1 arch/risc-v: include csr.h indirectly through nuttx/irq.h 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-31 19:34:52 +08:00
Huang Qi
00efcd3308 arch/risc-v: Merge riscv_getnewintctx into common 
And also mask the bits which should be preserved (from ISA spec)

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-19 17:38:18 +08:00
Xiang Xiao
ea614090cd arch/risc-v: Change hex number to low case in csr.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-13 10:17:25 +02:00
Huang Qi
35330a798b risc-v: Implement READ_AND_SET_CSR for CSR operate 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-03 19:55:54 +08:00
Ville Juven
81188d9c94 Extend the RISC-V PMP functionality 
- Add test for mode support, which is architecture dependent
- Add tests for address alignment and region size
- Add option to query for access rights
 - The function goes through every PMP entry and tests if an address
   range from [base, base+size] has been configured for desired
   access rights.
 - If several PMP entries match the range and access rights, the
   information is combined
 - End result is either no access, a partial match was found, or a full
   match was found. Details about the partial match are not provided.

The intent for testing access rights and not just blindly applying them
is a case where they are already set in e.g. a bootloader. In this
case, nothing should be done, unless the configuration does not match,
in which case the software must not continue further.
 2022-01-25 20:22:34 +08:00
Alin Jerpelea
231b8518b7 NuttX: Ken Pettit: update licenses to Apache 
Ken Pettit has submitted the ICLA and we can migrate the licenses
 to Apache.

Sebastien Lorquet has submitted the ICLA and we can migrate the licenses
 to Apache.

Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-10 06:42:19 -05:00
hotislandn
6aa86b469c arch:rv64:c906:add PMP, change mem map for protect build. 
Signed-off-by: hotislandn <hotislandn@hotmail.com>
 2021-03-28 09:02:48 -05:00
hotislandn
84daebf2cc arch:risc-v:bl602: enable FPU for this target. 2021-02-08 00:29:34 -08:00
Abdelatif Guettouche
0f2b774dec arch/risc-v: Remove unused and undefined file section "Public Variables" 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-01-27 18:40:10 -08:00
Virus.V
2b8e0945a9 Fix BL602 CI Build failed. 
Modify the default configuration in KConfig.
Sync latest commit from mainline.

Remove unused demo configuration

fixup bl602 nsh defconfig cause CICD failed

Rebase from mainline code
 2020-12-29 01:52:09 -08:00
liang
b074ebec9e fix redefined CSR_INSTRET 2020-12-23 01:34:14 -06:00
Xiang Xiao
92cefb0a78 arch/risc-v: Move CSR register bit definition to csr.h 
to avoid the macro duplication

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-20 20:27:13 -08:00
Xiang Xiao
d42c5a0bf6 arch/risc-v: Move csr.h to common place 
since CSR definition is same for 32bit and 64bit arch

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-19 08:41:33 +09:00