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66 Commits

Author SHA1 Message Date
Gregory Nutt
be5ba90d4f Move optimized ARM memcpy functions from arch/arm/src/ to libc/machine/. This is necessary for the PROTECTED and KERNEL build modes. Otherwise, memcpy() will be built in to kernel space and not accessible to applications. 2017-01-20 10:53:46 -06:00
Gregory Nutt
13d00344c9 Add configuration to prevent selection of Windows native toolchains when using Ubuntu under Windows 10 2017-01-02 07:16:47 -06:00
Gregory Nutt
3a0413c048 Back out most of 34be3e7c3c and update README again. Windows native tools cannot be used with Ubuntu under Windows 10 now. For Cygwin, that support depends on the 'cygpath -w' tool to convert POSIX paths to Windows paths. There is no corresponding tool for Ubuntu under Windows 10. 2017-01-01 16:29:03 -06:00
Gregory Nutt
34be3e7c3c Add configuration support for builds with Ubuntu under Windows 10 2017-01-01 15:34:23 -06:00
Gregory Nutt
dc79e35d65 For Cortex-A9, should also set ACTLR.FW in SMP mode to enble TLB and cache broadcasts. Does not fix SMP cache problem. 2016-12-07 09:06:41 -06:00
Gregory Nutt
89c3c20052 Merge remote-tracking branch 'origin/master' into misoc 2016-11-06 11:09:05 -06:00
Gregory Nutt
c1a687a4e5 Trivial changes from review of last PR 2016-11-06 08:11:01 -06:00
Heesub Shin
bda7d9ee4d ARMv7-R: fix to restore the Thumb flag in CPSR 
Thumb flag in CPSR is not restored back when the context switch occurs
while executing thumb instruction.

Reported-by: Eunbong Song <eunb.song@samsung.com>
Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
 2016-11-06 21:48:02 +09:00
Heesub Shin
343243c7c0 ARMv7-R: fix CPSR corruption after exception handling 
A sporadic hang with consequent crash is observed when booting:

    arm_prefetchabort: Prefetch abort. PC: 04d34a00 IFAR: 04d34a00 IFSR: 00000008
    up_assert: Assertion failed at file:armv7-r/arm_prefetchabort.c line: 87 task: init
    up_dumpstate: Current sp: 004c3df0
    up_dumpstate: Interrupt stack:
    up_dumpstate:   base: 004c05fc
    up_dumpstate:   size: 00000800
    up_dumpstate: User stack:
    up_dumpstate:   base: 004c3f58
    up_dumpstate:   size: 00000fec
    up_dumpstate: User Stack
    up_stackdump: 004c3de0: 004a0d14 004c3df0 004c3f58 004a0d20 00000057 004c2c58 09000000 004a42a4
    up_stackdump: 004c3e00: 00000003 004c3e10 004a0f1c 004bbcef 33c44b00 004a0f28 04d34a00 00000008
    up_stackdump: 004c3e20: 00000008 004a01bc 004bfd38 00000001 00007fff 00000001 34134a00 d83e4c00
    up_stackdump: 004c3e40: 09000000 00000000 33c44b00 d83e4c00 0c3f4c00 00000000 00000000 00000003
    up_stackdump: 004c3e60: 004c3e70 004a1494 04d34a00 200b0253 004c3ed8 004a5298 004c3ed8 6d00006d
    up_stackdump: 004c3e80: 0000006d 004bc3f4 00000009 004a4f64 00000009 b9e0784f 333f3ed0 69d4227d
    up_stackdump: 004c3ea0: d81f09bd 0f867344 5a7e2c12 8acefd34 5d00dc1b 004bc432 004c3f08 004c0e08
    up_stackdump: 004c3ec0: 00000000 00000000 00000000 00000000 00000000 004a4210 004a5258 004a5300
    up_stackdump: 004c3ee0: 00000000 00000001 ffffffff 004c3f80 000002b0 004a4234 00000007 004c3f08
    up_stackdump: 004c3f00: 004a58b4 004bc432 004bc3f4 004c3f80 000002b0 0000029c 00000000 0000029c
    up_stackdump: 004c3f20: 00000000 004a5900 0000ff01 00000000 00000000 004a61f4 00000000 004a5fa4
    up_stackdump: 004c3f40: 00000000 004a5f6c 00000000 004a2668 00000000 00000000 b7509f04 004c3f64
    up_registerdump: R0: 00000001 00007fff 00000001 34134a00 d83e4c00 09000000 00000000 33c44b00
    up_registerdump: R8: d83e4c00 0c3f4c00 00000000 00000000 00000003 004c3e70 004a1494 04d34a00
    up_registerdump: CPSR: 200b0253

It seems to be caused by the corrupted or wrong CPSR restored on return
from exception. NuttX restores the context using code like this:

    msr spsr, r1

GCC translates this to:

    msr spsr_fc, r1

As a result, not all SPSR fields are updated on exception return. This
should be:

    msr spsr_fsxc, r1

On some evaluation boards, spsr_svc may have totally invalid value at
power-on-reset. As it is not initialized at boot, the code above may
result in the corruption of cpsr and thus unexpected behavior.

Reported-by: Eunbong Song <eunb.song@samsung.com>
Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
 2016-11-06 20:48:09 +09:00
Heesub Shin
6bfc6b4d23 ARMv7-R: fix typo in mpu support 
s/ARMV7M/ARMV7R/g

Reported-by: Eunbong Song <eunb.song@samsung.com>
Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
 2016-11-06 20:48:09 +09:00
Heesub Shin
003511d198 ARMv7-R: add cache handling functions 
This commit adds functions for enabling and disabling d/i-caches which
were missing for ARMv7-R.

Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
 2016-11-06 20:48:01 +09:00
Heesub Shin
6a1a846011 ARMv7-R: add new Kconfig entries for d/i-cache 
Unlike in ARMv7-A/M, Kconfig entries for data and instruction caches
are currently missing in ARMv7-R. This commit adds those missing Kconfig
entries. Actual implmenetation for those functions will be added in the
subsequent patches.

Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
 2016-11-06 16:07:46 +09:00
Heesub Shin
2b922fcdbd ARMv7-R: remove the redundant update on SCTLR 
mpu_control() is invoking cp15_wrsctlr() around SCTLR update
redundantly.

Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
 2016-11-06 16:07:45 +09:00
Heesub Shin
05d477661b ARMv7-R: fix invalid drbar handling 
In ARMv7-R, [31:5] bits of DRBAR is physical base address and other bits
are reserved and SBZ. Thus, there is no point in passing other than the
base address.

Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
 2016-11-06 16:07:41 +09:00
Heesub Shin
af6e4f59c6 ARMv7-R: fix compilation error 
This commit fixes compilation errors on MPU support for ARMv7-R.

Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
 2016-11-06 16:07:38 +09:00
Heesub Shin
96a200a71c ARMv7-R: fix typo 
fix trivial typo: s/ARMv7-A/ARMv7-R/

Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
 2016-11-06 16:07:36 +09:00
Gregory Nutt
cb96e632fa LM32: Add toolchain configuration; Add Toolchain.defs. 2016-11-03 07:21:25 -06:00
Gregory Nutt
841e1aa77f Fix a cloned typo 2016-10-19 09:14:21 -06:00
Gregory Nutt
5a0f9fcb7d Fix STM32 RTC Alarm interrupts. They were being enabled BEFORE the interrupt system was being initialized. 2016-07-23 10:36:06 -06:00
Gregory Nutt
7f16548f57 Replaces last three commits. Does the same thing, but does it in a way that does not change the usage model. 2016-06-21 05:26:08 -06:00
Gregory Nutt
c05da80a27 Eliminate a warning 2016-06-20 22:54:58 -06:00
Gregory Nutt
505ca542e8 Remove some last traces of lowvsyslog that were missed; Add a SYSLOG emergency channel for handling assertion output more cleanly 2016-06-20 16:11:50 -06:00
Gregory Nutt
43eb04bb8f Without lowsyslog() *llinfo() is not useful. Eliminate and replace with *info(). 2016-06-20 11:59:15 -06:00
Gregory Nutt
d88bbaa185 armv7-r/armv7-m: Convert *err() to either *info() or add ERROR:, depending on if an error is reported 2016-06-17 15:57:52 -06:00
Gregory Nutt
b39e53391d Add underscore at beginning of alert() as well 2016-06-16 12:38:05 -06:00
Gregory Nutt
0c8c7fecf0 Add _ to the beginning of all debug macros to avoid name collisions 2016-06-16 12:33:32 -06:00
Gregory Nutt
6f08216621 Centralize definitions associated with CONFIG_DEBUG_SYSCALL 2016-06-16 08:12:38 -06:00
Gregory Nutt
a98bc05f65 New debug macro: alert(). This is high priority, unconditional output and is used to simplify and stanardize crash error reporting. 2016-06-14 09:07:53 -06:00
Gregory Nutt
0f249016a0 Eliminate some warnings 2016-06-13 14:01:32 -06:00
Gregory Nutt
a1469a3e95 Add CONFIG_DEBUG_ERROR. Change names of *dbg() * *err() 2016-06-11 15:50:49 -06:00
Gregory Nutt
e99301d7c2 Rename *lldbg to *llerr 2016-06-11 14:55:27 -06:00
Gregory Nutt
1cdc746726 Rename CONFIG_DEBUG to CONFIG_DEBUG_FEATURES 2016-06-11 14:14:08 -06:00
Gregory Nutt
fc3540cffe Replace all occurrences of vdbg with vinfo 2016-06-11 11:59:51 -06:00
Gregory Nutt
3a74a438d9 Rename CONFIG_DEBUG_VERBOSE to CONFIG_DEBUG_INFO 2016-06-11 11:50:18 -06:00
Gregory Nutt
4d4f54a789 Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
Gregory Nutt
83bc1c97c3 Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore() 2016-02-14 16:11:25 -06:00
Gregory Nutt
70e502adb0 Replace irqsave() with enter_critical_section(); replace irqrestore() with leave_critical_section() 2016-02-13 19:11:09 -06:00
Gregory Nutt
6181711942 Correct some comments 2016-02-09 13:48:16 -06:00
Gregory Nutt
a6eb9a351c Add spinlock support for ARMv7-M architectures 2016-02-09 13:44:22 -06:00
Gregory Nutt
98e9e7d768 Add spinlock support for ARMv7-R architectures 2016-02-09 13:01:32 -06:00
Gregory Nutt
ed4e3c0a9e ARM: Replace explicit references to g_readytorun with indirect references via the macro this_task() 2016-02-06 13:41:28 -06:00
Gregory Nutt
10001f8556 WINTOOl should be selected only for Cygwin. MSYS and native should not have it. 2016-01-09 16:34:33 -06:00
Gregory Nutt
d9737f0645 TMS570: reset stack pointer before calling os_start 2015-12-29 07:56:22 -06:00
Gregory Nutt
e7d7036cb9 ARMv7-R: L2CC_VBASE->L2CC_BASE 2015-12-28 16:32:34 -06:00
Gregory Nutt
ae0e6b4096 ARMv7-R and TMS570: Re-orider some initialization logic. __start used to called arm_boot() which would return. Then __start would call os_start(). That won't work for the TMS570 if is does a destructive memory tested because the return information will be lost in the stack. Also comment a nuisance assertion. The assertion is probably correct but certainly a nuisance during initial testing 2015-12-28 16:15:33 -06:00
Gregory Nutt
c3758286d7 TMS570: Add ESM interrupt handler 2015-12-27 08:34:14 -06:00
Gregory Nutt
e0214f9d62 ARMv7-R: Remove some CONFIG_PAGING logic left over from ARMv7-A leverage 2015-12-27 08:32:53 -06:00
Gregory Nutt
6d0650349a Add support for ARM big-endian toolchains with prefix armeb- 2015-12-26 18:13:01 -06:00
Gregory Nutt
9bcf27d15b TMS570 is big-endian 2015-12-26 14:47:54 -06:00
Gregory Nutt
663d2b0127 Eliminate a warning due to a range check on an undefined pre-processar variable 2015-12-22 13:20:20 -06:00