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18964 Commits

Author SHA1 Message Date
Xiang Xiao
30e80f2394 arch/sim: Remove the unused SIM_TCNWAITERS from Kconfig 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-28 09:16:38 +03:00
lishaoen
aa0c9fd788 nuttx: Add new config ARM_HAVE_MVE for MVE instruction 
Signed-off-by: lishaoen <lishaoen@xiaomi.com>
 2022-03-28 08:51:24 +03:00
Huang Qi
83a5e9958f arch/risc-v: Correct comments for current implementations 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-28 13:41:57 +08:00
Huang Qi
35f9265483 arch/risc-v: Move fpu [re]store to common place 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-28 13:41:57 +08:00
Lee Lup Yuen
c67272f9c8 riscv/bl602: Enable SPI Master in SPI Poll Send 
## Summary

SPI Poll Send `bl602_spi_poll_send()` doesn't send any SPI Data because it doesn't enable SPI Master and it doesn't clear the SPI FIFO. Also it hangs because it loops forever waiting for the FIFO.

We fix this problem by moving the code that enables SPI Master and clears the FIFO, from SPI Poll Exchange `bl602_spi_poll_exchange()` to SPI Poll Send. (Note that SPI Poll Exchange calls SPI Poll Send)

[More Details Here](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

## Impact

This problem affects all NuttX Drivers that call `SPI_SEND()` on BL602, including the ST7789 Display Driver.

Previously `SPI_SEND()` didn't send any SPI Data and never returns, because it loops forever waiting to receive data.

Now `SPI_SEND()` sends data and returns correctly.

[More Details Here](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

## Testing

We tested the modified SPI Poll Send with NuttX ST7789 Driver and a Logic Analyser on PineCone BL602:

-  [Testing with Logic Analyser](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

We also tested LVGL with ST7789 on PineCone BL602:

-  [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for the modified SPI Poll Exchange, we tested with Semtech SX1262 SPI Transceiver on PineCone BL602:

-  [Testing SPI Poll Exchange](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-25)
 2022-03-28 13:32:27 +08:00
Xiang Xiao
8c8c60f70a arch: Add -fsanitize=kernel-address to ARCHCPUFLAGS if CONFIG_MM_KASAN=y 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-27 23:01:47 +03:00
ligd
e87d262c7f arch/Toolchain.defs: add wildcard for EXTRA_LIBS 
VELAPLATFO-1491

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-27 22:53:58 +03:00
Xiang Xiao
a2e079fdd2 arch/arm: Change arm_arch.h to arm_internal.h in arm_perf.c 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-27 22:31:43 +03:00
Anthony Merlino
baeb2e9af7 stm32h7: Addresses tickless PR review comments 2022-03-28 00:33:26 +08:00
Anthony Merlino
896435e7c9 Fixes formatting 2022-03-28 00:33:26 +08:00
Anthony Merlino
c3745c8441 Adjust up_timer_getmask to handle 16-bit timers correctly. 2022-03-28 00:33:26 +08:00
Anthony Merlino
30f6dbc613 Throw compile time error if tickless timer is set to TIM6/TIM7 2022-03-28 00:33:26 +08:00
Anthony Merlino
95199f4790 stm32h7 timer: Clean up some bit operations to make them more readable. 2022-03-28 00:33:26 +08:00
Anthony Merlino
e5c8bb9b34 stm32h7: Fix a bunch of tickless issues. 2022-03-28 00:33:26 +08:00
Anthony Merlino
2fad06008a stm32h7: Adds tickless support. 2022-03-28 00:33:26 +08:00
ligd
f623ac0f13 armv7-m/armv8-m: move up_pref* api to common place 
Signed-off-by: ligd <liguiding1@xiaomi.com>
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-26 13:39:18 +02:00
Huang Qi
052c071867 arch/risc-v: Minor style change 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-26 16:52:13 +09:00
Huang Qi
494230a841 arch/risc-v: Improve performance of context switch 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-26 07:19:09 +09:00
Petro Karashchenko
7afedda89e arch/risc-v: improve style consistency accross chip variants 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-25 10:26:15 -03:00
Abdelatif Guettouche
914e9588bb esp32/Make.defs: Organise common arch files and chip files 
appropriately.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-25 11:31:24 +08:00
Gustavo Henrique Nihei
c92c4af304 xtensa/esp32s2: Initialize instruction cache on startup 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-23 20:05:40 -03:00
Gustavo Henrique Nihei
bc071ec243 xtensa/esp32s2: Use functions defined in xtensa_counter for TimerISR 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-23 19:38:28 -03:00
Gustavo Henrique Nihei
04b80cc8d2 xtensa/esp32s2: Remove unused and not unsupported configs from Kconfig 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-23 19:38:28 -03:00
Ville Juven
44bec4cf8e RISC-V: Add missing code to dumpstate 
Just add the kernel stack dumping for completeness
 2022-03-24 00:15:28 +08:00
Ville Juven
77e90d9c87 RISC-V: Include support for kernel stack 
Preparation for CONFIG_BUILD_KERNEL=y, which requires that a kernel
stack is allocated for each user process.
 2022-03-24 00:15:28 +08:00
Huang Qi
9cffc105c8 arch: Show assigned cpu in dump task 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-23 22:18:15 +08:00
Huang Qi
f09ea317c1 risc-v/qemu-rv: Restore FPU context after context switch 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-23 19:30:04 +08:00
chao.an
7b73606300 arm/schedulesigaction: update the SP to signal context top 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-23 19:08:37 +09:00
chao.an
a770ff2017 arm/vfork: update the SP to stack top 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-23 19:08:37 +09:00
Xiang Xiao
9ae0dcd4a2 arch/arm: Remove the code copy register from xcpt to stack 
since xcpt always point to the stack after the below change:
commit 7b9978883c
Author: chao.an <anchao@xiaomi.com>
Date:   Tue Mar 1 01:06:24 2022 +0800

    arch/arm: optimize context switch speed

    The current context save implementation saves registers of each task
    to xcp context, which is unnecessary because most of the arm registers are
    already saved in the task stack, this commit replace the xcp context with
    stack context to improve context switching performance and reduce the tcb
    space occupation of tcb instance.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-23 19:08:37 +09:00
Gustavo Henrique Nihei
024364ebbd xtensa/esp32s3: Add support for GPIO pin interrupts 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-23 07:23:51 +09:00
Gustavo Henrique Nihei
0e67dc8637 xtensa/esp32s3: Add support for GPIO read/write operations 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-23 07:23:51 +09:00
Petro Karashchenko
68902d8732 pid_t: unify usage of special task IDs 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-22 21:22:32 +08:00
Harri Luhtala
2ee12b2c5d arch/arm/src/stm32l4: peripheral voltage monitor support for vddio2 
Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
 2022-03-22 21:08:29 +08:00
Petro Karashchenko
757d01d915 progmem: eliminate PROGMEM_ERASESTATE configuration option 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-22 10:01:41 -03:00
Abdelatif Guettouche
10f8f6c9e3 xtensa/esp32(s2)_user.c: For EXCCAUSE values, use macros defined in xtensa_corebits.h 
instead of those defined in core.h as they are deprecated.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-22 10:20:27 +08:00
smartether
7fbadb5c16 fixed mpu9250 not work on i2c bus issue. 
1,set rp2040 FIFO_MAX_SIZE to 16.ref: pico sdk ->
static inline size_t i2c_get_write_available(i2c_inst_t *i2c) {
const size_t IC_TX_BUFFER_DEPTH = 16;
return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr;
}
 2022-03-21 12:07:03 +08:00
Petro Karashchenko
3fff4508c7 netinitialize: call xxx_netinitialize unconditionally 
The xxx_netinitialize is defined to a function only if
CONFIG_NET=y and CONFIG_NETDEV_LATEINIT=n.  Otherwise it
is defined to an empty macro.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-19 17:41:33 +08:00
Huang Qi
00efcd3308 arch/risc-v: Merge riscv_getnewintctx into common 
And also mask the bits which should be preserved (from ISA spec)

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-19 17:38:18 +08:00
Petro Karashchenko
20ac85860c config: finalize transition from USER_ENTRYPOINT to INIT_ENTRYPOINT 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-19 11:32:47 +08:00
Abdelatif Guettouche
aa84559566 xtensa_coproc.S: Replace spaces by tabs. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-19 01:09:22 +02:00
Abdelatif Guettouche
ce8fae2842 xtensa_coproc.S: Adjust the save reserved for local variables when 
restoring/saving coprocessor state.

These function don't use call8 or call12 and thus need to create just 16
bytes for the base save area, however they do use one variable so we
need a space for that.  The `entry` instruction works in unit of 8 bytes
so we add whole 8 bytes for one variable.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-19 01:09:22 +02:00
Gustavo Henrique Nihei
9ae826e925 xtensa/esp32s3: Fix output handling for pins numbered from 32 to 48 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-19 01:08:27 +02:00
Gustavo Henrique Nihei
f21a9f9578 xtensa/esp32s3: Enable UART pins to use IOMUX and bypass GPIO matrix 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-19 01:08:27 +02:00
Gustavo Henrique Nihei
77944ceb42 xtensa/esp32s3: Clean up and improve GPIO driver interface 
Also fix an inconsistenct regarding the ESP32S3_NGPIOS macro. Although
correctly defining the number of available GPIOs in ESP32-S3, it was
erroneously being used for verifying the pin range.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-19 01:08:27 +02:00
Gustavo Henrique Nihei
43b7d9b0da xtensa/esp32s3: Sync GPIO sigmap with IDF version 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-19 01:08:27 +02:00
Huang Qi
edef327655 arch/arm: Move ARCHCPUFLAGS to Toolchain.defs 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-19 02:24:00 +08:00
Petro Karashchenko
c1fb14ccaa boards/arm/samv7/same70-qmtech: add /dev/timer0 support 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-19 02:21:03 +08:00
Abdelatif Guettouche
2793e6f82d xtensa_releasepending.c: Remove commented out code. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-19 02:20:36 +08:00
Petro Karashchenko
6472a698b6 style/typo: fix few style and typo issues 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-18 17:05:10 +01:00
Janne Rosberg
d72a523c00 risc-v/mpfs: add support for ethernet 2022-03-18 17:22:27 +02:00
Janne Rosberg
07aeb12b30 risc-v/common: add call to riscv_netinitialize() 2022-03-18 17:22:27 +02:00
Eero Nurkkala
ec2352a4f9 risc-v/mpfs: usb: fix ep0 read done 
USB EP0 reads data from the fifo but doesn't mark the read
done which adds significant delays. Fix this unnecessary
slowdown due to operation timeouts by finishing the read
properly.

Also add a missing function description to the function
mpfs_ep_set_fifo_size().

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-03-18 22:47:29 +08:00
Ville Juven
15960f25a5 MPFS: Add board_memorymap.h 
Move the target specific memory map to a separate file so there is no
need to copy&paste the __xxram_start etc linker symbols to each file
that needs them.

Also add MMU flags for I/O and kernel areas, they will be needed
when the kernel runs with virtual addresses also.
 2022-03-18 09:35:00 -03:00
wangbowen6
7de7ba1b7e phy62xx_exception: using armv6-m exception_common code. 
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-03-18 20:01:00 +08:00
Ville Juven
ade848b60a MPFS: Use linker symbols for heap allocation 2022-03-18 18:20:12 +08:00
Ville Juven
75afe491ad RISC-V: Prepare for CONFIG_BUILD_KERNEL 
- Thread context prior to system call needs to be preserved
- Allocate a kernel heap
 2022-03-18 18:20:12 +08:00
Ville Juven
195705d11f MPFS: Create centralized module for PLIC address handling 
Reduce complexity and copy-paste amount by implementing a module
to handle calculating PLIC offsets.
 2022-03-18 18:20:12 +08:00
Ville Juven
745f00e77d MPFS: Use riscv_mhartid to obtain hartid 
Preparation for S-mode, read mhartid via function call instead of
directly from the machine mode register
 2022-03-18 18:20:12 +08:00
Ville Juven
f8ffcbbf36 MPFS: Remove definition and reference to MPFS_PLIC_CTRL 
The register does not exist. c906 implementation has it, but MPFS does not.
 2022-03-18 18:20:12 +08:00
Ville Juven
0f91eab626 MPFS: Protected mode, fix MMU mapping 
The mapped vaddr was wrong, don't want to map the page tables, but
the user space area (start of .text) instead.
 2022-03-18 18:20:12 +08:00
Ville Juven
9269a86d00 RISC-V: Add common data memory and instruction barriers 2022-03-18 18:20:12 +08:00
chao.an
19119a9c43 arch/arm: set the SP to stack top 
fix the stack imbalance

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-18 07:56:51 +09:00
Abdelatif Guettouche
5085f854d0 esp32(s3)_start.c: In SMP mode, don't disable APP CPU at startup. It starts in a 
disabled state and if OpenOCD is used this will clear OpenOCD configuration.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-17 14:33:32 -03:00
Abdelatif Guettouche
b98676f8be esp32(s3)_cpustart.c: Don't reset app CPU if it was already configured by 
OpenOCD.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-17 14:33:32 -03:00
Abdelatif Guettouche
b10c8955cf arch/Kconfig: Don't depend on Xtensa for the SUPPRESS_CLOCK_CONFIG 
option.  This config was probably added in the early bring up of the
ESP32 chip. At that point the clock config was suppressed and we relied
on the bootloader.  Now we can configure the clock from NuttX.

The option itself is still useful and can be used for any other
architecture or chip.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-17 14:33:12 -03:00
Xiang Xiao
c2a1d0f5ae procfs: Remove mallinfo from struct procfs_meminfo_entry_s 
let's call mm_mallinfo directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-17 13:59:03 -03:00
Gustavo Henrique Nihei
baa09aa999 risc-v/esp32c3: Remove deprecated option for disabling atomics support 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-17 23:40:29 +08:00
Huang Qi
807304f283 arch/risc-v: Rework riscv_get_newintctx 
Some fields of mstatus were marked as Reserved Writes Preserve Values, Reads Ignore Values (WPRI),
so we must keep its origin value with addition flags.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-17 15:43:30 +08:00
Petro Karashchenko
c3bae60c57 drivers/can: optimize can driver reader side 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-17 15:43:15 +08:00
Gustavo Henrique Nihei
39e9a17e60 xtensa/esp32s3: Apply style fixes throughout serial driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-16 19:06:39 -03:00
Gustavo Henrique Nihei
0dc2930403 xtensa/esp32s3: Remove code for not yet supported USB-Serial Driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-16 19:06:39 -03:00
Gustavo Henrique Nihei
57273ad994 xtensa/esp32s3: Fix IRQ setup hardcoded to CPU 0 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-16 19:06:39 -03:00
Huang Qi
9cc0a609bd arch/risc-v: Correct stack coloration in riscv_cpu_boot 
In smp system riscv_cpu_boot run in idle task so there is a overlap with the origin coloration range and in used stack.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-16 14:12:45 +02:00
SPRESENSE
c05ace557f arch: cxd56xx: Fix critical section in serial transmission 
Fix an issue that the serial transmission buffers are corrupted because
serial transmission are not protected by critical section in non-smp mode.
 2022-03-16 20:23:41 +09:00
Petro Karashchenko
985829190e arch/arm/samv7/sam_tc: implement timer driver support 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-16 03:19:57 +08:00
Eero Nurkkala
c38d547900 risc-v/mpfs: usb: fix ep0 stall/resume and rx reads 
Fix EP0 stall and resume properly. EP0 wasn't clearly addressed
on stall / resume operations.

Also fix data reads that provide garbage for the first request.
It has always random data as it's completed prior to any read
operation.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-03-16 00:59:25 +08:00
Ville Juven
e843c441de RISC-V: Fix nasty bug in PMP region test 
The end address was not handled correctly, it is not a part of a mapped
region.
 2022-03-15 18:59:20 +02:00
Matthew Trescott
8c471db932 Corrections to Tiva KConfig 2022-03-15 11:32:31 -04:00
Matthew Trescott
bc80bbddc7 Add Tiva CAN driver 2022-03-15 11:32:31 -04:00
chao.an
81130bc692 arch/arm: remove unused arm_copyfullstate/arm_copyarmstate 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-15 23:03:51 +09:00
chao.an
7b9978883c arch/arm: optimize context switch speed 
The current context save implementation saves registers of each task
to xcp context, which is unnecessary because most of the arm registers are
already saved in the task stack, this commit replace the xcp context with
stack context to improve context switching performance and reduce the tcb
space occupation of tcb instance.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-15 23:03:51 +09:00
Petro Karashchenko
b04447d066 timer_lowerhalf: minor improvements 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-15 10:30:48 +08:00
Xiang Xiao
b6bc460b2c arch: Make the comment and definition of CONFIG_SYS_RESERVED correctly 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 22:51:00 +02:00
chao.an
ea42981cc6 syscall/names: export the syscall name in STUB module 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 21:37:53 +02:00
chao.an
d398ffb930 arm/armv7-a/r: unified syscall registers dump 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 21:37:53 +02:00
chao.an
22e71e2d71 board/sim: add support of custom optimization level 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 23:25:26 +08:00
Abdelatif Guettouche
d21d02c65d xtensa_panic.S: Save exception cause and vaddr into the user frame. 
This area is what's passed later to assert and be used to dump the
state.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 19:54:30 +08:00
Abdelatif Guettouche
a9e3b5ae37 xtensa_panic.S: A2 is already saved by the caller, no need to save it 
here again.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 19:54:30 +08:00
chao.an
7c02432f0e arm/armv7-a/r: set the default CPU mode to System 
In SVC mode, the banked register will be inconsistent with the user mode register:

arch/arm/src/armv7-a/arm_vectors.S

 276   .globl  arm_syscall
 277   .globl  arm_vectorsvc
 278   .type arm_vectorsvc, %function
 279
 280 arm_vectorsvc:
...
 286   sub   sp, sp, #XCPTCONTEXT_SIZE        // < SVC mode SP
...
 308   stmia   r0, {r13, r14}^                // < USR mode SP/LR
...

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4
[    2.200000] [ 4] [ ALERT]   R0: 00000004 80001229 00000001 80202018 00000000 00000000 00000000 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 802027d0 1080f710 1080f710
[    2.200000] [ 4] [ ALERT] CPSR: 00000073
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 1 80202018 1 80202018 0 0 0 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 802027d0 1080f710 80001229
[    2.200000] [ 4] [ ALERT] CPSR: 00000070

SVC SP is 0x80202708
USR SP is 0x802027d0
0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51
[    2.200000] [ 4] [ ALERT]   R0: 00000033 00000000 80202780 00000000 00000000 00000000 00000000 80202710
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 80202710 800039d5 800039b2
[    2.200000] [ 4] [ ALERT] CPSR: 00000070
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 2b 0 80202780 0 0 0 0 80202710
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 10843d80 800039d5 10801425
[    2.200000] [ 4] [ ALERT] CPSR: 00000073

SVC SP is 0x80202708
USR SP is 0x80202710
SP overlap in SVC and USR mode

This commit change the default CPU mode to System and ensure the consistency of SP/LR in USR/SYS mode during syscall.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 19:54:53 +09:00
Xiang Xiao
54e630e14d arch: Merge up_arch.h into up_internal.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 09:32:17 +02:00
Xiang Xiao
e800f54bfd arch/mpfs: Don't include nuttx header file in mpfs_opensbi.c 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 09:32:17 +02:00
Abdelatif Guettouche
cff3d9df7b arch/xtensa: Fix some indentations. 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
6fa4a42e34 xtensa/: Save A3 as part of the regular context saving. 
It was separate because the syscal handler was using it before calling
_xtensa_context_save.  The order of operations has now changed and we
can save A3 with the rest of the context.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
4d1bb20f8c xtensa_user_handler.S: In syscall handler store context before 
continuing the rest of the syscall handling.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
5305f76b1d xtensa_context.S: Use Zephyr's version of spilling the window register 
file.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
2445de173d xtensa_dumpstate.c: Don't dump temporary registers. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
4786963ee2 xtensa_context.S: No need to save A2 before calling 
_xtensa_save_context.  It uses CALL0, in this case A1 is callee saved
and we can it directly.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
2dcbf28f15 xtensa_context.S: A1 should be restored by the caller not 
xtensa_context_resotred. Here it was being restored twice.
Remove the one in xtensa_context_restore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
5bd2e97a27 xtensa_context.S: Fix the type of _xtensa_context_restore. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00