As proposed by David Sidrane. Required drive strength is board specific
and should be defined in the respective board.h file.
Signed-off-by: Michael Jung <mijung@gmx.net>
Architecture support for STMicroelectronics STM32L552xx and STM32L562xx
MCUs. This is based on corresponding code for STM32L4, but has been
considerably adjusted. Tested with Nucleo-L552ZE-Q and STM32L562E-DK
boards with simple NSH configurations.
Signed-off-by: Michael Jung <mijung@gmx.net>
Alan Carvalho de Assis has submitted the SGA and we can migrate the licenses
to Apache.
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
mmcsd:Remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
stm32h7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
stm32f7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
stm32f7:sdmmc WRITE COMPLETE prevent false triggers
stm32h7:sdmmc WRITE COMPLETE prevent false triggers
While testing PR #2989 on the H7 I noticed that the cards
were staying in 1-bit mode. The root cause was that the
scr read path was using DMA without an invlidate.
This was caused by CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT,
but the sdmmc driver, did not use the delayed invalidate
nor would it work on 8 bytes.
The driver fully supported dcache mgt on runt buffers, but
the #ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT blocked it.
Reviewing the PR that added CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
it may have been valid at the time. But after the dcache operations
we fixed. It is not necessary and offers no benefit.
Summary:
- This commit fixes an error message in imx_enet.c
Impact:
- None
Testing:
- Build only
Suggested-by: David Sidrane <David.Sidrane@NscDg.com>
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds CPU activity LED feature to cxd56_idle.c and cx56_irq.c
- An LED for the current CPU will turn off before calling WFI
- An LED for the current CPU will turn on when an interrupt happens
Impact:
- CONFIG_ARCH_LEDS_CPU_ACTIVITY=y only
Testing:
- defconfigs will be commited later.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- The original commit was added to avoid hardfault but the
root cause was the stack corruption which has been fixed by
the previous commit. So let me revert the original commit.
Impact:
- SMP only
Testing:
- spresense:rndis_smp with nxplayer + telnet
This reverts commit 197187d826.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes hardfault when running nxplayer with rndis_smp
Impact:
- SMP only
Testing:
- Tested with rndis_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
In scenarios where there is suspicion that someone might be touching your data when you don't expect, you can setup a watchpoint, and then guard accesses that you know are valid. If the debugger halts due to the watchpoint, you'll see where the unexpected access is coming from.
Implement si_send/sendto/recvfrom with si_sendmsg/recvmsg, instead of
the other way round.
Change-Id: I7b858556996e0862df22807a6edf6d7cfe6518fc
Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
Bug description:
CONFIG_SMP=y
Suppose we have 2 cores in SMP, here is the ps return:
PID GROUP CPU PRI POLICY TYPE NPX STATE STACK USED FILLED COMMAND
0 0 0 0 FIFO Kthread N-- Assigned 004076 000748 18.3% CPU0 IDLE
1 0 1 0 FIFO Kthread N-- Running 004096 000540 13.1% CPU1 IDLE
nsh> kill -4 0
or:
nsh> kill -4 1
system blocked.
Reason:
In func xx_sigdeliver() restore stage, when saved_irqcount == 0, that means
rtcb NOT in critical_section before switch to xx_sigdeliver(), then we need
reset the critical_section state before swith back.
Fix:
Add condition to cover saved_irqcount == 0.
Change-Id: I4af7f95e47f6d78a4094c3757d39b01ac9d533b3
Signed-off-by: ligd <liguiding1@xiaomi.com>
This Knob will cycle through the values from
low to high. To avoid damaging the crystal.
We want to use the lowest setting that gets
the OSC running. See app note AN2867
This Knob will cycle through the correct*
values from low to high. To avoid damaging
the crystal. We want to use the lowest setting
that gets the OSC running. See app note AN2867
*It will take into account the rev of the silicon
and use the correct code points to achive the drive
strength. See Eratta ES0392 Rev 7 2.2.14 LSE oscillator
driving capability selection bits are swapped.
With TrustZone support in armv8-m the bit-fields in EXC_RETURN have been
extended. Bit 6 ('S') now specifies whether the interrupted program was
running in the Non-Secure (S=0) or Secure (S=1) security state.
Furthermore, Bit 0 ('ES' - Exception Secure) specifies the
security state athe exception is taken to (0: Non-Secure, 1: Secure).
When NuttX is run together with TrustedFirmware-M as the application in
the non-secure world both the S and the ES bits have to be set to '0'.
For armv8-m those are also the correct values if TrustZone is not
implemented on the respective MCU or if it is disabled.
Signed-off-by: Michael Jung <mijung@gmx.net>
Summary:
- This commit applies armv7-m signal handling logic
Impact:
- armv6-m signal handling
Testing:
- Tested with ostest with the following configs
- raspberrypi-pico:nsh, raspberrypi-pico:smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
