Update PLL configuration parameters to match the values provided
by the vendor.
Also remove extra call to mpfs_pll_config() as it's already called
at mpfs_clockconfig().
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This patch adds corrected implementation of FLASH memory to be used
with progmem driver for use with mtd filesystems like nxffs or smartfs.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
Summary:
- I noticed that QEMU shows a high CPU load.
- This commit re-adds imx_idle.c to avoid this issue.
Impact:
- None
Testing:
- Tested with sabre-6quad:smp with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This patch implements working support for EXTI GPIO.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
--
v1 -> v2:
Suggested by: Petro Karashchenko
- change (1 << n) to (1 << (n)) in macro definition
- change 1 << X to (1 << X) in code
- fix alignment
v2 -> v3:
Suggested by: Petro Karashchenko
- I was supposed to change (1 << pin) to 1 << pin, not the other way around:)
Summary:
- I noticed that sometimes uart shows nothing on the maix-bit board.
- This commit adds a workaround to avoid such the issue
Impact:
- k210 only
Testing:
- Tested with maix-bit
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This provides USB composite (CDC/ACM and Mass Storage) support
for mpfs board. In addition, a number of USB fixes are included:
- Support for Setup Out packets
- Proper support for larger than packet size writes
- Finishing setup packets properly
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Output "X" with showprogress and make a system reset.
Silently ignoring failed training is dangerous and will cause random behaviour if DDR is used
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This patch adds new chip family, stm32wl5x. This is bare minimum
implementation of said chip. I've tested this by running nsh.
There are only two chips in this family, stm32wl55 and stm32wl54.
The only difference between them is that stm32wl55 has LORA.
stm32wl5 is dual CPU (not core!). Right now only CPU1 is implemented.
CPU0 has access to radio hardware (while CPU1 does not). Chip is
designed so that CPU0 handles radio traffic while CPU1 does the
heavy lifting with data - there is communication pipe between two
CPUs.
I plan to use nuttx on CPU1 and LORA from stm32cube on CPU0 so I
don't have implementing CPU0 right now - once we have working LORA
in nuttx this may change.
Peripherals (except for radio) are shared so it's best to focus on
CPU1 to initialize all peripherals so that CPU0 can only use them
later. There is no real benefit to implement CPU0 if we don't have
working LORA/radio support in nuttx.
In time I will be implementing more and more things from this chip.
Right now I would like this minimal implementation to be merged in
case someone wants to work on this chip as well.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
---
patch v1->v2
- fixed formatting (suggested by Alan Carvalho de Assis)
- rebased patch to master (previous patch was based on nuttx-10.2
and did not compile on master)
arch/x86/Kconfig:28:warning: choice value used outside its choice group
arch/x86/Kconfig:29:warning: defaults for choice values not supported
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
We might have a situation where an allocation will be requested before
the call to `up_initialize` is performed. For the current code, this
situation is the stack for the CPUs in SMP mode.
Beside this issue, it's natural to have the internal heap initialized
with the other heaps.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
jumping back to the assembly signal trampoline and getting into its
infinite loop.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Change pin initialization timing for camera from board power on to camera device
power on for the following purposes.
- avoid unnecessary power consumption
- Make the corresponding pins available for other uses when camera is not in use
RF and system timer interrupt are used for ble.
tlsr82_flash.c:
1. BLE will loss packets during flash operation beacause the interrupt
is disabled and the operation take too long (especially erasing,
about 100ms), so allow RF and system timer interrupt during flash
operation;
2. Add sched_lock()/sched_unlock() to avoid the task switch in ble and
system timer interrupt;
flash_boot_ble.ld:
3. Because of 1, the code executes in RF and system timer interrupt
must be in ram to avoid bus error. The sem_post() will be called and
const variable g_tasklisttable will be accessed in RF and system
timer interrupt handler;
4. To improve the performance, copy some frequently called function to
ram as well, such as: sem_take(), sched_lock(), sched_unlock(),
some lib functions, some zephyr ble functions and some tinycrypt
functions;
5. The RF and system timer interrupt handler will call some libgcc
functions, so copy all the libgcc functions to ram exclude _divdi3.o,
_udivdi3.o and _umoddi3.o;
tlsr82_serial.c
6. Make up_putc() be thread safe, add enter/leave_critical_section() in
function uart_send_byte();
tc32_doirq.c
7. Increase the RF and system timer interrupt response priority;
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
since the code could map the unsupported work to the
supported one and remove select SCHED_WORKQUEUE from
Kconfig since SCHED_[L|H]PWORK already do the selection
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
As coproc_save/restore only used in context_restore/save.
Use macro instead of function.
Some register use optimize.
Unify with arm/riscv.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
The current SAMv7 PWM driver assumes that all PWM channels should
work in sync mode, but that is a partial case of a generic PWM
driver operation.
Start SAMv7 PWM channels in async mode. The sync mode should be
implemeted either using ioctl command or via a separate Kconfig
option.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Linux kernel uses M-mode trap for handling Inter-Hart Communication (IHC).
This patch provides all the required functionalities for this purpose.
Previously, HSS bootloader was required. Now, NuttX is run as the
bootloader providing OpenSBI vendor extensions instead. This setup has
been tested on the following configuration:
- Hart 0 has NuttX in bootloader mode with OpenSBI
- Hart 1 unused
- Hart 2 has NuttX configured at 0xa2000000
- Hart 3 has U-boot / Linux kernel (at 0x80200000)
- Hart 4 has U-boot / Linux kernel (at 0x80200000)
Upon startup, NuttX on hart 0 will initialize SD-card driver, loads
the hart 2 NuttX from the SD-card and loads the U-boot to 0x80200000.
Also the nuttx.sbi -binary is loaded from SD-card into address 0x80000000,
which is also marked as reserved area in the Linux kernel device tree (for
the chuck 0x80000000 - 0x80200000).
Hart 2 NuttX waits until Linux kernel (IHC master) is started. After the
initial handshake, RPMsg / virtIO bus along with the IHC may be used for
proper AMP mode.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Summary:
- I noticed that rv-virt:knsh64 crashes when it executes the init.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with rv-virt:knsh64
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
1. Add vbat mode for chip internal voltage sample;
2. Add adc channel config;
3. Using DFIFO2 to get the sample value, follow telink sdk.
4. Add calibration function and config;
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
The FPU register saving upon vfork entry was missing.
Also added macro that tells the actual size of an FPU reg, instead
of just having a coefficient for qfpu/no-qfpu.
- Remove most of the ifeq-conditions and replace them with variables.
- Move the -I flag for 3rd party headers to opensbi/Make.defs
This clean-up / generalization makes it much simpler to add a new SBI
implementation, without the need to add a bunch of ifeq / elif conditions
to the makefile.
Let the user pick what runs on the harts. For example, the
default configuration now supports NuttX on hart2 and Linux
kernel on harts 3 and 4. Also fix a few issues in the code.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
g_mpfs_ack_sig and g_mpfs_rx_sig are better used with
SEM_INITIALIZER(0) (signalling) rather than with
SEM_INITIALIZER(1) (mutual exclusion).
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Number of channels are now set based on enabled modules (channels) in
configuration instead of the usage of static 4.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Number of channels are now set based on enabled channels in configuration
instead of the usage of static 4.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
1 move fpu register to XCP_REGS
2 move save & restore fpu register to context_save/restore
Consistency with other archs.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
PR#6249 was already merged without the review fixes. Provide the
fixes here on a separate patch.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Summary:
- This commit adds MMU support for qemu-rv
- Please note that mtimer is disabled for S-mode because
the mtimer needs to be accessed in M-mode
Impact:
- qemu-rv only
Testing:
- Tested with rv-virt:knsh64 (will be pushed later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This provides an example of Asymmetric Multiprocessing (AMP). The
master from Linux sends pings that this NuttX echoes back. The system
uses RPMsg from OpenAMP.
The Inter-Hart Communication module is present in the vendor's software
stack with the tag "2021.11". The software is present on github at the
polarfire-soc project. The following conditions must be met:
1. FPGA programmed with 2021.11 software
2. HSS (Vendor bootloader) with 2021.11 software
3. U-boot and Linux kernel from 2011.11 software
Currently the IHC works as a slave only on the hart number 4.
On the NuttX side, this patch uses rptun that incorporates rpmsg and
virtio. If it used only rpmsg and virtio, the future maintenance would
likely be much heavier. Using rptun also simplifies many things.
Upon success, the master side from Linux may issue an example test:
root@icicle-kit-es-amp:/opt/microchip/amp/rpmsg-pingpong# ./rpmsg-pingpong
However, the rpmsg-pingpong.c (compiled on target with gcc), may need to
be modified as seen below to match the device id:
- char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.0";
+ char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.1024";
This work uses a separate linker script. Due to a bug yet unknown to date,
a small NuttX, when loaded by the vendor HSS bootloader, will cause the
Linux kernel to hang at boot. Thus, the binary size is increased with
a section 'filler_area' whose only purpose is to increase the image size
so that the Linux kernel will boot up.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Implement a generic access rights modification procedure instead
of the procedures that only do one thing (enable/disable write)
to one section (text).
1. using armv6-m arm_irq();
2. simplify the interrupt number get process;
3. To improve the performance, move common exception code to ram_code.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
fix warning:
common/arm_createstack.c: In function 'up_create_stack':
common/arm_createstack.c:154:11: warning: format '%d' expects type 'int', but argument 3 has type 'size_t'
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Summary:
- Because a context switch issue still exists with FPU,
it should be enabled only if EXPERIMENTAL=y
Impact:
- None
Testing:
- Tested with ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
1. add pulse count support for pwm0;
2. add more detailed config for pwm;
3. pwm configuration and start process optimize;
4. tlsr82/Kconfig format;
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Summary:
- TIVA_WITH_QEMU is used to run the NuttX with QEMU
- The configuration should not depend on TIVA_ETHERNET
- This commit fixes this issue
Impact:
- None
Testing:
- Tested with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
_xtensa_sig_trampoline is returned to after a context switch and not called
by the usual Window call instructions (call4, call8 and call12),
thus does not need the entry instruction. Furthermore, the ENTRY instruction
in this case is messing up the backtrace as it creates an extra frame.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
to generate more information for profile feedback optimization
and remove -lgcov from STDLIBS since gcc/clang will automatically
add the profile help lirary(triggered by -fprofile-generate).
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Summary:
- In case of SMP and ADDRENV, allocate the page table for each cpu
- Each cpu holds separated addrenv and MMU setting
Impact:
- armv7-a
Testing:
- sabre-6quad:smp w/ qemu
- sabre-6quad:knsh w/ qemu
- sabre-6quad:knsh_smp w/ qemu (WIP)
Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
Note that pinmap.h, irq.h, fdcan.h still need to be updated with proper
register definitions for the FDCAN3 peripheral present in
STM32H7[2|3][3|5] MCUs
Adds stubs for up_addrenv_text_enable/disable_write. These don't have
to do anything as the ARM MMU allows setting access per mode. Currently
the settings for user .text area grants the kernel write access, but
revokes user write access.
When the .elf file is loaded from disk, the kernel must be given write
access to the allocated .text section in the task's address environment.
The access is removed after the elf is loaded and relocations are done.
NOTE:
The reason this works for the ARM implementation, is that the ARM MMU
can be configured to give write access for the privileged mode, but
revoke write access for the user mode.
Regardless, it would be smart to revoke write access even for the
kernel, when the kernel does not need it. This framework allows doing
that, if someone wishes to take up the task.
Summary:
- The stack pointer is subtracted to alloc xcptcontext area
in the __cpu?_start block
- Fix the stack coloration overrun to the previous cpu's xcpt area
Impact:
- armv7-a's smp configuration
Testing:
- smp and ostest on sabre-6quad:smp w/ qemu
Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
Summary:
- This commit adds support for semihosting and hostfs
Impact:
- None
Testing:
- Tested with nsh and nsh64 (defconfig will be updated later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Mappings are done with vaddr=paddr.
- I/O space mapped with two gigapages
- Kernel space mapped to statically allocated page tables. 2MB of kernel
memory is supported.
- Page pool is mapped to the kernel space, to allow virtual memory access
for the kernel e.g. to initialize the page memory when it is allocated.
by renaming riscv_dispatch_syscall to sys_callx, so the caller
don't need the immediate step(syscallx->riscv_dispatch_syscall)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Summary:
- Use CPS instruction to change cpu mode for code simplification
- CPS which changes cpu mode is available in armv6 and above
Impact:
- armv7-a/r
Testing:
- smp and ostest on sabre-6quad:smp w/ qemu
Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
Using the Kconfig macro does not work for RISC-V target, as there the
user heap follows .data/.bss and does not obey any Kconfig provided
boundary.
Added stubs for ARM and Z80 also.
Copy the kernel mappings to the new (user) address environment. The
copyuing is done exactly once. This relies on the fact that the kernel
L1/L2 mappings will never change, as all of the kernel memory is mapped
upon boot.
This implements initial support for kernel build (address environments,
page allocator) for RISC-V.
This is done a bit differently compared to the ARMV7 implementation:
- Support implemented for Sv39 MMU, however the implementation should be
extensible for other MMU types also.
- Instead of preserving and moving the L1 references around, a canonical
approach is used instead, where the page table base address register
is switched upon context switch.
- To preserve a bit of memory, only a single L1/L2 table is supported,
this gives access to 1GiB of virtual memory for each process, which
should be more than enough.
Some things worth noting:
- Assumes page pool is mapped with vaddr=paddr mappings
- The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are
ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used
for ARCH_DATA_RESERVE
- ARCH_DATA_RESERVE is placed at the beginning of the userspace task's
address environment
common/arm_assert.c:80:14: warning: format specifies type 'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned long') [-Wformat]
stack, ptr[0], ptr[1], ptr[2], ptr[3],
^~~~~
include/debug.h:119:59: note: expanded from macro '_alert'
__arch_syslog(LOG_EMERG, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
~~~~~~ ^~~~~~~~~~~
Signed-off-by: chao.an <anchao@xiaomi.com>
Summary:
- I noticed that maix-bit:smp does not work with QEMU.
- Actually, QEMU supports sifive_u (not K210) but it works
if FPU is disabled.
- This commit fixes this issue.
Impact:
- K210 with QEMU only
Testing:
- Tested with qemu-5.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Selecting this option will pass "-Map=$(TOPDIR)$(DELIM)nuttx.map" to ld
when linking NuttX ELF. That file can be useful for verifying
and debugging magic section games, and for seeing which
pieces of code get eliminated with DEBUG_OPT_UNUSED_SECTIONS.
Signed-off-by: chao.an <anchao@xiaomi.com>
Enable this option to optimization the unused input sections with the
linker by compiling with " -ffunction-sections -fdata-sections ", and
linking with " --gc-sections ".
Signed-off-by: chao.an <anchao@xiaomi.com>
This PR resolved 2 issues:
1. CURRENT_REGS is not set correctly on swint handling
2. group env is not changed properly
Signed-off-by: chao.an <anchao@xiaomi.com>
since it is broken and inefficient, and then removed by:
commit dc961baaea
Author: chao.an <anchao@xiaomi.com>
Date: Thu Apr 14 18:07:14 2022 +0800
arm/armv7-[a|r]: move fpu save/restore to assembly handler
Save/Restore FPU registers in C environment is dangerous practive,
which cannot guarantee the compiler won't generate the assembly code
with float point registers, especially in interrupt handling
Signed-off-by: chao.an <anchao@xiaomi.com>
commit 8d66dbc068
Author: chao.an <anchao@xiaomi.com>
Date: Thu Apr 7 13:48:04 2022 +0800
arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only
Signed-off-by: chao.an <anchao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Save/Restore FPU registers in C environment is dangerous practive,
which cannot guarantee the compiler won't generate the assembly code
with float point registers, especially in interrupt handling
Signed-off-by: chao.an <anchao@xiaomi.com>
Otherwise we will try to dump the state of the current task, however the
exit handler has already started doing some cleanup and invalidated its
group. Accessing the group from dumponexit will crash.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
"error: incompatible types when assigning to type 'struct filelist *' from type 'struct filelist'
filelist = tcb->group->tg_filelist;"
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
If source register of sw instruction is x0, we must point it to a constant zero
since in NuttX's context,
value of index 0 is EPC.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Hartid and cpuindex are not the same thing. Hartid is needed regardless
of SMP, for external interrupt handling etc.
SMP needs cpuindex which might not be index == hartid, so both are
needed. IMO it is clearer to provide separate API for both.
Currently the implementation of up_cpu_index is done a bit lazily,
because it assumes hartid == cpu index, but this is not 100% accurate,
so it is still missing some logic.
chip/c906_timerisr.c: In function 'up_timer_initialize':
Error: chip/c906_timerisr.c:71:3: error: implicit declaration of function 'DEBUGASSERT' [-Werror=implicit-function-declaration]
DEBUGASSERT(lower);
^~~~~~~~~~~
cc1: all warnings being treated as errors
Signed-off-by: chao.an <anchao@xiaomi.com>
riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.
Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
IRQ_NSTACKS, ARCH_CPU_COUNT, CONFIG_SMP_NCPUS all relate to each
other. However, a bit of clean up can be done and everything can
be merged into SMP_NCPUS.
The MPFS bootloader case works also as it requires only 1 IRQ stack
for the hart that executes as bootloader.
Some risc-v based chips don't support unaligned data access,
it will trigger a exception and then lead to crash.
In this patch, we handle the misaligned access by software to make
system run continue.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
ESP32C3 use customized irq encoding so it's hard to share further code
with other risc-v based chips, in this patch, we keep the exception
number definition with risc-v spec.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
- Access to PLIC via S-mode registers
- Access to IRQs via S-mode registers / definitions
- Initialize S-mode registers upon boot
- Initialize per CPU area before nx_start
NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
thus S-mode is not usable as is, yet.
Remove riscv_fault since its code is duplicated with riscv_exception,
and there are textual excpetion reason in riscv_exception.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Fix stm32_stdclockconfig for stm32u585xx to the extend that the
B-U585I-IOT02A board's clock tree can be configured. This board uses
the MSIS as PLL1's input clock and the LSE to autotrim the MSIS.
It might be useful to store things in memory per CPU. The tricky part
is that all CPUs run the same code and see the same memory, so some
kind of centralized access is required.
For now, the structure contains the hart id.
Access to the structure elements is provided via sscratch, which is
unique for every hart!
- Add config "ARCH_USE_S_MODE" which controls whether the kernel
runs in M-mode or S-mode
- Add more MSTATUS and most of the SSTATUS register definitions
- Add more MIP flags for interrupt delegation
- Add handling of interrupts from S-mode
- Add handling of FPU from S-mode
- Add new context handling functions that are not dependent on the trap
handlers / ecall
NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
thus S-mode is not usable as is, yet.
glibc 2.34 changed the dynamic linker behavior during the startup
process, which makes the previous "__init_array_start" replacement trick
non-effective.
Now the dynamic linker parses the constructors/destructors information
from the DYNAMIC segment of the program.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
When process a is switched to process b, the address environment is
swapped with a call to group_addrenv(). The stack upon entry will be
a's, and upon exit b's. This will fail, so a neutral stack is required,
either a kernel stack or an IRQ stack.
Infrastructure for an IRQ stack is already in place, so give a hint
that an interrupt stack should be provided if address environments
are enabled.
This is required to avoid the interface header (syscall.h) depending on
the xtensa_swi.h header from the implementation
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
## Summary
`bl602_spi_cmddata()` implements SPI Cmd/Data `SPI_CMDDATA()` for only 3 LCD drivers: ST7735, ST7789 and GC9A01.
This patch removes the check for LCD drivers, so that SPI Cmd/Data will work for all LCD drivers.
More details: https://github.com/apache/incubator-nuttx/pull/5898
## Impact
This change impacts LCD drivers that call `SPI_CMDDATA()`.
Previously `SPI_CMDDATA()` would fail with `ENODEV` for LCD drivers other than ST7735, ST7789 and GC9A01.
After patching, `SPI_CMDDATA()` will work correctly with all LCD drivers.
## Testing
We tested with LVGL and ST7789 on PineCone BL602:
- [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)
As for regular SPI Devices that don't require SPI Cmd/Data, we tested `CONFIG_SPI_CMDDATA=y` with Semtech SX1262 SPI Transceiver on PineCone BL602:
- [Testing Cmd/Data](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-30)
The SPSR is used to store the current value of the CPSR when an exception
is taken so that it can be restored after handling the exception.
Each exception handling mode can access its own SPSR.
User mode and System mode do not have an SPSR because they are not
exception handling modes.
Signed-off-by: chao.an <anchao@xiaomi.com>
## Summary
To control the Data/Command Pin on ST7789 SPI Display, the SPI Driver flips the MISO Pin as though it was a GPIO.
To implement this on BL602, we reconfigure MISO from SPI Pin to GPIO Pin on the fly inside `bl602_spi_cmddata()`.
When the SPI Port is deselected (after the SPI operation), we revert MISO back from GPIO Pin to SPI Pin. We implement this inside `bl602_spi_select()`.
[More Details Here](https://github.com/lupyuen/st7789-nuttx#spi-cmddata)
## Impact
This change impacts 3 LCD drivers that call `SPI_CMDDATA()`: ST7735, ST7789, GC9A01.
Previously the BL602 SPI Driver would fail with "SPI cmddata not supported" when the above drivers are used.
After the change, the above drivers will set the LCD Data/Command Pin correctly.
## Testing
We tested this implementation of SPI Cmd/Data with NuttX ST7789 Driver and a Logic Analyser on PineCone BL602:
- [Testing with Logic Analyser](https://github.com/lupyuen/st7789-nuttx#spi-cmddata)
We also tested LVGL with ST7789 on PineCone BL602:
- [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)
As for regular SPI Devices that don't require SPI Cmd/Data, we tested `CONFIG_SPI_CMDDATA=y` with Semtech SX1262 SPI Transceiver on PineCone BL602:
- [Testing Cmd/Data](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-29)
As xtensa timer is common in all xtensa chips,
Use oneshot ops, implement a common xtensa oneshot timer.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
