Commit Graph

1286 Commits

Author SHA1 Message Date
Jukka Laitinen
c269adbff1 arch/risc-v/src/mpfs/mpfs_ddr.c: Correct erroneous register addresses in DDR training
Writes to MPFS_CFG_DDR_SGMII_PHY_EXPERT_DFI_STATUS_OVERRIDE register were not done properly. Use correct address for writes.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-07-18 10:11:10 -03:00
Eero Nurkkala
b79671a336 risc-v/mpfs: emmcsd: fix csd read
Reading the CSD field misses 3 bytes as the residual bytes
are not carried over properly. Fix this by adding the missing
bytes due to shifting.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-07-17 23:05:37 +08:00
Xiang Xiao
abfe082a6f Kconfig: Simplify the conditional default statement
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-07-16 14:39:20 -03:00
simbit18
d991ef77e8 Fix nuttx coding style
Remove TABs
Fix indentation
2023-07-14 20:48:24 +08:00
simbit18
b0965ab963 Fix nuttx coding style
Remove TABs
Fix indentation
Fix Multi-line comments
Fix Comments to the Right of Statements.
2023-07-14 01:16:06 +08:00
simbit18
1b1ac6f3b7 Fix nuttx coding style
Remove TABs
Fix indentation
Fix Multi-line comments
Fix Comments to the Right of Statements.

Fix nuttx coding style

Fix Comments to the Right of Statements.
2023-07-13 19:30:56 +08:00
guoshichao
c33d1c9c97 sched/task/fork: add fork implementation
1. as we can use fork to implement vfork, so we rename the vfork to
fork, and use the fork method as the base to implement vfork method
2. create the vfork function as a libc function based on fork
function

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2023-07-12 02:27:37 +08:00
tjwu1217
4969f8faf9 risc-v Toolchain.defs compatibility.
Reference:https://xpack.github.io/blog/2022/05/18/riscv-none-elf-gcc-v12-1-0-2-released/

RISC-V ISA updates

Compared to previous releases, starting from 12.x, the compiler implements the new RISC-V ISA, which introduces an incompatibility issue, and builds might throw error messages like unrecognized opcode csrr.

The reason is that csr read/write (csrr*/csrw*) instructions and fence.i instruction were separated from the I extension, becoming two standalone extensions: Zicsr and Zifencei.

The solution is to add _zicsr and/or _zifencei to the -march option, e.g. -march=rv32imac becomes -march=rv32imac_zicsr_zifencei.
2023-07-01 13:19:30 +08:00
Jani Paalijarvi
78a2c91a04 risc-v/mpfs: cache: Fix cache and scratchpad init
Initialize ICACHE way with correct mask.
Initialize scratchpad with constant g_init_marker as it has been done in HSS

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2023-06-30 20:19:54 -03:00
Stuart Ianna
5b00c31396 boards/litex/arty_a7: Support building fully linked executables.
Changes the executable type built against the `make export` target fully linked by default. This greatly improves performance when loading applications, as relocations no longer need to be processed.
2023-06-28 15:16:28 +08:00
Lucas Saavedra Vaz
9bd1d5ddda arch/risc-v/espressif: Add USB-Serial-JTAG driver
Add support for USB-Serial-JTAG on ESP32-C3/C6/H2 using the Espressif HAL
2023-06-28 08:47:55 +08:00
Stuart Ianna
d94013837e risc-v/litex: Improve ethernet packet reception.
In the default configuration, the Litex ethernet peripheral contains two RX and two TX buffers. The active buffer for the peripheral should be swapped as soon as possible, in order to reduce packet loss.

This modification acknowledges the receive buffer as soon as the pending data is copied into the NuttX device data buffer. Improving reliability under heavy load.
2023-06-27 03:33:40 +08:00
Lucas Saavedra Vaz
8aeba210e4 arch/risc-v/espressif: Add full GPIO support
Full GPIO support using Espressif's HAL
2023-06-24 13:11:45 +08:00
Stuart Ianna
2db6ea9984 litex/gpio: Fix incorrect declaration name. 2023-06-23 12:29:59 +08:00
Xiang Xiao
0eeca0f375 build: Replace "$(shell $(INCDIR) $(CC) ...)" with $(INCDIR_PREFIX)
to unify the way to get include directories

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-06-23 00:11:25 +03:00
Masayuki Ishikawa
c5641b0252 Revert "riscv/swint: Give the full tcb to the context switch routine"
This reverts commit 040eb3c990.
2023-06-20 06:17:11 +09:00
Masayuki Ishikawa
2c6ad5c2bf Revert "riscv/fpu: Restore correct lazy-FPU functionality"
This reverts commit 35c27b5a9a.
2023-06-20 06:17:11 +09:00
Masayuki Ishikawa
9d84d79b29 Revert "riscv/saveusercontext: Fix FPU state save"
This reverts commit 669196910c.
2023-06-20 06:17:11 +09:00
Masayuki Ishikawa
0124533cc3 Revert "riscv/addrenv: Move addrenv_switch() to correct place after FPU change"
This reverts commit da319bbd85.
2023-06-20 06:17:11 +09:00
Masayuki Ishikawa
7410f4a6b8 Revert "riscv/lazyfpu: Add option to disable lazy FPU"
This reverts commit 425cc89989.
2023-06-20 06:17:11 +09:00
simbit18
3f4151525d Fix Kconfig style
Remove TABs from Kconfig files
Add comments
2023-06-19 20:05:57 +03:00
Ville Juven
425cc89989 riscv/lazyfpu: Add option to disable lazy FPU
Adds option to use the old implementation where FPU is stored into
the process stack.
2023-06-19 19:28:07 +08:00
Ville Juven
da319bbd85 riscv/addrenv: Move addrenv_switch() to correct place after FPU change
The new address environment must be instantiated prior to restoring FPU
state as the CPU status register is in tcb->regs, which is user stack.
2023-06-19 19:28:07 +08:00
Ville Juven
669196910c riscv/saveusercontext: Fix FPU state save 2023-06-19 19:28:07 +08:00
Ville Juven
35c27b5a9a riscv/fpu: Restore correct lazy-FPU functionality
- Save the FPU registers into the tcb so they don't get lost if the stack
  frame for xcp.regs moves (as it does)
- Handle interger and FPU register save/load separately
- Integer registers are saved/loaded always, like before
- FPU registers are only saved during a context switch:
  - Save ONLY if FPU is dirty
  - Restore always if FPU has been used (not in FSTATE_OFF, FSTATE_INIT)
- Remove all lazy-FPU related logic from the macros, it is not needed
2023-06-19 19:28:07 +08:00
Ville Juven
040eb3c990 riscv/swint: Give the full tcb to the context switch routine
Why? The tcb can contain info that is needed by the context switch
routine. One example is lazy-FPU handling; the integer registers can
be stored into the stack, because they are always stored & restored.

Lazy-FPU however needs a non-volatile location to store the FPU registers
as the save feature will skip saving a clean FPU, but the restore must
always restore the FPU registers if the thread uses FPU.
2023-06-19 19:28:07 +08:00
Eero Nurkkala
4494e75e87 risc-v/mpfs: add CoreMMC support
This adds support for the CoreMMC v3.1 FPGA driver as described
in Microchip Handbook HB0510. The driver doesn't support DMA.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-06-19 19:24:51 +08:00
Tiago Medicci Serrano
17c65d2067 risc-v/espressif: use the unquoted CHIP_SERIES variable
Instead of using `CONFIG_ESPRESSIF_CHIP_SERIES`, use the unquoted
version `CHIP_SERIES`.
2023-06-16 11:14:36 +08:00
Tiago Medicci Serrano
6559ac4034 risc-v/espressif: update to the newest esp-hal-3rdparty version
Also, get esp-hal-3rdparty by git cloning (instead of downloaded)
to enable getting its git submodules.
2023-06-16 11:14:36 +08:00
Ville Juven
9b5746cb5f riscv/barrier: Define more granular memory barriers
Separate barriers for full (memory + I/O) and local memory (cache) flushing.
2023-06-14 16:14:57 -03:00
Huang Qi
84f4cf9b9d riscv/vfork: Replace jal with call for long jump
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-06-14 02:01:04 +08:00
chao an
2369e3cbc8 arm/dataabort: fix compile warning
Error: arm/arm_dataabort.c:146:10: error: format '%x' expects argument of type 'unsigned int',
                                          but argument 3 has type 'uint32_t' {aka 'long unsigned int'} [-Werror=format=]
  146 |   _alert("Data abort. PC: %08x FAR: %08x FSR: %08x\n",
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  147 |          regs[REG_PC], far, fsr);

Signed-off-by: chao an <anchao@xiaomi.com>
2023-06-12 13:36:08 +08:00
Xiang Xiao
da5e978341 mm: Correct the callsite of mm_mallinfo
forget to update in https://github.com/apache/nuttx/pull/9488

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-06-11 19:37:04 +03:00
Xiang Xiao
d920bfba10 mm: include malloc.h in mm/mm.h
to remove the forward declaration of mallinfo and mallinfo_task

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-06-11 19:37:04 +03:00
Ville Juven
37bf542c9e mpfs/mpfs_shead.S: Remove MMU mappings and flush TLB upon boot
This fixes warm reset crash when trying to access memory via old stale
MMU mappings
2023-06-10 01:36:59 +08:00
Ville Juven
7bc8e59cce riscv/kernel_stack: Use kernel stack to store the user context
If a kernel stack exists, use that whenever the user process is in
privileged mode, i.e. running an exception or in system call. Previously
the exception context was stored into the user's stack, which is not ideal.

Why?

1. Because the exception entry status (REG_INT_CTX) is needed by the
   kernel, and this is now in user memory which requires that the correct
   user mappings are active when it is accessed.

2. The user must currently account for the exception stack frame (which
   is BIG) in its own stack allocation. Moving the exception context save
   to the kernel stack offloads this responsibility from the user to the
   kernel, which is IMO the correct behavior.

3. The kernel access to user memory is currently allowed without condition,
   however this is not ideal either. The privileged mode status CSR allows
   blocking access to user memory via the STATUS_SUM-bit, which should be
   disabled by default and only enabled when access to user space is really
   needed. This patch allows implementing such features.
2023-06-09 13:53:27 +08:00
Ville Juven
a636edcbe4 addrenv/kstack: Allocate the kernel stack before initializing tcb
This is preparation to use kernel stack for everything when the user
process enters the kernel. Now the user stack is in use when the user
process runs a system call, which might not be the safest option.
2023-06-09 13:53:27 +08:00
SunJ
ad4e2f0922 arch/riscv: Fixed FPU context save/restore error
Always save/restore FPU context if the current thread use FPU

Signed-off-by: SunJ <jsun@bouffalolab.com>
2023-06-07 16:39:51 +03:00
Ville Juven
0a9279f672 MPFS: Use NuttX SBI for Kernel mode 2023-06-07 01:48:15 +08:00
Ville Juven
2525c10729 RISC-V: bind NuttX native SBI to SBI glue logic 2023-06-07 01:48:15 +08:00
Ville Juven
ae64f28344 RISC-V: Implement simple and native NuttX SBI
This is a minimalistic SBI implementation for NuttX.

Provides a single service for now:
- Access to machine timer

Provides a start trampoline to start NuttX in S-mode:
- Exceptions / faults are delegated to S-mode.
- External interrupts are delegated to S-mode.

Machine mode timer is used as follows:
- The timer compare match register reload happens in M-mode, via
  call gate "riscv_sbi_set_timer"
- The compare match event is dispatched to S-mode ISR, which will
  notify the kernel to advance time
- Clearing the STIP interrupt does not work from S-mode,
  so the call gate does this from M-mode

The only supported (tested) target for now is MPFS.
2023-06-07 01:48:15 +08:00
chao an
76e5204a80 risc-v/backtrace: correct stack pointer if enable ARCH_KERNEL_STACK
Signed-off-by: chao an <anchao@xiaomi.com>
2023-06-07 01:44:28 +08:00
Ville Juven
a41f752ecc kmm/kmm_map: Add missing FAR qualifiers 2023-06-05 12:03:37 +03:00
Ville Juven
d193c50947 mpfs_corespi: Change default motorola mode to MODE3 2023-06-02 11:13:02 -03:00
Ville Juven
4d49f80e16 mpfs_corespi: Fix DEBUGASSERT() for clk divider
Valid range is 0...255, not 2...512
2023-06-02 11:13:02 -03:00
Ville Juven
f28ac98de0 arch/risc-v: Add riscv_addrenv_pgmap
This is the counterpart for the kernel mapping functionality, i.e. it
implements the up_addrenv_xx functions needed by kmm_map
2023-06-02 10:50:26 +08:00
Ville Juven
1387c35213 arch/risc-v: Add method to extract PPN from SATP value
This makes it possible to get the physical page number (PPN) from any
SATP value, not only the currently active SATP register.
2023-06-02 10:50:26 +08:00
Ville Juven
376874d88b arch/risc-v: Add maximum user addrenv size and end boundary
Also in riscv_uservaddr() check the end boundary
2023-06-02 10:50:26 +08:00
Ville Juven
783f3f4c92 arch/risc-v: Move ARCH_ADDRENV_VBASE to addrenv.h
Move the user address environment base address to a public header and
add riscv_uservaddr query
2023-06-02 10:50:26 +08:00
Ville Juven
7c2930c3df mpfs/mpfs_corespi: Optimize TX / RX FIFO handling
Remove unnecessary reading of the status register when loading / unloading
the FIFOs. Reading from the IP block is slow due to BUS synchronization and
this basically makes the SPI busy loop for no reason at all, destroying the
CPU usage.

The overall benefit of these changes is approx. 25%-points, which is a
MASSIVE improvement.
2023-05-31 15:52:56 -03:00