Commit Graph

35 Commits

Author SHA1 Message Date
Jani Paalijarvi
4dfd3c9160 arch/riscv: Add ARCH_HAVE_SPI_CS_CONTROL for mpfs
Make it possible to override SPI CS function in board logic

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-11-24 06:50:32 -06:00
Abdelatif Guettouche
6cbcbd5481 arch/risc-v&xtensa/Kconfig: Don't select LIBC_ARCH_MEMCCMP. The Kconfig
option doens't exist and we are not providing any external
implementation.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-13 11:54:42 -03:00
Abdelatif Guettouche
a01cb867ce esp32c3_rom.ld: Add some of the string.h functions to the linker
script.

These functions are strongly declared and thus will be used instead of
any other implementation.  Furthermore, necessary Kconfig options are
selected to avoid building those function from NuttX's C library.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-13 11:54:42 -03:00
Gustavo Henrique Nihei
20341e6f17 risc-v/esp32c3: Enable support for "make bootloader" target
This enables the provisioning of the bootloader binaries through the
build system.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-27 18:22:29 -07:00
zhuyanlin
cd18d1f050 arch:riscv: remove arch atomic, use libc atomic when need
It is more common for implement in libc/machine

Change-Id: I3da6c3db64adb78c05ddb26d3956817ac6ada93e
2021-08-28 13:17:30 -03:00
Antti Vähälummukka
6eb73ced51 arch/risc-v/src/mpfs: Add CorePWM driver
Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA

This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals
2021-08-20 08:56:30 -03:00
jordi
f3af6edf93 Kconfig: add quotes in source to clean warnings from setconfig
To avoid the setconfig warning "style: quotes recommended around xxx in
source xxx"
2021-07-23 02:32:19 -07:00
Abdelatif Guettouche
af5e0c620f Rename MODULE_TEXT to TEXT_HEAP as the latter is more generic.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-18 07:14:17 -05:00
unixjet
68f19a6290 risc-v/rv32m1: Basic port to rv32m1 ri5cy 2021-06-05 17:25:57 -03:00
Abdelatif Guettouche
2d55f2659e riscv/esp32c3: Add module text allocator.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-04 18:08:36 -03:00
Janne Rosberg
f7cbed0256 risc-v/mpfs: enable up_systemreset() 2021-06-04 10:14:58 -05:00
Janne Rosberg
d6205642ab add support for PolarFire SoC and icicle board
Co-authored-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-05-24 22:55:44 -05:00
hotislandn
fb7a5b86ca arch:rv64:c906:demo protect build without PMP.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-03-16 11:43:10 -03:00
Dong Heng
458caf2732 riscv/esp32c3: Add ESP32-C3 WLAN netcard driver 2021-03-16 10:42:32 -03:00
Xiang Xiao
c047c1412f Remove all gap8(risc-v) arch and board source code
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-03-11 10:51:11 -08:00
Xiang Xiao
c54d617f2c Remove nr5m100(risc-v) arch and board source code
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-03-11 10:51:11 -08:00
hotislandn
5e50938726 arch:riscv64:basic porting for C906.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-03-10 19:23:24 +08:00
Abdelatif Guettouche
fb68a4b777 esp32c3: Add system reset.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-23 18:13:02 -08:00
Dong Heng
b11a5ca8b2 risc-v/esp32c3: Add ESP32-C3 basic support
Co-authored-by: Dong Heng <dongheng@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-18 01:21:53 -08:00
hotislandn
84daebf2cc arch:risc-v:bl602: enable FPU for this target. 2021-02-08 00:29:34 -08:00
Brennan Ashton
dd26d9c9f9 BL602: Add support for system reboot modes
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
2021-01-02 00:14:37 -06:00
Lei Chen
58bd873729 Add Basic support for BL602(UART timer CLIC) 2020-12-29 01:52:09 -08:00
Huang Qi
4078548ae3 risc-v: Introduce basic setjmp support
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2020-12-04 09:40:07 -03:00
liuhaitao
d5c6bfe6cf arch: Add custom arch chip build support
Just like custom board build support, add custom arch chip build
support.

Change-Id: I71c87e6b2195501a1b1d728b71d7cbe344951057
Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
2020-10-20 14:48:16 +08:00
Masayuki Ishikawa
08c4376606 arch, include, sched : Refactor ARCH_GLOBAL_IRQDISABLE related code
Summary:
- ARCH_GLOBAL_IRQDISABLE was initially introduced for LC823450 SMP
- At that time, i.MX6 (quad Cortex-A9) did not use this config
- However, this option is now used for all CPUs which support SMP
- So it's good timing for refactoring the code

Impact:
- Should have no impact because the logic is the same for SMP

Testing:
- Tested with board: spresense:smp, spresense:wifi_smp
- Tested with qemu: esp32-core:smp, maix-bit:smp, sabre-6quad:smp
- Build only: lc823450-xgevk:rndis, sam4cmp-db:nsh

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-09-03 10:20:20 +08:00
Xiang Xiao
b932b653dd arch: Select 64bit elf base on the architecture characteristic
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I09eec5a76f255016a910cfec3b3f70cd7577525e
2020-05-31 21:38:32 -07:00
aenrbes
d450f5ce77
Add support for Litex VexRiscV. 2020-03-21 06:01:56 +00:00
Masayuki Ishikawa
382cc29c72 arch: risc-v: Add support for PROTECTED build to k210 2020-02-14 09:29:51 -06:00
Masayuki Ishikawa
29d3ed2ec1 Feature k210 smp (#71)
* arch: risc-v: Remove unused typedef for irqstate_t

    NOTE: irqstate_t is defined in arch/risc-v/include/types.h

  * arch: risc-v: Add typedef irqstate_t for __LP64__
  * arch: risc-v: Add SMP support to K210 (RV64GC) processor
  * boards: maxi-bit: Update READMEs and add smp/defconfig
2020-01-10 08:04:41 -06:00
Masayuki Ishikawa
e33fc3dc89 Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>

    Run all .c and .h modified in PR through nxstyle.

Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>

    feature k210 (#16)

    * arch: risc-v: Add support for __LP64__ to types.h
    * arch: risc-v: Add support for RV64GC to common files
    * arch: risc-v: Add support for Kendryte K210 processor (RV64GC)
    * boards: risk-v: Add support for Sipeed Maix Bit with K210
    * tools: Add support for Kendryte K210 processor
2019-12-31 09:06:20 -06:00
Masayuki Ishikawa
7a8e9581ca Merged in masayuki2009/nuttx.nuttx/hifive1-qemu (pull request #1078)
HiFive1 with qemu

* arch: risc-v: Add include/.gitignore

* arch: risc-v: Add src/.gitignore

* arch: risc-v: Remove uncommon function prototypes in include/irq.h

* arch: risc-v: Add missing symbols and function prototypes in src/common/up_internal.h

* arch: risc-v: Add src/common/up_modifyreg32.c

* arch: risc-v: Enable include Make.dep in src/Makefile

* arch: risc-v: Fix stack coloration in common/up_createstack.c

* arch: risc-v: Add common/up_puts.c

* arch: risc-v: Add common/up_checkstack.c

* arch: rv32im: Move all logics from up_dumpstate.c to up_assert.c

    This change is same as other architectures like arm/src/armv7-m

* arch: Select ARCH_HAVE_STACKCHECK for RISC-V in Kconfig

* arch: risc-v: Add SiFive fe310 processor

    NOTE: Currently only tested with qemu

* boards: hifive1-revb: Add SiFive hifive1-revb board

    NOTE: Currently only tested with qemu

* tools: Add fe310 processor to configure.sh

Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-11-28 20:37:24 +00:00
Gregory Nutt
e4562fc538 This commit brings in support for the GAP8 architecture. The GAP8 is a 1+8-core DSP-like RISC-V MCU. Also included is support for the Gapuino GAP8 evaluation board.
Squashed commit of the following:

Author: Gregory Nutt <gnutt@nuttx.org>

    Completes review of configs/gapuino.
    arch/risc-v/include/gap8/chip.h:  Replace the moved chip.h header file with a dummy chip.h header file just to keep the system happy.
    Move include/gap8/chip.h to src/gap8/chip.h.  Internal details should not be exposed outside of arch/ and configs/.  Review all headers files in src/gap8
    Review of arch/risc-v/include.

Author: hhuysqt <hyq9606@126.com>

    corrected author and email
    Add app initialization, add signal support, cleanup irq context and configs
    fix some warnings
    gapuino initial port
    GAP8 initial port
2018-10-30 09:38:50 -06:00
Gregory Nutt
c2267a57a0 Kconfig files: Fix several errors noted by Alex Denisov in Bitbucket issue 115. 2018-08-05 10:48:02 -06:00
Ken Pettit
1e40e03c7f Minor RISC-V update 2016-10-21 17:01:40 -06:00
Ken Pettit
201a32cf8c Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it. 2016-10-16 09:47:07 -06:00