Gregory Nutt
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c33efa0a60
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SAMA5D2: Add chip definitions, PIDs, and IRQ definitions
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2015-08-31 15:19:01 -06:00 |
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Gregory Nutt
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9ba349f2b8
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SAMV71 QSPI: Fix frequency calculation. Need to use ceil() type logic so that requested frequency is not exceeded
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2015-08-31 10:18:17 -06:00 |
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Gregory Nutt
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4f87a71e6d
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SAMV7 QSPI: Use of CPHA in mode settings was inverted
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2015-08-31 10:05:41 -06:00 |
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Gregory Nutt
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4b738ba7cc
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SAMV7 QSPI: Fix some compiler problems when SPI debug is enabled
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2015-08-31 08:57:30 -06:00 |
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Gregory Nutt
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70f1a49fbe
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arch/arm/src/up_iternal.h and several ARM Make.defs files: In the original implementation, NOT defined(CONFIG_ARMV7M_CMNVECTOR) was a sufficient test to determine if lazy floating point register saving was being used. But recents changes added common lazy register as well so now that test must be (NOT defined(CONFIG_ARMV7M_CMNVECTOR) || defined(CONFIG_ARMV7M_LAZYFPU)).
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2015-08-31 08:40:02 -06:00 |
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Gregory Nutt
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b6515bbd4d
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SAMV71 QSPI: Changes resulting removing of clocking
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2015-08-29 18:53:27 -06:00 |
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Gregory Nutt
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b94eef2f19
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SAMV71 QSPI: Driver is code complete
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2015-08-29 15:57:20 -06:00 |
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Gregory Nutt
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3877cb09d9
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Trivial renaming
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2015-08-29 10:04:36 -06:00 |
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Gregory Nutt
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b887d39d2e
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SAMV7 QSPI: Add DMA transfer support
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2015-08-29 10:02:59 -06:00 |
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Gregory Nutt
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0b1bd46e24
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SAMV71 QSPI: Add support for dual and quad data transfers and dummy read cycles
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2015-08-28 11:58:19 -06:00 |
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Gregory Nutt
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3e0affba86
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SAMV71 QSPI: Add support for non-DMA memory transfers
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2015-08-28 10:13:46 -06:00 |
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Gregory Nutt
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8aefb9d139
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SAMV71 QSPI: Redesign some functions to better matched new interface definition
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2015-08-27 14:15:23 -06:00 |
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Gregory Nutt
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71bbe5b48d
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Merge remote-tracking branch 'origin/master' into st25fl1
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2015-08-27 12:08:04 -06:00 |
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Gregory Nutt
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926f3aa9af
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Update some comments
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2015-08-27 08:19:26 -06:00 |
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Gregory Nutt
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45a6f79eeb
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SAMV71 QSPI: Flesh out most of the initialization logic
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2015-08-26 14:15:40 -06:00 |
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Gregory Nutt
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768aba20ad
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SAMV71 QSPI: Use new QSPI interface. Can't use SPI interface as planned; the hardware architectue is too different
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2015-08-25 15:23:59 -06:00 |
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Gregory Nutt
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fa9522da41
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Missed one file in last commit
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2015-08-24 14:30:58 -06:00 |
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Gregory Nutt
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01cfe8c315
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Networking: Move where the local loopback device is initialized from board_app_intiialize() to up_intiialize() so that it will happen automatically
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2015-08-24 14:25:49 -06:00 |
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Gregory Nutt
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0732914d09
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Merged in david_s5/arch/upstream_446_clock (pull request #9)
Upstream_446_clock
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2015-08-24 14:13:51 -06:00 |
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Gregory Nutt
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706d50d97a
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Merge branch 'master' of bitbucket.org:nuttx/arch
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2015-08-24 13:46:19 -06:00 |
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Gregory Nutt
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c9603b27c0
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sim: Add logic to initialize the local loopback device is so configured
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2015-08-24 13:46:05 -06:00 |
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David Sidrane
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98ce2b2912
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Fixed Mask and made configuration macros consistant
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2015-08-24 08:56:24 -10:00 |
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David Sidrane
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b95c642a88
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Added Kconfig Enable Support for SAI and I2S PLL
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2015-08-24 08:55:45 -10:00 |
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Gregory Nutt
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bddc4dbd6a
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LPC17: Fix RAM vector table alignment for the LPC17 family. The ARMv7-M TRM only requires 128-byte alignment for vector tables; the LPC17, however, requires 256 byte alignment
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2015-08-23 17:17:14 -06:00 |
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Gregory Nutt
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065f2d6057
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SAMV7 USBHS DCD: Add logic to detect high speed mode; use DEBUGASSERT to check input parameters
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2015-08-22 08:58:38 -06:00 |
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David Sidrane
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6559c8994a
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Remove the word NOT - that was used to test the fix.
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2015-08-21 18:51:28 -06:00 |
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David Sidrane
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390c777a2a
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Removed the word NOT - that was used to test the fix.
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2015-08-21 18:40:20 -06:00 |
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Pavel Pisa
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2fafe1c817
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arch/arm/src/lpc17: Actually implement options to use external SDRAM and or SRAM for the heap. From Pavel Pisa
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2015-08-21 18:28:59 -06:00 |
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Gregory Nutt
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4c0d36740d
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Some of the last review chnages were still in the editor
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2015-08-21 18:25:10 -06:00 |
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Gregory Nutt
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9a32e907df
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Trivial, cosmetic changes from review of merge
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2015-08-21 18:22:57 -06:00 |
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Gregory Nutt
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4e347080e6
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Update comments in Kconfig file
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2015-08-21 18:15:09 -06:00 |
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Gregory Nutt
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16c5be9767
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Merged in david_s5/arch/upstream_446 (pull request #7)
Upstream_446
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2015-08-21 18:11:05 -06:00 |
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David Sidrane
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9d64050d68
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Added Changes to support for the new USB OTG controller for F446 register map
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2015-08-21 13:57:08 -10:00 |
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David Sidrane
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7c96342c63
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Break the stm32_otg.h into an stm32fxxxxx and stm32f44xx (should work on F7) versions
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2015-08-21 13:55:06 -10:00 |
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David Sidrane
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5d1ff3f7e1
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Use read modify write on PLL and CFG registers
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2015-08-21 13:22:09 -10:00 |
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David Sidrane
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1c746edceb
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Added PLL P constants
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2015-08-21 13:20:16 -10:00 |
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Gregory Nutt
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972f67ce42
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SAMV7 QSPI: Add framework for a QSPI driver. Initial commit is just the SPI driver with some name changes
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2015-08-21 14:22:47 -06:00 |
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Gregory Nutt
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f6c6723d88
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SAMV7 USBHS Device: After aligning DMA buffers and disabling write-back data cache, the DCD driver is fully functional using the CDC/ACM device
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2015-08-21 12:30:29 -06:00 |
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Gregory Nutt
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da6c5aabdf
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All ARMV7-M IRQ setup: Always set the NVIC vector table address. This is needed in cases where the code is running with a bootload and when the code is running from RAM. It is also needed by the logic of up_ramvec_initialize() which gets the vector base address from the NVIC. Suggested by Pavel Pisa
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2015-08-21 08:42:24 -06:00 |
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Gregory Nutt
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0b3b104b74
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Remove unnecessary step in previous commit
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2015-08-20 16:21:45 -06:00 |
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Pavel Pisa
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387f76d455
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This fix allows to run NuttX from SRAM or to place it after bootloader when run from Flash. From Pavel Pisa
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2015-08-20 07:46:18 -06:00 |
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Gregory Nutt
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5196a4183c
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SAMV7 USBHS device: Fix how we send data on control endpoints; fix how we select USB address
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2015-08-19 11:36:38 -06:00 |
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Gregory Nutt
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0db7ac92d9
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Minor coding style fixes in last commit; remove some unneeded debug output
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2015-08-19 07:54:46 -06:00 |
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Gregory Nutt
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098f1035fc
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Merged in seanshpark/nuttx_arch/stm32net (pull request #6)
STM32: Fix eth mem leak in recvframe
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2015-08-19 07:49:30 -06:00 |
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SaeHie Park
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75626fb071
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STM32: Fix eth mem leak in recvframe
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2015-08-19 15:40:04 +09:00 |
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Gregory Nutt
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cfd4f943da
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SAMV7 MCAN: When bitrate is changed, the MCAN has to be reset and there are lots of issues related to getting back to a healthy state if there is multithreaded access to the MCAN device. This commit handles a few of those issues, but there are more
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2015-08-18 11:56:07 -06:00 |
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Gregory Nutt
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4b96605f93
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SAMV7 MAN: Add support for bit timing IOCTL commands
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2015-08-18 11:20:22 -06:00 |
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Gregory Nutt
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ff84e67e59
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SAMV7 MCAN: Add logic to report CAN errors
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2015-08-18 08:48:13 -06:00 |
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Gregory Nutt
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b7d6720a23
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All CAN drivers: Set the new error indication to zero in the CAN message report
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2015-08-18 07:24:12 -06:00 |
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Gregory Nutt
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c01d3298e5
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Merged in paulpatience/nuttx-arch (pull request #5)
Added definitions for STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8, STM32F303RD, and STM32F303RE devices.
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2015-08-17 12:55:32 -06:00 |
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