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Author SHA1 Message Date
Masayuki Ishikawa
c5af689180 boards: sabre-6quad: Fix dramboot.ld for libcxx 
Summary:
- I noticed that cxxtest does not work correctly.
- Finally, I found that initializers for c++ is not called.
- This commit fixes this issue

Impact:
- None

Testing:
- Tested with cxxtest (defconfig will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-05-02 10:24:16 +03:00
Xiang Xiao
f77a0ec7fa arch: Move -finstrument-functions from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 23:54:15 +03:00
Xiang Xiao
1fde7e17bb arch: Move -fstack-protector-all from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 23:54:15 +03:00
Xiang Xiao
aeb9c5d822 boards: Move -fno-strict-aliasing from Make.defs to Toolchain.defs 
and migrate MAXOPTIMIZATION into ARCHOPTIMIZATION

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 11:36:41 +03:00
Xiang Xiao
1e23799455 arch/riscv: Optimize the syscall performance in kernel mode 
by renaming riscv_dispatch_syscall to sys_callx, so the caller
don't need the immediate step(syscallx->riscv_dispatch_syscall)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 11:31:01 +03:00
Xiang Xiao
efce8bd198 Revert "arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm" 
This reverts commit 9b7f9867aa.
 2022-05-01 11:31:01 +03:00
Xiang Xiao
a021177de8 arch: Fix the style found in review 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 11:29:44 +03:00
Xiang Xiao
4a03cab6f9 libc: Remove the redundant seek in writev 
since the file position isn't changed if write return fail

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 10:07:36 +03:00
Xiang Xiao
220f1dd6a0 boards: run tools/refresh.sh to normalize defconfig 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 09:50:50 +03:00
Xiang Xiao
05ff19d17b tools/testbuild.sh: Don't skip configure and distclean 
to improve the test coverage

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 09:50:50 +03:00
chao.an
5db447623d arm/cxd56xx/lc823450/rp2040: replace arch testset to board implement 
This patch to resolve the regression which leads to the breakage of spresense:smp

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-05-01 06:38:25 +09:00
chao.an
3ec2f70046 arch/arm/Make.defs: unify arch common source include 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-30 21:50:16 +08:00
chao.an
8951b0135b arch/cortex-[a|r]/Make.defs: unify arch common source include 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-30 21:50:16 +08:00
chao.an
5677fe2153 arch/cortex-m/Make.defs: unify arch common source include 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-30 21:50:16 +08:00
chao.an
a560eb5f8d arch/arm/Make.defs: unify common source include 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-30 21:50:16 +08:00
Xiang Xiao
2a95be5086 arch/avr: Remvoe the error message when toolchain can't find 
to avoid blocking the basic ci check

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-30 01:20:11 -03:00
Xiang Xiao
baf852ff4b tools/ci: Enable libcxx test config 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-29 21:08:14 -03:00
Xiang Xiao
b12c0a1e31 boards: Remove -std=c++1x from Make.defs 
let the implementation of standard library choice what they want

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-29 21:08:14 -03:00
Xiang Xiao
7f91fcdf89 boards/arm: Remove the unneeded C++ config from stm32l4/nucleo-l476rg 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-29 21:08:14 -03:00
Xiang Xiao
94cb0c6072 arch: Move -nostdinc++ to Tooolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-29 21:08:14 -03:00
Xiang Xiao
c1e5ba4602 libxx: Always build libcxx with -std=c++17 
since the implementation of barrier require
the aligned new which is defined in C++ 17

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-29 21:08:14 -03:00
Simon Filgis
385519302e Corrected typo in sam_spi.c. Debaugcall needs cs not if as ref... 
Signed-off-by: Simon Filgis <simon@ingenieurbuero-filgis.de>
 2022-04-30 03:13:38 +08:00
Oki Minabe
c38234e342 armv7-a/r: use cps instruction to change cpu mode 
Summary:
- Use CPS instruction to change cpu mode for code simplification
- CPS which changes cpu mode is available in armv6 and above

Impact:
- armv7-a/r

Testing:
- smp and ostest on sabre-6quad:smp w/ qemu

Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
 2022-04-30 03:13:22 +08:00
Ville Juven
b3baf95835 UMM: Implement getter for address environment heap start vaddr 
Using the Kconfig macro does not work for RISC-V target, as there the
user heap follows .data/.bss and does not obey any Kconfig provided
boundary.

Added stubs for ARM and Z80 also.
 2022-04-29 23:13:16 +08:00
wangbowen6
dcb440a4d9 libc/arch_atomic: add FAR to pointers. 
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-04-29 15:06:11 +08:00
wangbowen6
ea164f28b8 libc/arch_atomic: add gcc legacy __sync buitins support. 
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-04-29 15:06:11 +08:00
Sergey Nikitenko
19c5ac9135 stm32l4 fix ECCR comment 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
3cc8d7d52a stm32l4 rtcc register fixes 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
0b9a36d142 stm32l4 fix tim channel range checking 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
541b03b787 stm32l4 TIM register fixes 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
57c64d327e stm32l4 FLASH_CR_FSTPG register fix 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
50fb3b5dc0 stm32l4 fixing proper register name RCC_APB1ENR1_PWREN 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
b73e89a674 stm32l4 RCC multi-bit field fixes 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
7e4193c4a3 stm32l4 remove useless RTCPRE setup 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
9850766d07 stm32l4 RCC SW/SWS comment fixes 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
3da7706db8 stm32l4+ DMAMUX register fix 2022-04-29 09:30:09 +03:00
Abdelatif Guettouche
da273fce0b arch/xtensa: Replace the xcp context with stack context to improve context switching 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-29 02:51:41 +08:00
Ville Juven
e674d5cb86 RISC-V: Add crt0 file 
Contains the code for the user process signal trampoline.
 2022-04-29 02:02:15 +08:00
Ville Juven
0ccda05a82 RISC-V: Move wipe_page to pgalloc.h and rename it riscv_pgwipe 2022-04-29 02:02:15 +08:00
Ville Juven
3d8ba496a2 RISC-V: Add pgpool to vaddr utility function 
The only mapping that is supported now is vaddr=paddr, but the function
DOES check that the address is within the page pool, so it is not
useless.
 2022-04-29 02:02:15 +08:00
Ville Juven
1322f82802 RISC-V: Copy kernel memory mappings to userspace addrenv 
Copy the kernel mappings to the new (user) address environment. The
copyuing is done exactly once. This relies on the fact that the kernel
L1/L2 mappings will never change, as all of the kernel memory is mapped
upon boot.
 2022-04-29 02:02:15 +08:00
Ville Juven
57127b9429 RISC-V: Initial support for CONFIG_BUILD_KERNEL 
This implements initial support for kernel build (address environments,
page allocator) for RISC-V.

This is done a bit differently compared to the ARMV7 implementation:

- Support implemented for Sv39 MMU, however the implementation should be
  extensible for other MMU types also.
- Instead of preserving and moving the L1 references around, a canonical
  approach is used instead, where the page table base address register
  is switched upon context switch.
- To preserve a bit of memory, only a single L1/L2 table is supported,
  this gives access to 1GiB of virtual memory for each process, which
  should be more than enough.

Some things worth noting:
- Assumes page pool is mapped with vaddr=paddr mappings
- The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are
  ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used
  for ARCH_DATA_RESERVE
- ARCH_DATA_RESERVE is placed at the beginning of the userspace task's
  address environment
 2022-04-29 02:02:15 +08:00
Michael Jung
61f3bd10a5 Fix udp recvfrom to correctly return addrlen 
According to POSIX the length of the source address of the received
message shall be stored in the object pointed to by the address_len
argument.

This patch fixes two places where this did not happen correctly.

Signed-off-by: Michael Jung <michael.jung@secore.ly>
 2022-04-28 20:25:38 +08:00
YAMAMOTO Takashi
ded4fd33c1 Implement preadv and pwritev 2022-04-28 13:40:25 +08:00
YAMAMOTO Takashi
d832df88a5 libc.csv: sort 2022-04-28 13:40:25 +08:00
anjiahao
2b938ed8f8 tools:minidumpserver.py support xtensa 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-28 13:29:25 +08:00
Xiang Xiao
2dbf826c19 config: It's enough to let LTO_FULL depend on ARCH_TOOLCHAIN_GNU only 
since ARCH_TOOLCHAIN_CLANG automatically select ARCH_TOOLCHAIN_GNU

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-28 11:25:00 +09:00
Xiang Xiao
7539d75bb4 config: DEBUG_LINK_MAP don't need depend on ARCH_TOOLCHAIN_GNU 
since all toolchain could generate the map file

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-28 11:25:00 +09:00
Takayoshi Koizumi
afc09fb442 drivers/audio/cxd56: Workaround for HW issue of CXD56 
Because of HW issue, Audio output volume is limited until -30db as maximum.
This commit fix it. And fix the bug of voulme control.
 2022-04-28 08:12:47 +09:00
Gustavo Henrique Nihei
ffab2dc628 risc-v: Restrict Fence instruction for chips that support S-mode 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-04-28 01:18:46 +08:00