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c6e636a871
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719 Commits

Author SHA1 Message Date
Huang Qi
c6e636a871 arch/risc-v: Save/Load float register in setjmp 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-09 10:15:54 +02:00
Huang Qi
8dedf1d9af arch/risc-v: Correct handling of QPFPU and DPFPU 
If QPFPU enabled we will never enter the expected QPFPU branch since
option QPFPU depend on DPFPU.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-09 10:15:54 +02:00
Eero Nurkkala
4b2fbab998 risc-v/mpfs: usb: fix an unused variable warning 
Fix an unused variable warning if the CONFIG_HAVE_USBTRACE
(and USB_DEBUG) aren't set.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-03-08 23:00:31 +08:00
Eero Nurkkala
8c1ab129ac risc-v/mpfs: add USB device driver 
This adds a simple USB device driver for the mpfs. However,
this driver is still at its early phase. Only limited testing
with CDC/ACM has been conducted.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-03-08 16:49:29 +08:00
zhuyanlin
634d337394 riscv/xtensa: corrent dumpstate xcp size 
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-03-08 10:14:04 +02:00
Huang Qi
e383439dda risc-v: Replace all inline assembly with macro 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-03 19:55:54 +08:00
Huang Qi
35330a798b risc-v: Implement READ_AND_SET_CSR for CSR operate 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-03 19:55:54 +08:00
Huang Qi
d0356bb9ba arch/risc-v/qemu-rv: Set FS bits in mstatus 
FPU test may fail without correct FS bits.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-28 16:28:22 +08:00
Xiang Xiao
3bf416e8b8 arch: Move STACK_ALIGNMENT definition to up_internal.h 
to avoid the same macro duplicate to many place

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-28 15:05:41 +08:00
Xiang Xiao
44bd3212d4 arch: Remove SYS_RESERVED from Kconfg 
let's arch define the correct value instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-27 22:54:13 +08:00
Xiang Xiao
087b9e5ff3 arch: Move the content from svcall.h to syscall.h 
and remove svcall.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-27 22:54:13 +08:00
Gustavo Henrique Nihei
36ac532c98 risc-v/esp32c3: Fix Scheduler CPU Load feature using Oneshot Timer 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-26 03:23:13 +08:00
Gustavo Henrique Nihei
a6fea1c3a5 risc-v/esp32c3: Enable Timer Groups clocks on timer initialization 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-25 22:49:22 +08:00
Gustavo Henrique Nihei
1d15196df7 risc-v/esp32c3: Fix detection of CPU reset by Watchdog Timer 
This commit fixes an issue where some peripheral clocks are being
disabled during CPU reset on ESP32-C3.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-25 22:48:09 +08:00
Huang Qi
e8552156b6 arch/risc-v: Remove unneeded ISA specifc interface 
They are not really defined and used in any where:
uint32_t up_getmisa(void);
uint32_t up_getarchid(void);
uint32_t up_getimpid(void);
uint32_t up_getvendorid(void);
uint32_t up_gethartid(void);

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-25 20:36:16 +08:00
Huang Qi
8b66280b4f arch/risc-v: Update outdated comments 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-25 20:36:16 +08:00
Xiang Xiao
6fa5885d2d arch/esp32: Update esp-wireless-drivers-3rdparty to verion 45701c0 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-24 09:05:40 +01:00
Xiang Xiao
d7fe0127b0 Replece clock_gettime(CLOCK_REALTIME) with clock_systime_timespec if suitable 
it's better to call the kernrel api insteaad user space api in kernel

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-24 01:06:36 +08:00
Xiang Xiao
43f57240e0 Replece clock_gettime(CLOCK_MONOTONIC) with clock_systime_timespec 
it's better to call the kernrel api insteaad user space api in kernel

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-24 01:06:36 +08:00
Xiang Xiao
f1ed349dd9 sched/clock: Remove CLOCK_MONOTONIC option from Kconfig 
here is the reason:
1.clock_systime_timespec(core function) always exist regardless the setting
2.CLOCK_MONOTONIC is a foundamental clock type required by many places

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-23 01:21:26 +08:00
Xiang Xiao
163fe4ff0b boards: Replace CONFIG_CYGWIN_WINTOOL with CONVERT_PATH 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-20 21:15:36 +01:00
Xiang Xiao
1d1bdd85a3 Remove the double blank line from source files 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-20 20:10:14 +01:00
Huang Qi
0c5aff9be6 risc-v/qemu-rv: Supports SMP up to 8 cores 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-18 13:25:01 +08:00
Huang Qi
36ff081b1a risc-v: Support more than 2 cores in riscv_cpu_boot 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-18 13:25:01 +08:00
Huang Qi
7c18290331 risc-v: Rename up_fault to riscv_fault 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-18 13:25:01 +08:00
Alan Rosenthal
8defb843aa Remove duplicate linker script definitions 
## Summary
A lot of linker scripts were listed twice, once for unix, once for windows.

This PR cleans up the logic so they're only listed once.

 ## Impact
Any opportunity to use a single source of truth and reduce lines of code is a win!

 ## Testing
CI will test all build
 2022-02-17 02:55:25 +08:00
Xiang Xiao
db57e2cd8e Fix the minor style issue 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-15 15:26:38 +01:00
Huang Qi
5cde8c6934 risc-v: Let g_cpu_basestack determined at compile time 
Fix the CPU1 idle tasks stack corruption since the cpux's idle stack
is loaded from g_cpu_basestack (data section) before, but on this time
it maybe not ready since it is initialized by CPU0, and the value
from g_cpu_basestack is random.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-15 11:40:34 +09:00
Huang Qi
0d7f30c86d risc-v/k210: Move wfi to entry of the slave cpu boot routine 
Fix another potential bug in non-smp case: load a value from overflowed address of g_cpu_basestack.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-15 11:40:34 +09:00
Huang Qi
b8477f857b k210: Use common cpu idle stack implementation 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-14 11:32:34 +08:00
Huang Qi
55d88627a0 risc-v: Implement common up_cpu_idlestack 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-14 11:32:34 +08:00
Huang Qi
64130b4775 risc-v: Use _ebss instead of _default_stack_limit as idle stack base 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-13 14:37:57 +08:00
Huang Qi
95b0c85f58 arch: Add xxx_tcbinfo.c to SoC level Make.defs 
Fix build break with CONFIG_DEBUG_TCBINFO enabled.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-12 21:07:35 +09:00
Huang Qi
3fe9c9523c risc-v: Fix style issue in SoC's Make.defs 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-11 15:20:17 +08:00
Alan C. Assis
d49ad207ef esp32c3: Fix issue #5377 UART1 not working because clock as disabled 2022-02-11 10:01:25 +08:00
Huang Qi
7134220ae2 risc-v: Remove duplicated up_idle logic 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-10 13:09:32 +08:00
Huang Qi
9223547afc risc-v: Support cpu activity led in up_idle 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-10 13:09:32 +08:00
Huang Qi
6f18747dc2 risc-v: Add WFI to up_idle and fix compile issue 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-10 13:09:32 +08:00
Huang Qi
9d91d69ee0 arch/risc-v/mpfs: Remove riscv_pthread_exit.c in Make.defs 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-09 21:21:43 +08:00
Huang Qi
c0a0de97ce Revert "libc: Call pthread_exit in user-space by up_pthread_exit" 
This reverts commit f4a0b7aedd.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-09 21:21:43 +08:00
Xiang Xiao
4c167b0729 Correct the code alignment 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-01 21:22:21 -03:00
Abdelatif Guettouche
f49a579721 esp32c3/: Remove unused exported variables from ROM and add declaration 
for the one used.
 2022-01-31 23:35:50 +08:00
Xiang Xiao
2c3020ddaf arch/Toolchain.defs: Replace --print-file-name=libgcc.a with --print-libgcc-file-name 
to more compatable with clang: https://reviews.llvm.org/D25338

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-31 09:46:04 +01:00
Xiang Xiao
e0b62bf677 arch/Toolchain.defs: Don't expand EXTRA_LIBS immediately 
since board's Make.defs may overwrite ARCHCPUFLAGS

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-30 11:04:35 +09:00
Xiang Xiao
1c2c0e4707 arch/Toolchain.defs: Simplify the builtin library addition for EXTRA_LIBS 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-28 12:02:38 +01:00
Ville Juven
7c116efe05 Add support for a ROMFS image for MPFS 
The image must be placed into:
boards/risc-v/mpfs/icicle/include/boot_romfsimg.h

The image is mounted by mpfs_bringup, which is run by the application
itself, or by board_late_initialize() in the case when
CONFIG_BOARD_LATE_INITIALIZE is defined, e.g. with CONFIG_BUILD_KERNEL
 2022-01-27 11:06:43 -03:00
Xiang Xiao
f903a55102 sched/tcbinfo: Fix the compile warning 
Update tcbinfo struct

armv8-m/arm_tcbinfo.c:109:3: warning: excess elements in struct initializer
  109 |   TCB_REG_OFF(REG_S31),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:109:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:110:3: warning: excess elements in struct initializer
  110 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:110:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:111:3: warning: excess elements in struct initializer
  111 |   TCB_REG_OFF(REG_FPSCR),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:111:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:112:3: warning: excess elements in struct initializer
  112 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:112:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:37:1: warning: missing braces around initializer [-Wmissing-braces]
   37 | {

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-27 17:36:27 +08:00
Ville Juven
4bd1bd177b RISC-V MMU: Add missing implementation for PTE getter 
For some reason this was (mistakenly) left out from the patch
that was supposed to have it.
 2022-01-27 10:22:30 +01:00
Ville Juven
fc3cd308d5 Wipe the PMP configuration in MPFS bootloader start routine 
This way old PMP configurations are removed upon warm reset.
 2022-01-25 20:22:34 +08:00
Ville Juven
81188d9c94 Extend the RISC-V PMP functionality 
- Add test for mode support, which is architecture dependent
- Add tests for address alignment and region size
- Add option to query for access rights
 - The function goes through every PMP entry and tests if an address
   range from [base, base+size] has been configured for desired
   access rights.
 - If several PMP entries match the range and access rights, the
   information is combined
 - End result is either no access, a partial match was found, or a full
   match was found. Details about the partial match are not provided.

The intent for testing access rights and not just blindly applying them
is a case where they are already set in e.g. a bootloader. In this
case, nothing should be done, unless the configuration does not match,
in which case the software must not continue further.
 2022-01-25 20:22:34 +08:00