This change improves upon current support for pin interrupts. Before,
a pin interrupt was handled (with nrf52_gpiote_setevent) using one
of the eight available GPIOTE channels. Moreover, it didn't event let
the user specify which channel to use (simply tried to get a free one).
Also, it was buggy since it did not consider unsetting the callback.
Besides GPIOTE channels, there is another way to deal with pin interrupts.
The GPIO peripheral is capable of generating a PORT event
(for the whole GPIO port) depending on the pin SENSE configuration
(HIGH or LOW, or NONE) and GPIO DETECTMODE register
(latching or non-latching).
This change then renames nrf52_gpiote_setevent into nrf52_gpiote_set_ch_event,
maintaining functionality of original function, but now allows specifying
channel (and correctly handles unsetting the callback). Then, a
new nrf52_gpiote_set_pin_event is added, which allows to set a callback
for a given pin. During initialization, interrupt for the PORT event is
enabled and handled in such way that for each pin whose corresponding
bit in LATCH register (indicates the result of pin SENSEing) the
callback for this pin will be invoked. This mechanism means that
every pin can get an ISR. It also avoids using GPIOTE channels for this
purpose which carry higher current consumption.
This new per-pin callback mechanism has some added memory requirement
so it can be disabled and its default is dependant on DEFAULT_SMALL.
When disabled, a callback for the PORT event can be set directly
with nrf52_gpiote_set_port_event
There was only one use of nrf52_gpio_setevent() which was migrated
into nrf52_gpio_set_ch_event() passing channel zero.
Reference here:
https://pubs.opengroup.org/onlinepubs/009695399/functions/timer_create.html
DESCRIPTION
...
Each implementation shall define a set of clocks that can be
used as timing bases for per-process timers. All implementations
shall support a clock_id of CLOCK_REALTIME.
*** If the Monotonic Clock option is supported, implementations shall
support a clock_id of CLOCK_MONOTONIC. ***
...
Change-Id: Ia8e7302ed4a7e9ec11a0059bd68e9674ea942001
Signed-off-by: chao.an <anchao@xiaomi.com>
(gdb) b longjmp
Breakpoint 1 at 0x8270
(gdb) r
Starting program: /home/chao/code/m3/nuttx/nuttx
[ 0.000000] Assertion failed at file:task/task_onexit.c line: 99
Breakpoint 1, 0xf7b905e0 in siglongjmp () from /lib/i386-linux-gnu/libc.so.6
(gdb)
(gdb) bt
|#0 0xf7b905e0 in siglongjmp () from /lib/i386-linux-gnu/libc.so.6
|#1 0xf7f9c3dc in siglongjmp_alias () from /lib/i386-linux-gnu/libpthread.so.0
|#2 0x5655d668 in up_assert (filename=0x56641018 "task/task_onexit.c", line=99) at sim/up_head.c:132
|#3 0x56567413 in _assert (filename=0x56641018 "task/task_onexit.c", linenum=99) at assert/lib_assert.c:36
|#4 0x565f8cfd in on_exit (func=0x565f8c12 <exitfunc>, arg=0x565fd780 <simuart_restoremode>) at task/task_onexit.c:99
|#5 0x565f8c89 in atexit (func=0x565fd780 <simuart_restoremode>) at task/task_atexit.c:109
|#6 0x565fd819 in simuart_start () at sim/up_simuart.c:112
|#7 0x5656c844 in up_uartinit () at sim/up_uart.c:496
|#8 0x5656ba7a in up_initialize () at sim/up_initialize.c:234
|#9 0x5655da56 in nx_start () at init/nx_start.c:701
|#10 0x5655d5e9 in main (argc=1, argv=0xffffd6f4, envp=0xffffd6fc) at sim/up_head.c:96
Change-Id: Ifd7196b2de7bf9fc7cea764c19a5c0eacf08fdb6
Signed-off-by: chao.an <anchao@xiaomi.com>
Summary:
- I noticed that nxsched_merge_pending() is called outside a critical section
- The issue happens if a new rtcb does not hold a critical section
- Actually, global IRQ control is done in nxsched_resume_scheduler() in nxtask_exit()
- However, nxsched_merge_pending() was called after calling nxsched_resume_scheduler()
- This commit fixes the issue by moving nxsched_merge_pending() before the function
- NOTE: the sequence was changed for SMP but works for non-SMP as well
Impact:
- This commit affects both SMP and non-SMP
Testing:
- Tested with ostest with the following configurations
- spresense:wifi_smp (NCPUS=2 and 4)
- spresense:wifi (non SMP)
- sabre-6quad:smp (QEMU)
- esp32-core:smp (QEMU)
- maix-bit:smp (QEMU)
- sim:smp
- lc823450-xgevk:rndis
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_flash.h:
* Merge comments when they are section separators for
similar/related registers:
- TIVA_FLASH_FWPWRITE*
- TIVA_FLASH_FSM_SECTOR1*
- TIVA_FLASH_FSM_BSLE*
- TIVA_FLASH_FSM_BSLP*
regards to the data used by the ROM.
Static alloaction sections should end at the begining of the ROM data.
The rest of memory (End of ROM data --> End of DRAM) is added to the
heap.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
