Gregory Nutt
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c7293535fe
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Various changes to get SAMA5 SDRAM working. Marginally functional, but there is more to be done
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2013-08-02 18:30:27 -06:00 |
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Gregory Nutt
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08a1ff5c79
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Correct some typos int he MPADDRCS register address definitions
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2013-08-02 12:06:11 -06:00 |
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Gregory Nutt
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b00d72a7f2
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SAMA5: More MMU-related changes to properly initialize SDRAM
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2013-08-02 11:11:57 -06:00 |
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Gregory Nutt
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894618f894
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SAMA5: Add logic to initialize SAMA5D3x-EK on-board SDRAM
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2013-08-01 16:58:55 -06:00 |
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Gregory Nutt
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70e1028d41
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SAMA5: Add DDR controller register definitions
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2013-08-01 12:27:41 -06:00 |
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Gregory Nutt
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35c3a49e1c
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ARMv7-A: Map all of .text, .bss, .data., stacks before enabling the MMU and caching. This is simpler and avoids fears I have about caching
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2013-08-01 10:05:33 -06:00 |
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Gregory Nutt
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f0e6d4f101
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ARMv7-A: Separate CONFIG_PAGING start-up logic into a different startup file. Too much conditional compilation.
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2013-08-01 07:41:00 -06:00 |
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Gregory Nutt
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b0045bc7e2
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SAMA5: Add an NSH configuration of the SAMA5D3x-EK board
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2013-07-31 10:46:13 -06:00 |
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Gregory Nutt
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8695c89aa4
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SAMA5: Modification of some CPSR-related inline functions
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2013-07-31 09:11:24 -06:00 |
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Gregory Nutt
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db20c5fc43
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Fix Cortex-A CPSR register field definition
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2013-07-30 19:05:24 -06:00 |
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Gregory Nutt
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391d300d4d
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SAMA5: Change mapping of vector tables to work around that fact that I don't understand how the AXI MATRIX remap works
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2013-07-30 16:19:52 -06:00 |
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Gregory Nutt
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16371b50e4
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ARMv7-A: Add cp15_disable_dcache(); SAMA5: nor_main.c no disables MMU and caches; Should not remap ISRAM to address 0x0 unless we booted into ISRAM
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2013-07-30 13:20:33 -06:00 |
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Gregory Nutt
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6f99994722
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More DAC changes from John Wharington
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2013-07-30 11:41:53 -06:00 |
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Gregory Nutt
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b75a0cf8be
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Add ARMv7-A irqdisable() inline function
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2013-07-30 11:37:09 -06:00 |
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Gregory Nutt
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84150fd7ed
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STM32 F3 I2C driver from John Wharington
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2013-07-30 10:35:17 -06:00 |
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Gregory Nutt
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4bdcceb3b3
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STM32 DAC DMA fixes from John Wharington
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2013-07-30 08:54:32 -06:00 |
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Gregory Nutt
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547f9be80f
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SAMA5: More cache and mmu inline utility functions
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2013-07-29 19:57:15 -06:00 |
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Gregory Nutt
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95998c715f
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SAMA5: Separate cache operations into separate files
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2013-07-29 18:38:02 -06:00 |
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Gregory Nutt
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f658bcdb13
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Changes to ARMv7-A boot logic to handle the case where we execute out of NOR FLASH
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2013-07-29 17:54:56 -06:00 |
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Gregory Nutt
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4e90fae5e8
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Add SAMA5 HSMC register definitions and logic to reconfigure the NOR FLASH
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2013-07-29 10:56:21 -06:00 |
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Gregory Nutt
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27a9da98f4
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SAMA5: Add file structure to support board-specific initialization of NOR flash
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2013-07-29 07:41:53 -06:00 |
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Gregory Nutt
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65c8abddb8
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SAMA5: The ostest configuration have been converted to run out of NOR flash. There is more to be done, however
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2013-07-28 15:07:35 -06:00 |
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Gregory Nutt
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7dfabf3507
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SAMA5: Correct a clock configuration bug; clarify some MMU memory types
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2013-07-28 12:44:06 -06:00 |
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Gregory Nutt
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f191ac94c0
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SAMA5: Correct vector mapping
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2013-07-28 09:44:11 -06:00 |
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Gregory Nutt
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9a5311296f
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Removed unused ARMv7-A cache function
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2013-07-27 14:03:02 -06:00 |
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Gregory Nutt
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ae6ed8ca52
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SAMA5: Fix heap allocation bugs
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2013-07-27 11:28:31 -06:00 |
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Gregory Nutt
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3d16c9afc7
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SAMA5 page table is cached; need to flush the cache each time that the page table is updated
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2013-07-27 09:27:37 -06:00 |
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Gregory Nutt
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87af1517ed
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Correct an error in Cortex-A5 intermediate MMU mapping
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2013-07-26 17:26:53 -06:00 |
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Gregory Nutt
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14093ef76a
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Add a hello world configuration to help with the SAMA5 bringup
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2013-07-26 15:28:01 -06:00 |
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Gregory Nutt
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2f772c84fd
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Finally... renamed all CONFIG_DRAM_ settings to CONFIG_RAM_
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2013-07-26 10:09:17 -06:00 |
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Gregory Nutt
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f87963accd
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SAMA5: If the page table is in high memory, make sure that it is excluded from the heap
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2013-07-26 09:16:46 -06:00 |
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Gregory Nutt
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4ea9e1eb6e
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Fix some bad page table definitions of last commit
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2013-07-25 18:11:25 -06:00 |
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Gregory Nutt
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696f6d0482
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Misc Cortex-A5 MMU-related fix -- still does not boot
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2013-07-25 16:37:55 -06:00 |
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Gregory Nutt
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d1be1e6698
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Fix an uninitialized register error that crept into the ARM9 start up code many years ago and was recently cloned into the Cortex-A5. Obviously no on has used NuttX with ARM9 for years
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2013-07-24 20:12:04 -06:00 |
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Gregory Nutt
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f337f3a977
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Fix SAMA5 vector linking issue
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2013-07-24 12:51:42 -06:00 |
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Gregory Nutt
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213780bc43
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Update SAMA5D3x-EK board configuration to support on-board UART connections, LEDs, and push buttons
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2013-07-24 12:27:12 -06:00 |
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Gregory Nutt
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63f136dd7e
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Revamp the way external memory regions are configured; Add logic to add SAMA5 external memory regions to the heap
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2013-07-24 10:08:32 -06:00 |
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Gregory Nutt
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a81abd3514
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Improve Cortex-A5 context switching so that a little less copying is done
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2013-07-24 07:47:51 -06:00 |
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Gregory Nutt
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2e8fcc7229
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ARMv7-N: Fix a copy error introduced in the previous check-in
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2013-07-23 19:09:17 -06:00 |
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Gregory Nutt
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cb3f394d53
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Improve some ARMv7-A/M floating point register save time; Add floating point register save logic for ARMv7-A
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2013-07-23 17:52:06 -06:00 |
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Gregory Nutt
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9e24c4fcd5
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ARMv7-A: Need 8-byte stack alignment when callign C code from interrupt handlers. This change needs to be ported to other ARM architectures as well
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2013-07-23 14:47:16 -06:00 |
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Gregory Nutt
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596cdf2982
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SAMA5: Adapt clocking for different boot modes. New header files for AXI matrix, BSC, and SFR
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2013-07-23 13:54:49 -06:00 |
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Gregory Nutt
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ae3f2b2876
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Add SAMA5D3 pin multiplexing definitions
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2013-07-23 09:47:01 -06:00 |
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Gregory Nutt
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e9f8689cee
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Add SAMA5 GPIO configuration support
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2013-07-22 20:59:47 -06:00 |
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Gregory Nutt
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50cd6352fa
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Add support SAMA5 UART and serial driver
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2013-07-22 19:16:37 -06:00 |
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Gregory Nutt
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9665c0d267
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SAMA5 clock configuration should now agree with Atmel sample code; Added header file with macros to enable and disable peripheral clocking
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2013-07-22 17:00:02 -06:00 |
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Gregory Nutt
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571308c27a
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Add SAMA5 clock logic. Cloned from SAM3U and not yet verified
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2013-07-22 14:42:05 -06:00 |
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Gregory Nutt
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fb8a7a91fb
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SAMA5 interrupt handling logic
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2013-07-22 11:54:39 -06:00 |
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Gregory Nutt
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ca9b52b07f
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SAMA5/Cortex-A: Improve irqsave/restore inlines + add irqenable. Add skeleton file for SAMA5 interrupt management. Also change from last commit that was left in the editor
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2013-07-21 17:08:40 -06:00 |
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Gregory Nutt
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b26d506514
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Add system timer logic for the SAMA5
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2013-07-21 15:49:17 -06:00 |
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