Commit Graph

904 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
c778f35f08 risc-v/esp32c3: Add support for Protected Mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-05-18 11:43:52 +08:00
Eero Nurkkala
817919ebb6 risc-v/mpfs: IHC: allow hart configuration
Let the user pick what runs on the harts. For example, the
default configuration now supports NuttX on hart2 and Linux
kernel on harts 3 and 4. Also fix a few issues in the code.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-18 01:34:33 +08:00
Xiang Xiao
5958d3ac62 risc-v: Move "LDFLAGS += -melf32lriscv" from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-16 11:17:08 +03:00
Xiang Xiao
1f920e55d3 Move warning option from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 15:40:35 +03:00
Xiang Xiao
8b7c5b039d arch: Move -fsanitize=kernel-address to ARCHOPTIMIZATION
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 15:40:35 +03:00
Xiang Xiao
1fb8c13e5e Replace nxsem_timedwait_uninterruptible with nxsem_tickwait_uninterruptible
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00
Xiang Xiao
816ce73ab4 Replace nxsem_timedwait with nxsem_tickwait
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00
Petro Karashchenko
0fee5a2b84 nuttx: fix typos in comments
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-05-14 23:45:52 +08:00
Eero Nurkkala
0178792a01 risc-v/mpfs: IHC: clarify semaphore usage
g_mpfs_ack_sig and g_mpfs_rx_sig are better used with
SEM_INITIALIZER(0) (signalling) rather than with
SEM_INITIALIZER(1) (mutual exclusion).

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-13 19:07:40 +03:00
Eero Nurkkala
0a75a9556d risc-v/mpfs: apply IHC review fixes
PR#6249 was already merged without the review fixes. Provide the
fixes here on a separate patch.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-13 10:38:51 +03:00
Xiang Xiao
1ba316b5c7 arch: Remove board/libboard$(LIBEXT) from the rerequest of export_startup
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-12 23:34:31 +03:00
Xiang Xiao
23200471df arch/riscv: Remove & ~1 before assign signal_handler to REG_EPC
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-12 23:31:50 +03:00
Masayuki Ishikawa
3193aa3c97 arch: risc-v: Add MMU support for qemu-rv
Summary:
- This commit adds MMU support for qemu-rv
- Please note that mtimer is disabled for S-mode because
  the mtimer needs to be accessed in M-mode

Impact:
- qemu-rv only

Testing:
- Tested with rv-virt:knsh64 (will be pushed later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-13 04:14:01 +08:00
Eero Nurkkala
77e36d1acc risc-v/mpfs: introduce IHC driver
This provides an example of Asymmetric Multiprocessing (AMP). The
master from Linux sends pings that this NuttX echoes back. The system
uses RPMsg from OpenAMP.

The Inter-Hart Communication module is present in the vendor's software
stack with the tag "2021.11". The software is present on github at the
polarfire-soc project. The following conditions must be met:

 1. FPGA programmed with 2021.11 software
 2. HSS (Vendor bootloader) with 2021.11 software
 3. U-boot and Linux kernel from 2011.11 software

Currently the IHC works as a slave only on the hart number 4.

On the NuttX side, this patch uses rptun that incorporates rpmsg and
virtio. If it used only rpmsg and virtio, the future maintenance would
likely be much heavier. Using rptun also simplifies many things.

Upon success, the master side from Linux may issue an example test:

root@icicle-kit-es-amp:/opt/microchip/amp/rpmsg-pingpong# ./rpmsg-pingpong

However, the rpmsg-pingpong.c (compiled on target with gcc), may need to
be modified as seen below to match the device id:
 - char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.0";
 + char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.1024";

This work uses a separate linker script. Due to a bug yet unknown to date,
a small NuttX, when loaded by the vendor HSS bootloader, will cause the
Linux kernel to hang at boot. Thus, the binary size is increased with
a section 'filler_area' whose only purpose is to increase the image size
so that the Linux kernel will boot up.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-05-12 22:56:12 +08:00
wangbowen6
bc61e71b94 crypto: change type uint32_t to size_t in aes_cypher() arguments.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-05-12 22:28:54 +08:00
Ville Juven
47e85b68fe arch/addrenv: Change text write enable/disable to generic mprot
Implement a generic access rights modification procedure instead
of the procedures that only do one thing (enable/disable write)
to one section (text).
2022-05-12 22:28:31 +08:00
Masayuki Ishikawa
45beda286b arch: risc-v: Enable FPU for qemu-rv only if EXPERIMENTAL=y
Summary:
- Because a context switch issue still exists with FPU,
  it should be enabled only if EXPERIMENTAL=y

Impact:
- None

Testing:
- Tested with ostest

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-11 21:57:16 +08:00
Xiang Xiao
8634e8de64 Replace all sem_xxx with nxsem_xxx
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-10 15:08:36 +03:00
dytang
96b0209366 riscv/pmp: fix bug: PMP_CFG_FLAG_MASK makes pmp cfg fail. 2022-05-08 00:26:24 +03:00
Xiang Xiao
e84e5f0e1d arch: Add gcov related config for arm/risc-v/xtensa
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-06 14:43:57 -03:00
Xiang Xiao
45fb96c508 esp32x/wlan: Fix error: increment of a boolean expression
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-05 16:23:32 -03:00
Ville Juven
9af8b740e6 Elf loader: give temporary write access to user .text memory
When the .elf file is loaded from disk, the kernel must be given write
access to the allocated .text section in the task's address environment.

The access is removed after the elf is loaded and relocations are done.

NOTE:
The reason this works for the ARM implementation, is that the ARM MMU
can be configured to give write access for the privileged mode, but
revoke write access for the user mode.

Regardless, it would be smart to revoke write access even for the
kernel, when the kernel does not need it. This framework allows doing
that, if someone wishes to take up the task.
2022-05-03 21:25:25 +09:00
Ville Juven
2fd29b6408 RISC-V: Fix bug in riscv_addrenv.c
Need 1 full page extra for heap, not 1 byte.
2022-05-03 03:05:22 +08:00
Masayuki Ishikawa
5a9b2920e8 arch: risc-v: Add support for semihosting and hostfs
Summary:
- This commit adds support for semihosting and hostfs

Impact:
- None

Testing:
- Tested with nsh and nsh64 (defconfig will be updated later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-02 19:46:58 +08:00
Ville Juven
0ae2e68116 RISC-V: Temporarily disable error about missing SBI 2022-05-02 16:13:15 +08:00
Ville Juven
31b916c485 MPFS: Add kernel space mappings
Mappings are done with vaddr=paddr.
- I/O space mapped with two gigapages
- Kernel space mapped to statically allocated page tables. 2MB of kernel
  memory is supported.
- Page pool is mapped to the kernel space, to allow virtual memory access
  for the kernel e.g. to initialize the page memory when it is allocated.
2022-05-02 16:13:15 +08:00
Ville Juven
3f6504076e MPFS: Add page pool allocation 2022-05-02 16:13:15 +08:00
Ville Juven
cccfe31d0c MPFS: Add sources for CONFIG_ARCH_ADDRENV 2022-05-02 16:13:15 +08:00
Ville Juven
6bf8623897 RISC-V: Fix crt0 file compilation
Definition of STACK_FRAME_SIZE was moved
2022-05-02 16:10:47 +08:00
Xiang Xiao
1fde7e17bb arch: Move -fstack-protector-all from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-01 23:54:15 +03:00
Xiang Xiao
aeb9c5d822 boards: Move -fno-strict-aliasing from Make.defs to Toolchain.defs
and migrate MAXOPTIMIZATION into ARCHOPTIMIZATION

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-01 11:36:41 +03:00
Xiang Xiao
1e23799455 arch/riscv: Optimize the syscall performance in kernel mode
by renaming riscv_dispatch_syscall to sys_callx, so the caller
don't need the immediate step(syscallx->riscv_dispatch_syscall)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-01 11:31:01 +03:00
Xiang Xiao
efce8bd198 Revert "arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm"
This reverts commit 9b7f9867aa.
2022-05-01 11:31:01 +03:00
Xiang Xiao
a021177de8 arch: Fix the style found in review
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-01 11:29:44 +03:00
Xiang Xiao
94cb0c6072 arch: Move -nostdinc++ to Tooolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-29 21:08:14 -03:00
Ville Juven
b3baf95835 UMM: Implement getter for address environment heap start vaddr
Using the Kconfig macro does not work for RISC-V target, as there the
user heap follows .data/.bss and does not obey any Kconfig provided
boundary.

Added stubs for ARM and Z80 also.
2022-04-29 23:13:16 +08:00
Ville Juven
e674d5cb86 RISC-V: Add crt0 file
Contains the code for the user process signal trampoline.
2022-04-29 02:02:15 +08:00
Ville Juven
0ccda05a82 RISC-V: Move wipe_page to pgalloc.h and rename it riscv_pgwipe 2022-04-29 02:02:15 +08:00
Ville Juven
3d8ba496a2 RISC-V: Add pgpool to vaddr utility function
The only mapping that is supported now is vaddr=paddr, but the function
DOES check that the address is within the page pool, so it is not
useless.
2022-04-29 02:02:15 +08:00
Ville Juven
1322f82802 RISC-V: Copy kernel memory mappings to userspace addrenv
Copy the kernel mappings to the new (user) address environment. The
copyuing is done exactly once. This relies on the fact that the kernel
L1/L2 mappings will never change, as all of the kernel memory is mapped
upon boot.
2022-04-29 02:02:15 +08:00
Ville Juven
57127b9429 RISC-V: Initial support for CONFIG_BUILD_KERNEL
This implements initial support for kernel build (address environments,
page allocator) for RISC-V.

This is done a bit differently compared to the ARMV7 implementation:

- Support implemented for Sv39 MMU, however the implementation should be
  extensible for other MMU types also.
- Instead of preserving and moving the L1 references around, a canonical
  approach is used instead, where the page table base address register
  is switched upon context switch.
- To preserve a bit of memory, only a single L1/L2 table is supported,
  this gives access to 1GiB of virtual memory for each process, which
  should be more than enough.

Some things worth noting:
- Assumes page pool is mapped with vaddr=paddr mappings
- The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are
  ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used
  for ARCH_DATA_RESERVE
- ARCH_DATA_RESERVE is placed at the beginning of the userspace task's
  address environment
2022-04-29 02:02:15 +08:00
Gustavo Henrique Nihei
ffab2dc628 risc-v: Restrict Fence instruction for chips that support S-mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-04-28 01:18:46 +08:00
Gustavo Henrique Nihei
1967805b91 risc-v: Fix format specifier in debug log
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-04-28 01:18:46 +08:00
chao.an
cbef8681fe arch/risc-v: add support for GCC LTO
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-27 23:42:37 +08:00
Ville Juven
216574bba8 OpenSBI: Add riscv_hardfp.S to compilation
It will just become an empty object if FPU support is not included.
2022-04-27 23:20:51 +08:00
dytang
d7cc3f9275 RISC-V: workaround for the RV64 SoC which does not has mem mapped MTIMER currten value regs. 2022-04-27 22:48:54 +08:00
Abdelatif Guettouche
587145a881 riscv/Makefile: Delete old target used for debugging.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-27 12:58:57 +08:00
Xiang Xiao
fc16cfaefe Correct the code alignment found in review
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-26 11:34:28 +03:00
Ville Juven
6546789b7e RISC-V: Add syscall support for vfork
If vfork is called via syscall (PROTECTED/KERNEL build) need to set up
return parameters for syscall. Otherwise the SW will get lost.
2022-04-25 16:23:17 +03:00
Xiang Xiao
8f8ee25a9c boards: Move -g from Make.defs to Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-25 16:23:03 +03:00