Commit Graph

15802 Commits

Author SHA1 Message Date
Jukka Laitinen
c7acbb80d8 arch/arm/src/stm32h7/stm32_dma.c: Allow transfer from peripheral to AXI SRAM
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-14 17:31:06 -06:00
Jukka Laitinen
f5571b2550 arch/arm/src/stm32h7/stm32_dma.c: Fix DEBUGASSERT compilation
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-14 17:31:06 -06:00
Jukka Laitinen
8f559b1276 arch/arm/src/stm32h7/stm32_dma.c: Split long lines to pass style checks
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-14 17:31:06 -06:00
Jukka Laitinen
1e0f416a93 arch/arm/src/stm32h7: Make flash program size configurable
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-14 17:27:49 -06:00
Jari Nippula
de8f3b73d5 arch/arm/src/stm32h7/stm32_flash.c: fix write and erase
Correct flash write and erase functions, they inherit some
broken code from other platforms. Also fix the confusion between
eraseblock(sector) and page sizes.

Signed-off-by: Jari Nippula <jari.nippula@intel.com>
2020-05-14 17:27:49 -06:00
Jukka Laitinen
f9a886f8b7 arch/arm/src/stm32h7/stm32_flash.c: Lock flash option register
If the flash option register was locked before modifying it, return
it to the locked state after modify.

Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-14 17:27:49 -06:00
Nathan Hartman
8d985819b3 Fix typos
Comments only. No functional changes.
2020-05-14 10:49:44 -06:00
chao.an
8bce416c25 sim/tapdev: follow the tunnel MTU size
Change-Id: Ia32255517650d95ea3a675ee9fe5b69e923fb51a
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-05-14 07:54:57 -06:00
Gregory Nutt
801b9d6e5f arch/arm: Remove support for old redundant toolchains.
Remove support for the Codesourcery, Atollic, DevKitArm, Raisonance, and CodeRed toolchains.  Not only are these tools old and no longer used but they are all equivalent to standard ARM EABI toolchains.  Retaining specific support has no effect (they are still supported, but now just as generic EABI toolchains).
2020-05-13 18:41:10 +01:00
Jukka Laitinen
e989147119 arch/arm/src/stm32h7: Add support for spi simplex configurations
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-13 07:29:14 -06:00
Jukka Laitinen
574b2593e6 arch/arm/src/stm32h7/stm32_spi.c: Correct the dmacapable check
First, configure the dmacfg in spi_dmarxsetup and spi_dmatxsetup. Then,
check for dmacapable, and only after that set up the dma.

This way the dmacapable actually works, and we don't need to initialize
the dmacfg structures twice.

Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-13 07:29:14 -06:00
Jukka Laitinen
d1c406d65d arch/arm/src/stm32h7/stm32_spi.c: Correct cache flush
When starting dma transfer, the dcache for the TX buffer should be cleaned.
"flush" performs also invalidate, which is unnecessary. The TX buffer
can be unaligned to the cahche line in some(most) cases, whereas RX buffer
can never be.

The cache for the receive buffer can be dirty and valid before call to exchange.
Thus another memory access (hitting the same cache line) may corrupt receive data
while waiting for transfer to complete. So the receive buffer should be
invalidated before the transfer

Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-13 07:29:14 -06:00
Jukka Laitinen
ace63ef74a arch/arm/src/stm32h7/stm32_spi.c: Remove un-used local variable
Causes compilation warning

Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-13 07:29:14 -06:00
Jukka Laitinen
63af18eaf9 arch/arm/src/stm32h7/stm32_spi.c: Fix long lines to pass style checks
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-13 07:29:14 -06:00
Jukka Laitinen
4967352c33 arch/arm/src/stm32h7/stm32_ethernet.c: Comment and debug assertion fixes
Modify some comments and debug assertions, which inherit from previous versions
and make no sense. Also add a few nerr printouts to make it easier to debug
running out of buffers

Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-13 06:51:57 -06:00
Jukka Laitinen
db492ca03b arch/arm/src/stm32h7/stm32_ethernet.c: Break long lines to pass style checks
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-13 06:51:57 -06:00
Jukka Laitinen
d618dad296 arch/arm/src/stm32h7/Make.defs: arm_mpu.c was added twice
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-13 06:51:57 -06:00
Jukka Laitinen
2ef571453a arch/arm/src/stm32h7/stm32_allocateheap.c: Fix compilation when CONFIG_MM_REGIONS == 1
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
2020-05-13 06:51:57 -06:00
rajeshwaribhat
3d7678ad9b nxstyle corrections for .c and .h file modified by PR1030 2020-05-13 06:46:56 -06:00
Gregory Nutt
4664642cf7 Board specific code moved to boards directory and ipv6 support added
Added support to crashdump for rx65n on sbram
Board specific code moved to boards directory and ipv6 support added
2020-05-13 06:46:44 -06:00
Xiang Xiao
9607152e68 arm/gic: Don't pirnt log in arm_decodeirq
it is unsafe place to do this

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I47fdb1a34a7f1d5c5d3c4f3c0030a60bf01c43c2
2020-05-13 06:33:56 -06:00
Xiang Xiao
7ffafa3654 Remove executable bit from source code
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-05-13 06:32:13 -06:00
Masayuki Ishikawa
77f15c8b17 arch: cxd56xx: Apply the latest cxd56_dma.c and cxd56_spi from SDK
See the following commit in SDK:

  commit 62a2fb4fd3001aefad9ec3b2e2e7c47e5b0f21e1
  Author: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
  Date:   Fri Jan 24 13:32:04 2020 +0900

      Enable dummy transfer by SPI using DMA

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-05-13 13:11:08 +02:00
Xiang Xiao
517974787f Rename clock_systime[r|spec] to clock_systime_[ticks|timespec]
follow up the new naming convention:
https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+OS+Internal+Functions
2020-05-10 14:35:50 -06:00
Gregory Nutt
3ac629bdfb Run all .c and .h files modifed by the PR though nxstyle. 2020-05-09 16:58:42 -03:00
Gregory Nutt
f92dba212d sched/sched/sched.h: Make naming of all internal names consistent:
1. Add internal scheduler functions should begin with nxsched_, not sched_
2. Follow the consistent naming patter of https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+OS+Internal+Functions
2020-05-09 16:58:42 -03:00
Gregory Nutt
4b44b628ea Run nxstyle against all .c and .h files modified by this PR.
All complaints fixed except for those that were not possible to fix:

- Used of Mixed case identifier in ESP32 files.  These are references to Expressif ROM functions which are outside of the scope of NuttX.
2020-05-09 14:19:08 -03:00
Gregory Nutt
a4218e2144 include/nuttx/sched.h: Make naming of all internal names consistent:
1. Add internal scheduler functions should begin with nxsched_, not sched_
2. Follow the consistent naming patter of https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+OS+Internal+Functions
2020-05-09 14:19:08 -03:00
Xiang Xiao
b7d922960f Fix nxstyle issue
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-05-08 07:20:49 -06:00
Gregory Nutt
2d78ed7c7e arch/sim/src/nuttx-names.dat: Add __errno()
Needed to avoid collision with the host on simulator build.
2020-05-08 01:58:25 +01:00
Ouss4
958999c443 arch/mips/src/common/mips_usestack.c: Include tls.h header. 2020-05-07 18:41:43 -06:00
Gregory Nutt
3dca5eba15 Completes the Implementation of the TLS-based errno
- Remove per-thread errno from the TCB structure (pterrno)
- Remove get_errno() and set_errno() as functions.  The macros are still available as stubs and will be needed in the future if we need to access the errno from a different address environment (KERNEL mode).
- Add errno value to the tls_info_s structure definitions
- Move sched/errno to libs/libc/errno.  Replace old TCB access to the errno with TLS access to the errno.
2020-05-07 23:11:34 +01:00
Ouss4
a6da3c2cb6 arch/*/*_checkstack.c: Get aligned address only when CONFIG_TLS_ALIGNED is
enabled.
2020-05-07 12:04:51 -06:00
Ouss4
e74899ff6d arch/risc-v/src/common/riscv_createstack.c: Fix the stack_color name. 2020-05-07 12:04:32 -06:00
Gregory Nutt
c2244a2382 Remove CONFIG_TLS
A first step in implementing the user-space error is force TLS to be enabled at all times.  It is no longer optional
2020-05-07 12:04:16 -06:00
Pierre-Olivier Vauboin
8d8ceee838 boards/arm/stm32h7/stm32h747i-disco: support for FMC SDRAM 2020-05-07 10:29:01 -06:00
Masayuki Ishikawa
1cf62c7db9 arch: k210: Fix cpu1 hangup during boot with qemu 2020-05-07 08:33:50 +02:00
Ouss4
6eb6d31c32 Fix nxstyle complaints 2020-05-06 21:56:40 -06:00
Ouss4
d56c613b7d arch/avr,renesas,risc-v: The *_getsp function was moved to a header
file, remove it from the different source files that used to implement
it to avoid redefinitions.
2020-05-06 21:56:40 -06:00
Ouss4
a4dd967440 arch/: Implement up_tls_info() for the rest of the architectures. 2020-05-06 21:56:40 -06:00
Ouss4
1e3ec6ecd0 arch/: Implement Thread Local Storage for the rest of the architectures.
The change consisted on modifying *_usestack.c and *_createstack.c
2020-05-06 21:56:40 -06:00
Xiang Xiao
3e00d182d2 Fix nxstyle issue
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-05-06 20:53:11 -06:00
Xiang Xiao
94bb2e05bb syslog: Code outside libc shouldn't call nx_vsyslog directly
since nx_vsyslog is the implementation detail

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-05-06 20:53:11 -06:00
Yang Chung-Fan
6b1f94ee49 arch: x86_64: real-mode bootstrap code should jump to 1M 2020-05-06 08:35:09 -07:00
Yang Chung-Fan
ffa2027226 arch: x86_64: Add option to disable interrupt controller initialization 2020-05-06 08:35:09 -07:00
Yang Chung-Fan
c63c8a3841 arch: x86_64: Add real-mode bootstrap stub 2020-05-06 08:35:09 -07:00
Yang Chung-Fan
9ab6b92ad7 arch: x86_64: move the disable multiboot2 marco around to retain labels 2020-05-06 08:35:09 -07:00
Yang Chung-Fan
235d905001 arch: x86_64: remove leftover debug output 2020-05-06 23:33:46 +08:00
Masayuki Ishikawa
4ca19e7e74 arch: k210: Set CPU clock based on PLL0 settings 2020-05-05 17:21:32 -07:00
Gregory Nutt
bda24f09c2 libs/libc/tls/tls_getinfo.c: Add tls_get_info()
Move the logic to get TLS information from an inline function to a normal function.  For the unaligned case, it is probably too large to be inlined.

Also fixes some minor things from review of previous commits.
2020-05-05 18:56:33 +01:00