Commit Graph

19384 Commits

Author SHA1 Message Date
raiden00pl
c7e6366e91 stm32f0l0g0/SPI: enable SPI for STM32G0 2022-07-15 11:38:36 -03:00
raiden00pl
f702c89c33 stm32f0l0g0/SPI: configure DMA support individually for each SPI 2022-07-15 11:38:36 -03:00
raiden00pl
056e11a3e5 stm32f0l0g0/SPI: only SPI1 and SPI2 are present in STM32 M0 devices 2022-07-15 11:38:36 -03:00
raiden00pl
47e29d9402 stm32f0l0g0: remove references to non-existent ADCs, only ADC1 present on STM32 M0/M0+ devices 2022-07-15 11:36:43 -03:00
Masayuki Ishikawa
82cd9b0a4a arch: arm64: Add stack coloration for SMP
Summary:
- This commit adds stack coloration for SMP

Impact:
- None

Testing:
- Tested with qemu-a53:nsh_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-07-15 16:16:02 +08:00
Masayuki Ishikawa
3682bcd4b3 arch: arm64: Fix do_stackcheck()
Summary:
- Since the stack coloration is done for every 32bits
  this function should be done in the same way.

Impact:
- None

Testing:
- Tested with qemu-a53:nsh

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-07-15 16:16:02 +08:00
qinwei1
e77b06721b arch: arm64: ARMv8-A support for NuttX
N/A

Summary:

Arm64 support for NuttX, Features supported:

1. Cortex-a53 single core and SMP support: it's can run into nsh shell at
   qemu virt machine.

2. qemu-a53 board configuration support: it's only for evaluate propose

3. FPU support for armv8-a: FPU context switching at NEON/floating-point
  TRAP is supported.

4. psci interface, armv8 cache operation(data cache) and smccc support.

5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko

Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail

Note:
1. GCC MACOS issue
The GCC 11.2 toolchain for MACOS may get crash while compiling
float operation function, the following link describe the issue
and give analyse at the issue:

https://bugs.linaro.org/show_bug.cgi?id=5825

it's seem GCC give a wrong instruction at certain machine which
without architecture features

the new toolchain is not available still, so just disable the MACOS
cibuild check at present

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-07-14 09:35:49 -04:00
Gustavo Henrique Nihei
68c722c051 xtensa/esp32: Build patched IDFBoot for Protected Mode support
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 14:57:57 +08:00
Gustavo Henrique Nihei
60b7479f12 xtensa/esp32: Avoid ROM functions due to error with PIDs 2-7
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 14:57:57 +08:00
Gustavo Henrique Nihei
27fc3c959d xtensa/esp32: Configure the PID controller for privilege separation
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 14:57:57 +08:00
Gustavo Henrique Nihei
76acfef5ec xtensa/esp32: Add support for Protected Mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 14:57:57 +08:00
Gustavo Henrique Nihei
e24621d545 arch: Convert DEBUGASSERT(false) into more intuitive DEBUGPANIC()
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 12:08:45 +08:00
Gustavo Henrique Nihei
8a4c9c3489 arch: Fix typo in "register" word
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-13 22:57:19 +03:00
Alan Carvalho de Assis
7d3eefbdce Review: Small improvements
Fixes suggested by Gustavo and Petro
2022-07-13 14:28:36 -03:00
Alan Carvalho de Assis
1e03a70258 Add DMA support to SPI and small issues on SPI driver 2022-07-13 14:28:36 -03:00
Alan Carvalho de Assis
368d65459c xtensa/esp32s3: Add DMA support to SPI 2022-07-13 14:28:36 -03:00
Alan Carvalho de Assis
1cb3c0d630 xtensa/esp32s3: Add support to Generic DMA 2022-07-13 14:28:36 -03:00
Petro Karashchenko
24abf9d5d9 arch/arm/samv7: EMAC bugfixes
1. Fix error recovery mechanism during transmission error
   handling (enable transmission at the end).
2. Fix compilation / operation with CONFIG_SAMV7_EMAC_PREALLOCATE=y
3. Enable fully configured address space for transmission queues
   to allow sending packets with length more than 976 bytes. With
   partially configured address space the AHB error is generated
   during transmission of long packets.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-07-12 18:34:37 +08:00
Eero Nurkkala
14447600ac risc-v/mpfs: usb: fix illegal reads
With faster data transfer rates, it was seen that the read
requests occasionally were issued while the USB RX operation
was actually in progress.  This patch makes sure the system
doesn't accidentally read the RX fifo while it's being filled
up, but rather, checks for the RXCSRL_REG_EPN_RX_PKT_RDY_MASK
flag.  This flag indicates the packet is ready to be read.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-07-12 18:34:28 +08:00
Gustavo Henrique Nihei
5e32aa14bf risc-v/esp32c3: Fix verification of ROM function return values
cache_dbus_mmu_set and cache_ibus_mmu_set return positive values in case
of errors, so DEBUVERIFY could never detect them since this macro checks
for negative values.
Besides, the successful execution of those functions is mandatory for
the reliable operation under Protected Mode, so the verification is
always performed, even when DEBUG is not enabled.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-12 10:56:59 +08:00
raiden00pl
5c1c18af03 stm32g0: add support for USART3 and USART4 2022-07-10 21:02:23 -03:00
raiden00pl
b179c46178 arch/stm32f0l0g0: add support for stm32l053 2022-07-09 23:37:33 +08:00
Nathan Hartman
849f760b77 Fix various typos 2022-07-08 02:15:54 +08:00
Abdelatif Guettouche
0bdf713df0 risc-v/esp32c3: Add the rest of the reset causes.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-07-08 01:06:35 +08:00
Xiang Xiao
3daa18b661 arch: Remove the unnecessary #if/#endif in assert
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-07 19:25:47 +03:00
Xiang Xiao
9ff0971d3f arch: Correct the order of stack related information in assert
forget to update in this patch:
commit b02db04e00
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date:   Sun Jun 5 17:10:19 2022 +0800

    arch/assert: Keep the thread dump column order same as ps

    Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-07 19:25:47 +03:00
curuvar
aa6ec6518c Added ADC to RP2040 2022-07-07 12:45:28 -03:00
Gustavo Henrique Nihei
f3e8decad2 xtensa: Build sources required for supporting CONFIG_BUILD_PROTECTED
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-05 23:07:00 +08:00
Gustavo Henrique Nihei
cd1ed92844 xtensa: Build sources for supporting CONFIG_SCHED_BACKTRACE
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-05 23:07:00 +08:00
Gustavo Henrique Nihei
b9703619b5 xtensa: Unify common options within a single Make.defs
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-05 23:07:00 +08:00
Huang Qi
a4e867b8d4 arch/arm/Kconfig: Add description for ARM_THUMB to make it configurable
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-07-05 19:34:18 +08:00
Xiang Xiao
fcc48c2254 arch/arm: Don't include arch/arch.h in include/irq.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:25:56 +03:00
Xiang Xiao
9ab3417882 arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place
1.Move __XSTR from include/arch.h to include/irq.h
2.Move  FLOAD/FSTORE and REGLOAD/REGSTORE from include/arch.h to src/common/riscv_internal.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:25:56 +03:00
Xiang Xiao
c20ed58879 arch: Remove the inclusion of arch/irq.h from chip/irq.h
since arch/irq.h will include chip/irq.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:03:47 +03:00
Alan Carvalho de Assis
922ebe5b96 Fix IOMUX function number 2022-07-01 23:34:21 +08:00
Xiang Xiao
3d1ce144df arch: Move up_getsp from arch.h to irq.h
since all other special register operation in irq.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-01 10:44:55 -03:00
curuvar
0c3db448bb Added Adafruit Feather RP2040, Adafruit KB2040 and Added neopixel driver to support RP2040 2022-06-30 22:13:49 -07:00
Sergey Nikitenko
4285274c31 New stm32wb chip family 2022-07-01 12:13:58 +08:00
Nathan Hartman
a3688b0c3b tiva: Add UART CTS/RTS support
* arch/arm/src/tiva/common/tiva_lowputc.c
  (tiva_lowsetup):
    For each UART, if Kconfig enables RTS/CTS (e.g.,
    CONFIG_UART0_IFLOWCONTROL and/or CONFIG_UART0_OFLOWCONTROL),
    configure the corresponding GPIO(s).

* arch/arm/src/tiva/common/tiva_serial.c:
  (struct up_dev_s):
    If CONFIG_SERIAL_IFLOWCONTROL, add a bool field 'iflow'. If
    CONFIG_SERIAL_OFLOWCONTROL, add a bool field 'oflow'. This is
    inspired by the implementation for kinetis.
  (g_uart0priv, g_uart1priv, g_uart2priv, g_uart3priv, g_uart4priv,
   g_uart5priv, g_uart6priv, g_uart7priv):
    If Kconfig enables RTS/CTS for a UART (e.g.,
    CONFIG_UART0_IFLOWCONTROL thru CONFIG_UART7_OFLOWCONTROL), set
    the corresponding iflow and/or oflow flag(s).
  (up_setup):
    Check the above-mentioned iflow and oflow flags and set or unset
    the RTSEN and/or CTSEN bits in the UART's CTL register to enable
    the feature.
2022-07-01 11:52:02 +08:00
Gustavo Henrique Nihei
5ce77fad1b arch: Remove "0x" prefix preceding "%p" specifier on format string
The "p" format specifier already prepends the pointer address with "0x"
when printing.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 22:08:58 +03:00
Gustavo Henrique Nihei
ea829cf7d5 xtensa/esp32s3: Add driver for I2C peripheral in Master mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 00:32:17 +03:00
Gustavo Henrique Nihei
0657621848 xtensa/esp32s2: Add driver for I2C peripheral in Master mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 00:32:02 +03:00
Gustavo Henrique Nihei
31cddc922c xtensa/esp32s2: Sync GPIO driver implementation with ESP32-S3
Sync driver interfaces, also fixes the handling of special pin value for
esp32s2_gpio_matrix_in and esp32s2_gpio_matrix_out functions

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 00:10:41 +08:00
Gustavo Henrique Nihei
2d6cd7e580 xtensa/esp32s2: Fix the number of GPIO IRQs
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 00:10:41 +08:00
Eero Nurkkala
ef28d915fe risc-v/mpfs: ihc: don't start rptun automatically
Starting the rptun with the autostart flag set will cause significant
delays at the boot, as it will wait for the master to be up. U-boot/linux
combination may take more than 10 seconds to boot to the point where the
rpmsg bus is initialized.

For now, the user needs to initialize the rptun separately, for example,
by issuing the following command:

  rptun start /dev/rptun/mpfs-ihc

This command will also block if started before the rpmsg bus master is up.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-28 11:34:38 -03:00
Ville Juven
cfebb5a5c1 risc-v: Move common memory map to its own file from riscv_internal
Move the linker defined symbols to a separate file, so they can be
accessed without pulling in everything from riscv_internal.h and
whatever it includes (e.g. syscall.h drags in a lot).
2022-06-28 14:41:56 +03:00
Huang Qi
bc8cf2c501 arch/arm/armv7-m: Fix error link argument for compiler-rt
Fix:
```
ld.lld: error: unknown argument '-/home/huang/Work/vwear/prebuilts/clang/linux/arm/bin/../lib/clang-runtimes/armv7em_hard_fpv4_sp_d16/lib/libclang_rt.builtins-armv7em.a'
```

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-06-28 12:38:36 +03:00
dependabot[bot]
4f8c8815d6 Spi driver for Stm32wl55
IRQ and DMA mode is not implemented
2022-06-28 10:38:03 +08:00
zouboan
fd8eaf4f42 arch/stm32_capture_lowerhalf.c: add lower half support of capture 2022-06-28 10:35:43 +08:00
Nimish Telang
4afd25b567 this flag is meaningless for the linker 2022-06-27 20:03:03 -03:00