Commit Graph

21604 Commits

Author SHA1 Message Date
Eren Terzioglu
c8d7c81cb9 risc-v/esp32c3: Rename legacy approach esp32c3 as esp32c3-legacy 2024-01-30 08:32:05 +01:00
Eren Terzioglu
4c4d62ff93 Rename espressif folder as common/espressif 2024-01-30 08:32:05 +01:00
Eren Terzioglu
721c37a876 risc-v/esp32c6: Remove duplicated esp32c6 implementation 2024-01-30 08:32:05 +01:00
Yanfeng Liu
0f169f50c4 risc-v/k230: add big core support
Previously NuttX runs on little core of K230, this patch allows NuttX to
run on the big core as well.

Within folder `arch/risc-v/src/k230`:

- Changes:

    - CMakeLists.txt      add k230_hart.c to sources list
    - Make.defs           add k230_hart.c to sources list
    - chip.h              add inclusion to k230_hart.h etc
    - k230_irq.c          move sbi_late_init() to k230_hart.c
    - k230_start.c        add support to run on big core
    - hardware/:
      - k230_memorymap.h  add T-Head C908 specific CSR

- Additions:

    - k230_hart.c         sbi_late_init w/ hart initialization
    - k230_hart.h         header file

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-29 09:06:28 +01:00
raiden00pl
9d761b8ca4 arch/{nrf52|nrf53|nrf91}/tim.c: fix typo
fix offset for EVENT COMPARE0
2024-01-28 09:46:34 -08:00
Yanfeng Liu
f69f0674f6 arch/risc-v: add status fields for VS and XS
add defintions for vector extension and additional user-mode
extension fields for MSTATUS and SSTATUS registers.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-28 06:38:25 -08:00
ThomasNS
fff193324d xmc4 ccu4 register map 2024-01-27 20:14:02 -08:00
Yanfeng Liu
bb63f8f36d risc-v/canmv230: add CMake support
Adding CMakeLists.txt files to support CMake build system.
Note that only FLAT build works now due to limitations of current
CMake build system.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-27 00:56:57 -08:00
Benign X
8ba74d06c6 arch/sim: fix X11 compile failed 2024-01-27 00:51:32 -08:00
chenwen@espressif.com
ba1b96e9d9 xtensa/esp32s3: Add DMA peripheral to spi driver configuration
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-01-26 19:14:04 -08:00
chenwen@espressif.com
8bef8ee9d5 xtensa/esp32s3: Fix crash issue that occurs when deleting a semaphore in WPA3
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-01-26 04:45:26 -08:00
Takeyoshi Kikuchi
8571893435 arm: sama5: sam_serial: fix to compile with "UART Flow control enabled" on SAMA5D2.
SAMA5D2 has UART (TX/RX only) and FLEXCOM USART (with control pins).
UART has only TX/RX, so if I try to use flow control with FLEXCOM USART,
there is no register definition on the UART side and get a compilation error.

Signed-off-by: Takeyoshi Kikuchi <kikuchi@centurysys.co.jp>
2024-01-26 11:25:23 +08:00
Michal Lenc
addfa1c030 samv7: fix QSPI DMA option not showing in menuconfig
Commit 03e5c02 introduced option to have both standard SPI and QSPI
in SPI mode on one system. However this change broke the appearance of
QSPI driver configuration menu entry in menuconfig as it was dependent
on !SAMV7_QSPI_IS_SPI (which is now true for all MCUs having standard
SPI ability in QSPI driver).

This change makes sure the menu is correctly shown when QSPI driver
used.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-01-25 18:19:27 -08:00
raiden00pl
a12fdd8876 cosmetic changes after pci code rebase 2024-01-25 09:09:30 -08:00
raiden00pl
2e758f33ee fix various compilation errors after pci code rebase 2024-01-25 09:09:30 -08:00
Brennan Ashton
0ed4123326 x86_64: Early framebuffer console
This adds support for creating an early frame buffer and primatives for
writing to this frame buffer as a console. This does require the font
infrastructure as well as multiboot2.

Additionally this can now be used with a UEFI bootloader long as it
boots NuttX via Multiboot2.  There does seem to be a PCI interrupt
issue when running in UEFI mode.

I was able to boot my laptop using this and see PCI devices enumerate.

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

x86_64: Add conditionals around the multiboot framebuffer
2024-01-25 09:09:30 -08:00
Ville Juven
a188cf3480 mpfs_corespi: Fix firing of stale interrupt after warm reset
After warm reset the interrupt source in the HW block is not explicitly
cleared, thus once the interrupt source is enabled the old / stale interrupt
fires immediately.

This causes a DEBUGASSERT() failure on line 808 mpfs_spi_unload_rx_fifo:
  DEBUGASSERT(nwords > 0);
2024-01-25 11:23:12 -03:00
Tiago Medicci Serrano
c4f76ff867 esp32c3: Fix building native MCUboot from sources
This commit fixes building native MCUboot from sources by getting
the required sources from `esp-hal-3rdparty` repository and enable
building MCUboot and using it as the 2nd stage bootlaoder.
2024-01-25 11:22:39 -03:00
Tiago Medicci Serrano
a2673d3bcd esp32c3: Improve selection of the bootloader being used on Kconfig
- A pre-built IDF bootloader is used by default;
- `ESP32C3_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32C3_PARTITION_TABLE.
2024-01-25 11:22:39 -03:00
Tiago Medicci Serrano
641a0df27f esp32s3: Improve selection of the bootloader being used on Kconfig
- A pre-built IDF bootloader is used by default;
- `ESP32S3_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32S3_PARTITION_TABLE.
2024-01-25 11:22:39 -03:00
Tiago Medicci Serrano
1e1ea7bb5d esp32s2: Improve selection of the bootloader being used on Kconfig
- A pre-built IDF bootloader is used by default;
- `ESP32S2_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32S2_PARTITION_TABLE.
2024-01-25 11:22:39 -03:00
Tiago Medicci Serrano
ec3714c816 esp32: Improve selection of the bootloader being used on Kconfig
- A pre-built IDF bootloader is used by default;
- `ESP32_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32_PARTITION_TABLE.
2024-01-25 11:22:39 -03:00
Tiago Medicci Serrano
7ac14b544e risc-v/espressif: Select simple boot by default for RISC-V
Simple boot is a method of booting that doesn't depend on a 2nd
stage bootloader. Please note that some of the ESP-IDF bootloader
features are not available using simple boot, such as partition
tables and OTA: most of these features are implemented in NuttX
and MCUboot.
2024-01-25 11:22:39 -03:00
Michal Lenc
fba4b2593c samv7: refactor DAC driver
This commit refactors DAC driver. The functionality remains the same
but driver start up is now done in dac_setup (after application called
open function) instead of sam_dac_initialize (called from BSP). This
ensures that driver does not take resources (timer, interrupt) until
opened. Implementation of dac_shutdown is also provided, therefore
the driver frees resources once closed.

This change is consistent with other drivers implementation.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-01-24 18:46:33 -08:00
Michal Lenc
55ec92e181 samv7: add support for SPI mode in USART peripheral
USART peripheral can work in SPI mode as well. This commit adds support
for such functionality. Only 1 slave device is supported by the
peripheral therefore board level does not have to ensure correct CS
setup.

The usage of the peripheral is the same as with other SPI drivers.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-01-23 17:16:35 -03:00
chenwen@espressif.com
bdd02cc624 xtensa/esp32s3: Add APIs to release DMA channel resources
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-01-23 17:16:16 -03:00
Almir Okato
f8b0b06b97 esp32c3-generic: add simple boot support
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also makes this bootloader configuration as default
for esp32c3-generic target and removes the need for running
'make bootloader' command for it.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-01-23 04:09:25 -08:00
w2016561536
6b5ca79509 esp32s3/spi-dma: Fix spi dma transfer.
Fix esp32s3 spi dma transfer only transmit first byte and receive empty problem.
2024-01-23 04:05:52 -08:00
Lee Lup Yuen
62c358946d risc-v/bl808: Flush MMU Cache after updating SATP
Ox64 BL808 crashes with a Page Fault when we run `getprime` then `hello`. This is caused by the T-Head C906 MMU incorrectly accessing the MMU Page Tables of the Previous Process (`getprime`) while starting the New Process (`hello`).

To fix the problem, this PR flushes the MMU Cache whenever we point the MMU SATP Register to the New Page Tables. We execute 2 RISC-V Instructions that are specific to T-Head C906:

- DCACHE.IALL: Invalidate all Page Table Entries in the D-Cache
- SYNC.S: Ensure that all Cache Operations are completed

This is derived from the T-Head Errata for Linux Kernel. More details here: https://lupyuen.github.io/articles/mmu#appendix-flush-the-mmu-cache-for-t-head-c906

Modified Files:

- `arch/risc-v/src/common/riscv_mmu.h`: If needed, `mmu_write_satp()` calls `mmu_flush_cache()` (weak function) to flush the MMU Cache. (Like for T-Head C906)

- `arch/risc-v/src/bl808/bl808_mm_init.c`: Flush the MMU Cache for T-Head C906. Extend `mmuflags` from 32-bit to 64-bit to be consistent with `mmu_ln_setentry()`.

- `boards/risc-v/bl808/ox64/configs/nsh/defconfig`: Enable `ostest` in the Build Config. Update `CONFIG_BOARD_LOOPSPERMSEC` according to `calib_udelay`.
2024-01-23 01:25:20 -08:00
Yanfeng Liu
cba993df85 risc-v/cmake: add support to Ubuntu stock toolchain
Ubuntu stock toolchain `gcc-riscv64-unknown-elf` complains about
current CMake system (see issue#11573). This tries to fix it so
that both newer XPack and stock toolchains can be used with CMake.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-23 01:23:44 -08:00
David Sidrane
6c186b6084 stm32h7:serial make TX DMA busy when there are an outstanding transaction
If a TX DMA completion interrups a forground write.
    The TX DMA completion can start a dma_send and it will
    then followed by the forground write's dma_send
    stoping the,then in progress DMA.

    By atomicaly marking the tx dma busy, the forground
    write will not perform the dma_send, and will only
    enqueue the data. At the next TX dma completion any
    data pending in the tx queue will be sent
2024-01-22 06:06:01 -08:00
ThomasNS
1c28bf2ed1 fix typo: it is P4.0 and not P0.4 2024-01-22 05:46:33 -08:00
Tiago Medicci Serrano
0ecc3aaad2 esp32: Explicitly fail on boot-up for unsupported ESP32 versions.
ESP32 is supported on NuttX starting from chip revision 3.0. This,
however, didn't prevent the user from using older chip revisions,
which caused unexpected behaviors. This commit checks chip revision
before finishing booting NuttX.
2024-01-21 06:33:25 -08:00
Tiago Medicci Serrano
2954551ef6 esp32/hardware/esp32_efuse.h: Update macros for registers.
This commit is intended to update the EFUSE's register content and
update related configs:
 - Remove duplicated configs from `esp32_soc.h`;
 - Add missing header files from APB registers;
 - Add missing macro definitions from EFUSE;
 - Update related code to use the new macros;
2024-01-21 06:33:25 -08:00
Tiago Medicci Serrano
8752e6d863 esp32/hardware: Rename efuse_reg.h to esp32_efuse.h. 2024-01-21 06:33:25 -08:00
Takeyoshi Kikuchi
bca8df7d65 arm: sama5: sam_ehci: fix transfer cancellation process.
The logic of the conditional expression that determines whether
the QH is a target QH or not is reversed in the process of canceling
a transfer in INPROGRESS state.

Therefore, the QH in INPROGRESS state is not released and subsequent
communication is not successful.

Checked with CDC-ACM driver and cu command.

Signed-off-by: Takeyoshi Kikuchi <kikuchi@centurysys.co.jp>
2024-01-20 19:54:26 -08:00
Dong Heng
85238fa4de xtensa/esp32s3: Fix USB pull-up and pull-down issue
ESP32-S3 USB OTG device can't call function esp32s3_pullup to notify USB host that it connects or disconnects.
2024-01-18 17:53:16 -08:00
ThomasNS
e966fff597 add GPIO_U1C0_SCLKOUT_3 P4.0 for spi2 on xm4 2024-01-18 17:49:56 -08:00
chao an
02acf2d2a4 risc-v/cmake: set nostdlib to c compiler
To avoid build break:

ld: riscv-none-elf/lib/rv64imafdc_zicsr/lp64d/crt0.o: in function `.L0 ':
(.text+0x8): undefined reference to `__bss_start'
ld: (.text+0x10): undefined reference to `_end'
ld: (.text+0x36): undefined reference to `main'
collect2: error: ld returned 1 exit status

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-18 09:53:53 +01:00
chao an
2fd95611cb risc-v/cmake: configurable vendor ISA extensions
merge below commit into cmake:

1. risc-v/toolchain: configurable vendor ISA extensions

This option allows the platform to enable some vendor-customized ISA extensions,
E.g OpenHW, SiFive, T-Head.

SiFive Intelligence Extensions:
    SiFive Vector Coprocessor Interface(VCIX): xsfvcp
    SiFive FP32-to-int8 Ranged Clip Instructions: Xsfvfnrclipxfqf
    SiFive Matrix Multiply Accumulate Instructions: Xsfvfwmaccqqq
    SiFive Int8 Matrix Multiplication Instructions: XSFvqmaccqoq
Command Line:
    xsfvcp0p1_xsfvfnrclipxfqf0p1_xsfvfwmaccqqq0p1_xsfvqmaccqoq0p1

2. "V" Standard Extension for Vector Operations
3. "Q" Standard Extension for Quad-Precision Floating-Point

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-18 09:53:53 +01:00
w2016561536
829ec6d5e4 esp32s3/pwm: Fix pwm output
1. Fix pwm output always low problem.
2. Add multi channel support in defconfig
2024-01-17 22:42:08 -03:00
Yanfeng Liu
1e9434e2db arch/: remove duplicated task exit logs
Newly added logging in `sched/task_exit.c` obsoletes the existing
ones in `arch/up_exit()`, thus remove the latter to reduce duplications.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-17 09:18:17 -08:00
Yanfeng Liu
87c9a0ee76 risc-v/k230: add NUTTSBI based kernel build support
Previously k230 kernel build needs OpenSBI wrapping for use on
target, thus leading to larger program and memory overheads.
This patch adds alternative small overhead kernel build support.

Changes:

- in arch/risc-v/src/k230:
  - k230_head.S          entrance renamed for sake of NUTTSBI
  - k230_irq.c           add M-mode handling for NUTTSBI case
  - k230_mm_init.c       add L3 table for smaller RAM case
  - hardware/k230_plic.h add PLIC_CTRL definition
  - Make.defs            use CHIP_ASRCS to fix entrance selection
- in boards/risc-v/canmv230/scripts:
  - Make.defs            add support for NUTTSBI case

Additions:

- in boards/riscv/canmv230/:
  - scripts/ld-nuttsbi.script  link script for NUTTSBI case
  - configs/nsbi/defconfig     config for NUTTSBI case

The artifact nuttx.bin from this configuration can be used directly
on target as OpenSBI wrapping is not needed.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>

fix typo
2024-01-17 10:31:29 -03:00
w2016561536
6a0eeb1b3e esp32s3/spi: Add SPI bus init in bringup and fix SPI bus 2 and 3 conflict
1. Add spi bus init in esp32s3_bringup.c
2. Fix IOMUX conflict between spi bus 2 and 3
3. Add spi defconfig
4. Follow the standard of NuttX
2024-01-17 09:29:20 -03:00
chao an
95fcc286a2 risc-v/toolchain: configurable vendor ISA extensions
This option allows the platform to enable some vendor-customized ISA extensions,
E.g OpenHW, SiFive, T-Head.

SiFive Intelligence Extensions:
    SiFive Vector Coprocessor Interface(VCIX): xsfvcp
    SiFive FP32-to-int8 Ranged Clip Instructions: Xsfvfnrclipxfqf
    SiFive Matrix Multiply Accumulate Instructions: Xsfvfwmaccqqq
    SiFive Int8 Matrix Multiplication Instructions: XSFvqmaccqoq
Command Line:
    xsfvcp0p1_xsfvfnrclipxfqf0p1_xsfvfwmaccqqq0p1_xsfvqmaccqoq0p1

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
ce201bba61 risc-v/kconfig: move ARCH_HAVE_MMU into mmu type define
Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
52e99bc66b risc-v/toolchain: move zicsr/zifencei extension into Kconfig
Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
f95bbb2949 risc-v/toolchain: add "V" Standard Extension into command line
"V" Standard Extension for Vector Operations

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
3ee4227668 risc-v/toolchain: add "Q" Standard Extension into command line
"Q" Standard Extension for Quad-Precision Floating-Point

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
90f24ec29d arch/risc-v: add ARCH_QPFPU for Quad-Precision Floating-Point
new options to enable toolchain support for quadruple precision
(128 bits or 16 bytes) floating point if both the toolchain and
the hardware support it.

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00