This commit backs out most of commit b4747286b1. That change was added because sem_wait() would sometimes cause cancellation points inappropriated. But with these recent changes, nxsem_wait() is used instead and it is not a cancellation point.
In the OS, all calls to sem_wait() changed to nxsem_wait(). nxsem_wait() does not return errors via errno so each place where nxsem_wait() is now called must not examine the errno variable.
In all OS functions (not libraries), change sem_wait() to nxsem_wait(). This will prevent the OS from creating bogus cancellation points and from modifying the per-task errno variable.
sched/semaphore: Add the function nxsem_wait(). This is a new internal OS interface. It is functionally equivalent to sem_wait() except that (1) it is not a cancellation point, and (2) it does not set the per-thread errno value on return.
sched/semaphore: Add nxsem_post() which is identical to sem_post() except that it never modifies the errno variable. Changed all references to sem_post in the OS to nxsem_post().
sched/semaphore: Add nxsem_destroy() which is identical to sem_destroy() except that it never modifies the errno variable. Changed all references to sem_destroy() in the OS to nxsem_destroy().
libc/semaphore and sched/semaphore: Add nxsem_getprotocol() and nxsem_setprotocola which are identical to sem_getprotocol() and set_setprotocol() except that they never modifies the errno variable. Changed all references to sem_setprotocol in the OS to nxsem_setprotocol(). sem_getprotocol() was not used in the OS
libc/semaphore: Add nxsem_getvalue() which is identical to sem_getvalue() except that it never modifies the errno variable. Changed all references to sem_getvalue in the OS to nxsem_getvalue().
sched/semaphore: Rename all internal private functions from sem_xyz to nxsem_xyz. The sem_ prefix is (will be) reserved only for the application semaphore interfaces.
libc/semaphore: Add nxsem_init() which is identical to sem_init() except that it never modifies the errno variable. Changed all references to sem_init in the OS to nxsem_init().
sched/semaphore: Rename sem_tickwait() to nxsem_tickwait() so that it is clear this is an internal OS function.
sched/semaphoate: Rename sem_reset() to nxsem_reset() so that it is clear this is an internal OS function.
STM32L4 RTC, PM: small fixes to subseconds handling, ADC power-management hooks
* STM32L4 ADC: add PM hooks from Motorola MDK
* STM32L4 RTC: add up_rtc_getdatetime_with_subseconds
* STM32 RTC: workaround for potential subseconds race condition
In all recent STM32 chips reading either RTC_SSR or RTC_TR is supposed to lock
the values in the higher-order calendar shadow registers until RTC_DR is read.
However many old chips have in their errata this silicon bug (at least F401xB/C,
F42xx, F43xx, L15xxE, L15xVD and likely others):
"When reading the calendar registers with BYPSHAD=0, the RTC_TR and RTC_DR
registers may not be locked after reading the RTC_SSR register. This happens
if the read operation is initiated one APB clock period before the shadow
registers are updated. This can result in a non-consistency of the three
registers. Similarly, RTC_DR register can be updated after reading the RTC_TR
register instead of being locked."
* STM32L4 RTC: correct RTC_SSR and RTC_TR read ordering
In all recent STM32 chips reading either RTC_SSR or RTC_TR is supposed to lock
the values in the higher-order calendar shadow registers until RTC_DR is read.
Change the register read ordering to match this and don't keep a workaround
for a hypothetical race condition (not in any L4 errata, lets for once assume
ST's silicon works as it is documented...)
* STM32L4 PM: remove useless #ifdefs and old non-L4 STM32 code
Approved-by: Gregory Nutt <gnutt@nuttx.org>
STM32, STM32 F7: LTDC and DMA2D drivers are not permitted to set the errno.
SIM LPC31xx: Serial and console drivers are not permitted to set the errno.
SAMv7, STM32, STM32 L4: DAC and ADC drivers are not permitted to set the errno.
stm32:stm32f40xxx I2C ensure proper isr handling
Injecting data errors that causes a STOP to be perceived by the
driver, will continually re-enter the isr with SB not set and BTF
and RxNE set. This changes allows the interrupts to
be cleared and propagates a I2C_SR1_TIMEOUT to the waiting task.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Injecting data errors would cause the driver to
continually reenter the isr with BERR an RxNE.
This fix allows the error to be cleared and
propagated to the waiting task.
Injecting data errors would cause the driver to
continually reenter the isr with BERR an RxNE.
This fix allows the error to be cleared and
propagated to the waiting task.
Actually write something to the DAC DMA buffer.
Change-Id: I1b2516ac26fb17f5242611b56be8926c5f40c2c7
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
On a very memory constrained device with a single task. The
sem_wait and sem_post operations can be disabled, to save space.
The default is blocking enabled.
This commit add a config STM32_OTGFS_VBUS_ CONTROL which lets us selectively disable VBus sensing and control. I also sneaked in a change to disable the configgpio call for the ID pin, which is only used in OTG mode which isn't supported yet. The only pins that need to be initialized should be OTGFS_DP and OTGFS_DM.
These changes let a USB mouse enumerate on my platform if it's plugged in on power-up. Plugging, unplugging, clicking, or moving the mouse cause NSH to stop responding. Because I'm using the ramlog, I don't have useful debug messaging yet, so there's a lot more work I have to do to troubleshoot it or get my JTAG debugging set up, but these patches shouldn't hurt anything. I'm hoping my issue is something simple I overlooked in configuration.
I'm planning to add similar changes for the OTGHS peripheral (using integrated full speed phy) but I still need to test those changes before submitting patches.
- compile issues because of missing RTC_MAGIC #defines
- missing functionality based on RTC_MAGIC in RTC based on stm32_rtcounter.c
- IRQ setup from up_rtc_initialize was later reset in up_irqinitialize
- write access to backup registers without enabling access to backup domain
- possible races in set/cancel alarm
tested with STM32F103C8 only
device now wakes up from forced STANDBY mode by alarm
reload = timclk / info->frequency;
which I belive to be incorrect, it should be
reload = timclk / info->frequency - 1;
since starting to count from 0, if I want to output half of the TIM clock, I must count to 1 and not to 2.
Surely enough, the original code did output 140/3=47 MHz, while this correction does allow the output up to 70 MHz.
I am not sure this affects most users generating slow PWM (e.g. PX4) but for frequencies
close to the PCLK, indeed the difference becomes significant.
Trivially triggered with two or more threads write to regular syslog stream and to emergency stream. In this case, freeze happens because of mismatch of priv->ie (TXEIE == 0) and actually enabled interrupts in USART registers (TXEIE == 1), which leads to unhandled TXE interrupt
and causes interrupt storm for USART.
The reason was that the code hit the line "canerr("ERROR: No available mailbox\n");" in stm32_cansend, so can_xmit thinks it has sent the packet to the hardware, but actually has not. Therefore the transmit interrupt never happens which would call can_txdone, and so the size of the FIFO size does not decrease.
The reason why the code actually hit the mentioned line above, is because stm32can_txready uses a different (incomplete) condition than stm32can_send to determine if the mailbox can be used for sending, and thus can_xmit forwards the packet to stm32can_send. stm32can_txready considered mailboxes OK for sending if the mailbox was empty, but did not consider that mailboxes may not yet be used if the request completed bit is set - stm32can_txinterrupt has to process these mailboxes first.
Note that I have also modified stm32can_txinterrupt - I removed the if condition, because the CAN controller retries to send the packet until it succeeds. Also if the condition would not evaluate to true, can_txdone would not be called and the FIFO size would not decrease also.
Add clock_resynchronize for better synchronization of CLOCK_REALTIME and CLOCK_MONOTONIC to match RTC after resume from low-power state.
Add up_rtc_getdatetime_with_subseconds under CONFIG_ARCH_HAVE_RTC_SUBSECONDS to allow initializing (and resynchronizing) system clock with subseconds accuracy RTC.
New interface allows checking if RTC time has been set. This allows to application to detect if RTC has valid time (after
reset) or should application attempt to get real time by other means (for example, by launching ntpclient or GPS).
Zero wait-state for flash can be configured when:
Range 1 and SYSCLK <= 16 Mhz
Range 2 and SYSCLK <= 8 Mhz
Range 3 and SYSCLK <= 4.2 Mhz
Medium performance voltage range (1.5V) can be configured when SYSCLK is up to 16 Mhz and PLLVCO up to 48 Mhz.
Writing to a flash sector while starting the erase of other sector
have a undefined behavior so lets add a semaphore and syncronize
access to Flash registers.
But for the semaphore to work it needs to be initialized so each
board needs call stm32_flash_initialize() on initialization, so
to avoid runtime problems it is only using semaphore and making
it thread safe if initialized, after all boards starts to call
stm32_flash_initialize() we can remove the boolean and the check.
Erase a sector from the second bank cause the bit 4 of SNB being set
but never unsed, so trying to erase a sector from the first bank
was acually eraseing a sector from the second bank.
Save elapsed time before handling I2C in stm32_i2c_sem_waitstop()
This patch follows the same logic as in previous fix to
stm32_i2c_sem_waitdone().
It is possible that a context switch occurs after I2C registers are read
but before elapsed time is saved in stm32_i2c_sem_waitstop(). It is then
possible that the registers were read only once with "elapsed time"
equal 0. When scheduler resumes this thread it is quite possible that
now "elapsed time" will be well above timeout threshold. In that case
the function returns and reports a timeout, even though the registers
were not read "recently".
Fix this by inverting the order of operations in the loop - save elapsed
time before reading registers. This way a context switch anywhere in the
loop will not cause an erroneous "timeout" error.
This patch follows the same logic as in previous fix to
stm32_i2c_sem_waitdone().
It is possible that a context switch occurs after I2C registers are read
but before elapsed time is saved in stm32_i2c_sem_waitstop(). It is then
possible that the registers were read only once with "elapsed time"
equal 0. When scheduler resumes this thread it is quite possible that
now "elapsed time" will be well above timeout threshold. In that case
the function returns and reports a timeout, even though the registers
were not read "recently".
Fix this by inverting the order of operations in the loop - save elapsed
time before reading registers. This way a context switch anywhere in the
loop will not cause an erroneous "timeout" error.
