Commit Graph

1656 Commits

Author SHA1 Message Date
Huang Qi
8ee461fa0e riscv: Add CSRs for Smcsrind/Sscsrind
Add CSR registers for RISC-V Indirect CSR Access (Smcsrind/Sscsrind) Extension.

Refer to: https://github.com/riscvarchive/riscv-indirect-csr-access/tree/main

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-06-21 03:02:59 +08:00
Inochi Amaoto
caeb1757f6 arch/risc-v: Improve the SBI function handle
To simplify processing, the existed SBI function code is just
invoking the ecall and return the error value. This omits
potential return value in "a1", which is defined in SBI doc.
Add the "sbiret" struct so it can handle all the return value.

In addition, there are some minor improvement:
1. move the SBI related interface to a separate file to make it clean.
2. add all necessary SBI ecall interface macro until version 2.0.
3. add an utilty function to convert sbi error numner to standard
error number.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-06-19 20:55:10 +08:00
Yanfeng Liu
8720594f4d risc-v/k230: initial rv64ilp32 support
This enables NuttX FLAT build with rv64ilp32 on CanMV230 device.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-19 15:32:19 +08:00
Yanfeng Liu
07463e2de1 arch/risc-v: revise mtime address for rv64ilp32
This revises the `mtime` and `mtimecmp` register addresses to
support rv64ilp32.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-19 01:53:21 +08:00
Yanfeng Liu
28ae3b3849 arch/risc-v: revise MMIO for rv64ilp32
This revises `getregXX` and `setregXX` for rv64ilp32 to overcome
the limitation of compiler generated addresses and reach devices
in a larger range.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-18 10:50:49 +08:00
Stuart Ianna
66df96e384 arch/risc-v/include/elf.f: Support coredump for rv32 and rv64 targets.
Adds the missing elf_gregset_t type definition so pr_regs field can be
resolved. Coredumps can be produced for both 32 and 64 bit targets.
2024-06-18 10:41:56 +08:00
Lup Yuen Lee
008803865f boards/risc-v: Add support for Milk-V Duo S SBC (SOPHGO SG2000 SoC)
This PR adds support for Milk-V Duo S 64-bit RISC-V SBC, based on SOPHGO SG2000 SoC (T-Head C906 Core). Most of the code is derived from NuttX for Ox64 BL808. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-sg2000

Modified Files:

`boards/Kconfig`: Added Milk-V Duo S board

`arch/risc-v/src/sg2000/sg2000_timerisr.c`: Fixed MTIMER_FREQ for sleep() to work correctly

New Files in boards/risc-v/sg2000/milkv_duos:

`src/sg2000_appinit.c`: Startup Code

`include/board.h`: Milk-V Duo S Definitions

`include/board_memorymap.h`: Memory Map

`src/etc/init.d/rc.sysinit`, `rcS`: Startup Script

`src/.gitignore`: Ignore the tmp filesystem

`scripts/ld.script`: Linker Script

`scripts/Make.defs`: Milk-V Duo S Makefile

`src/Makefile`: Milk-V Duo S Makefile

`Kconfig`: Milk-V Duo S Config

`configs/nsh/defconfig`: Build Config for `milkv_duos:nsh`

Updated Documentation:

`platforms/risc-v/sg2000/index.rst`: New page for SOPHGO SG2000 SoC

`platforms/risc-v/sg2000/boards/milkv_duos/index.rst`: Building and booting NuttX for Milk-V Duo S
2024-06-18 00:13:35 +08:00
Lee Lup Yuen
8e30c13441 arch/risc-v: Add support for SOPHGO SG2000 SoC (T-Head C906)
This PR adds support for the SOPHGO SG2000 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for Milk-V Duo S SBC.

Most of the code was derived from NuttX for Ox64 BL808. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-sg2000

Modified Files in arch/risc-v:

`Kconfig`: Added ARCH_CHIP_SG2000 for SG2000 SoC

New Files in arch/risc-v:

`include/sg2000/chip.h`: SG2000 Definitions

`include/sg2000/irq.h`: External Interrupts

`src/sg2000/chip.h`: Interrupt Stack Macro

`src/sg2000/sg2000_allocateheap.c`: Kernel Heap

`src/sg2000/sg2000_head.S`: Linux Header and Boot Code

`src/sg2000/sg2000_irq.c`: Configure Interrupts

`src/sg2000/sg2000_irq_dispatch.c`: Dispatch Interrupts

`src/sg2000/sg2000_memorymap.h`: Memory Map

`src/sg2000/sg2000_mm_init.c`, `sg2000_mm_init.h`: Memory Mgmt

`src/sg2000/sg2000_pgalloc.c`: Page Allocator

`src/sg2000/sg2000_start.c`: Startup Code

`src/sg2000/sg2000_timerisr.c`: Timer Interrupt

`src/sg2000/hardware/sg2000_memorymap.h`: PLIC and UART Base Address

`src/sg2000/hardware/sg2000_plic.h`: PLIC Register Addresses

`src/sg2000/Kconfig`: SG2000 Config

`src/sg2000/Make.defs`: Makefile
2024-06-17 09:41:29 +08:00
Inochi Amaoto
e37348aeba arch/risc-v: Add support for S-mode flat build
There is no need to use kernel build for S-mode all the time. As cpu
scratch is supported for non kernel mode build, it is possible to use
flat build for S-mode.

Add flat build support for risc-v S mode.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-06-14 19:52:00 +08:00
Yanfeng Liu
8ebc3aa9e8 arch/risc-v: initial qemu-rv64ilp32 support
This applies uintreg_t in risc-v commons and fixes araised ci issues
for multiple devices. The FLAT build runs on qemu-rv64ilp32 target.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-14 19:50:00 +08:00
Yanfeng Liu
33afbaadb9 arch/risc-v: add rv64ilp32 toolchain
This adds support of rv64ilp32 toolchain available from Github repo
`ruyisdk/riscv-gnu-toolchain-rv64ilp32`. With this 32-bit nuttx can
be generated for RV64 devices.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-14 19:50:00 +08:00
Neale Ferguson
73b15a87dc Fix SHMODULEFLAGS so that we link dynamically correctly
* arch/risc-v/src/common/Toolchain.defs
  arch/xtensa/src/lx6/Toolchain.defs
  arch/xtensa/src/lx7/Toolchain.defs
  - Define SHMODULEFLAGS etc. for sotest/dynload
  - Add --entry=__start to SHMODULEFLAGS

* boards/arm64/qemu/qemu-armv8a/scripts/Make.defs
  boards/sim/sim/sim/scripts/Make.defs
  - Define SHMODULEFLAGS etc. for sotest/dynload
2024-06-12 23:21:16 -03:00
Neale Ferguson
5033966d8c Add flags for building shared objects for architectures supporting dynamic loading
* arch/arm/src/common/Toolchain.defs
  arch/risc-v/src/common/Toolchain.defs
  boards/sim/sim/sim/scripts/Make.defs
  - Add SHCCFLAGS and SSHLDFLAGS
2024-06-12 23:21:16 -03:00
Eren Terzioglu
0cf7676aca esp32[c3|c6|h2]: Add SPI Slave support 2024-06-12 22:53:19 -03:00
Eren Terzioglu
62af2993a4 esp32h2: Change delimiter constant with variable 2024-06-12 23:35:24 +08:00
Eren Terzioglu
99ea8b7832 esp32[c3|c6|h2]: Add gspi master support 2024-06-12 23:35:24 +08:00
Tiago Medicci Serrano
6c3eeb7d5c espressif: Remove outdated config about IDF bootloader
For newer devices, IDF bootloader is not supported because the
devices are able to boot directly into NuttX or use MCUBoot to
enable OTA and security features.
2024-06-12 16:11:56 +08:00
Tiago Medicci Serrano
480ad6b631 esp: Make the legacy bootloader (IDF bootloader) option visible
This commit enables users to select the legacy bootloader (IDF
bootloader) in `menuconfig` directly. Please note, that this is a
legacy option intended to support devices already deployed and it
isn't recommended for new designs.
2024-06-12 16:11:56 +08:00
Matheus Catarino
c6eea4ad8b add LDC2 (dlang) support
*Note:* ldmd2 is ldc2-wrapper, allow using dmd frontend flags.
      This support may be extended to gdc (gnu) if nuttx developers demand it
  or are interested in it.
2024-06-06 09:32:56 +08:00
Jani Paalijarvi
b32a1dfd3d risc-v/mpfs: Add error handling for PMP conf
Check return value of mpfs_board_pmp_setup() and
jump to mpfs_board_pmp_error() in case of error.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-06-05 12:07:02 -03:00
Eren Terzioglu
24af23e49c esp32[c3]: Add XTWDT support 2024-06-04 17:42:07 -03:00
Stuart Ianna
e3056c781e arch/risc-v/riscv_mtimer: Update the mtimecmp value once per interrupt event.
Cache the next timeout value in the drivers instance and update the mtimecmp value once. This is advantageous as the opensbi ecall to set the timer is expensive in systems which don't have the supervisor mode timer extension.
2024-06-02 09:28:19 -03:00
Ville Juven
e6973c764c riscv/syscall: Optimize user service call performance
This patch changes how user service calls are executed:
Instead of using the common interrupt logic, execute the user service
call directly.

Why? When a user makes a service call request, all of the service call
parameters are already loaded into the correct registers, thus it makes
no sense to first clobber them and then reload them, which is what the
old logic does. It is much more effective to run the system call directly.

During a user system call the interrupts must be re-enabled, which the
new logic does as soon as we know the exception is a user service call
request.

This patch does NOT change the behavior of reserved system calls (like
switch_context), only the user service call request is affected.
2024-06-01 10:40:53 -03:00
Ville Juven
a5574d9485 risc-v_percpu: Add TCB to the per CPU structure
Also, convert the type to union; we don't need the list element once
the item has been popped from the free list (the linkage is never needed
when the item is in use).
2024-06-01 10:40:53 -03:00
Ville Juven
6bad48e4c7 riscv_syscall.S: Remove duplicated code
Return from exception is common code for both system calls and
exceptions
2024-06-01 10:40:53 -03:00
Stuart Ianna
1f02c05c6d arch/litex/litex_arch_alarm: Support tickless schedular with arch alarm.
This provides an alternate tickless scheduling method, which uses the riscv
mtimer as a timebase, allowing the time and timeh registers to used
throughout an application.

The exiting tickless method, using Litex's timer0 has been left in place, as
it is a more performant option, but currently has the potential issue
identified in #11189.
2024-05-31 10:21:44 +08:00
Ville Juven
c1f3245167 riscv-v/fork.S: Fix clobbering of s0 in fork()
Value of s0 (callee-saved) must be preserved through the call, use
a0 (caller-saved) to calculate the original SP instead.
2024-05-31 02:29:48 +08:00
xuxin19
275ec7102c cmake:bugfix CMake compilation options settings should not use strings
when repeatedly enabling and disabling string-controlled configurations,
the generated toolchain configuration may be incorrect.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-05-30 10:02:10 -03:00
Jani Paalijarvi
cfa544357e mpfs_mpu: Check that size is valid for MPUCFG
The size must be power-of-two for NAPOT according to the the PMP spec.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-05-24 21:32:55 +08:00
Jani Paalijarvi
9d4bd915eb riscv_pmp.c: Check that size is power of two for NAPOT
The size must be power-of-two according to the the PMP spec.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-05-24 21:32:55 +08:00
Eren Terzioglu
ea9eea4096 esp32[c3|c6|h2]: Add MWDT1 support 2024-05-24 13:59:03 +08:00
Eren Terzioglu
aa0bb55529 esp32[c3|c6|h2]: Add RWDT support 2024-05-24 13:59:03 +08:00
Eren Terzioglu
44e118eaf2 esp32[c3]: Add RTC IRQ support 2024-05-24 13:59:03 +08:00
Yanfeng Liu
f8749ef0e0 arch/risc-v: guard tcb->name usage
Add guard for tcb->name field usage as it is not always available.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-22 19:06:07 +08:00
Yanfeng Liu
7db71c8ee4 ci/riscv: fix unused var in esp_twai.c
This is to fix issue in [this log](https://github.com/apache/nuttx/actions/runs/9173629303/job/25222879619):

```
Configuration/Tool: esp32c3-generic/twai esp32c6-devkitm/twai esp32c6-devkitc/twai  esp32h2-devkit/twai
Error: common/espressif/esp_twai.c:242:7: error: variable 'ret' set but not used [-Werror=unused-but-set-variable]
```

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-22 16:40:13 +08:00
yinshengkai
20ebe0e64c Replace all asserts in kernel code with ASSERT
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-05-17 10:18:16 -03:00
Tiago Medicci Serrano
a00fbbeb9f espressif: Add option to disable the GIT_DEPTH to pull submodules
By default, submodules are cloned with `--depth=1`. This continues
to be true if `DISABLE_GIT_DEPTH` environment variable is not
defined (and it is not defined by default). But, if defined the
submodules will be fully cloned (without the `--depth` parameter).
2024-05-17 19:10:46 +08:00
Jukka Laitinen
9257af55f1 risc-v/mpfs: Change linker symbols _ssbi_ddr and _esbi_ddr into _ssbi_ram and _esbi_ram
The original names are confusing; the symbols' addresses point to the start and end of the
sbi executable ram area. This may also reside in l2lim and not in ddr, depending on the
configuration, and this is defined in the linker script.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-05-16 17:14:43 -03:00
Tiago Medicci Serrano
8a37d1ff1c espressif: Minor changes to keep consistency between sources
This commits replicates some changes on files that were originally
written for other Espressif SoCs and inspired new implementations.
Eventually, these new implementations were improved and this commit
replicates these changes on the original sources.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
c412dadcb9 esp32c3/wifi: Add support for the Wi-Fi in ESP32-C3
This commit introduces support for both station and softAP modes.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
7ed64e7234 esp32c3: Substitute / to $(DELIM)
Substitute `/` to `$(DELIM)` to make it compatible with other
implementations.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
2c4963dcd6 esp32c6/wifi: Add support for the Wi-Fi in ESP32-C6
This commit introduces support for both station and softAP modes.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
9e8c9ea47f esp: Update libc stubs to properly acquire/release locks.
Avoid using static mutex and recursive mutex as the resource to be
acquired/release. Instead, create a specific lock for each call if
it does not exist.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
47b0cae778 esp/hr_timer: Fix issue with timed-out timers 2024-05-14 22:10:45 +08:00
simbit18
d1789d84e8 fix nxstyle
fix Relative file path does not match actual file.
2024-05-13 22:24:36 +02:00
Inochi Amaoto
4d2d9ecf39 arch/risc-v: fix idle stack assign order
The bc022f8cd8 introduces a static way to calculate idle stack
address for risc-v platform. However, it uses the reverse order
to access idle stack, which breaks boards with smp configuration.

Correct the idle stack order of g_cpux_idlestack.

Fixes: bc022f8cd8 ("arch/risc-v: unify idle stack calculation")
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-12 15:22:50 +09:00
Inochi Amaoto
bc022f8cd8 arch/risc-v: remove g_cpux_idlestack
As all the board allocate idle stack from _ebss. The idle stack
layout is fix and can be computed directly by using _ebss. There
is no need to use g_cpux_idlestack array anymore, remove it.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-11 17:57:59 +02:00
Inochi Amaoto
afb5a66847 arch/risc-v: unify idle stack calculation
As the stack layout is unified, it is possible to
use a unify formula to calculate the top of idle
stack.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-11 17:57:59 +02:00
simbit18
09bfaa7292 fix nxstyle
fix Relative file path does not match actual file.
2024-05-11 01:19:06 +08:00
hujun5
5cee996588 up_putc: int up_putc, enter_critical_section may be called
before kernel has been iniitialized,we use spin_lock_irqsave to replace.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-05-09 13:45:02 +08:00
Inochi Amaoto
f4a38c01df arch/risc-v: Make esp32 SoCs allocate idle stack after ebss
ESP32 SoC use a static allocated array as idle stack. To fit
the existed idle stack allocation, make idle stack allocated
from ebss for the whole esp32 series.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-08 15:43:41 +08:00
Yanfeng Liu
ef15b5296d riscv/virt: M-mode poweroff support
This adds poweroff support to `rv-virt/nsh` and `rv-virt/nsh64`.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-08 15:39:26 +08:00
Yanfeng Liu
c352b04155 risc-v/sbi: add SRST extenstion usage in S-mode
This adds SBI specfication v0.3 based `riscv_sbi_system_reset()` to
support SBI firmware based system reset in kernel mode.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-07 21:02:49 +08:00
chenwen@espressif.com
3a9d163aae esp32_c3/pm: Fix assert issue in PM mode
1. Adjust code to avoid PM wakelock->count less than or equal to 0.
    2. Fix some document format issues.

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-05-07 15:45:32 +08:00
Inochi Amaoto
04e40182ad arch/risc-v: Make bl602 allocate idle stack after ebss
Although almost all board support allocating idle stack after ebss,
bl602 have a different memory layout for idle stack. To unify them,
make idle stack allocated from ebss for bl602.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-06 15:04:24 -03:00
Ville Juven
0cd5689bcb riscv/pgmap: Fix bug in kernel page directory init
The L2 table was not connected -> results in random crashes. Also add
missing data sync barrier to the end.
2024-05-03 23:49:11 +08:00
Inochi Amaoto
bd895222eb arch/risc-v: implement sbi_ipi_send
And SBI ipi support.

Fixup: 4f63ca1418 ("arch/risc-v: unfiy IPI access)
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-02 16:08:13 +08:00
Inochi Amaoto
b283b949b6 arch/risc-v: implement standard ecall interface for nuttsbi
NuttSBI have a simple ecall interface for the kernel, which make
it hard to add new SBI call for NuttSBI. So implement standard
ecall interface for NuttSBI and make life easier.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-02 16:08:13 +08:00
chao an
8821a0396a arch/risc-v: correct minor issues regarding comments
The comment in riscv_vpu.S should be vector not floating

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-30 17:26:57 +08:00
Eren Terzioglu
891d67bb5e esp32[c3|h2|c6]: Add support to TWAI/CANBus controller 2024-04-30 10:03:22 +08:00
Philippe Leduc
3dc6b4c9bd Add basic support for locales in order to C++ streams to build and work for simple cases (POSIX / C locale).
Fix build with C++ GCC toolchain
2024-04-29 17:34:10 +08:00
Inochi Amaoto
c148e8f2af arch/risc-v: Fix typo in riscv_set_inital_sp
Set right name for the parameter description of riscv_set_inital_sp.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-28 17:24:31 +08:00
Inochi Amaoto
49b3f52db1 arch/riscv/qemu-rv: replace M-mode init code with SBI in kernel build
The qemu-rv use a small init code for M mode in kernel build.
It is hard-coding and is difficult to change. Due to the fact,
introduce a already mature SBI implement (e.g OpenSBI) to
replace existing code is a better choice.

This patch introduce some change for qemu-rv:
1. use SSTC to provide time interrupt in kernel build
2. remove uncessary M mode trap.

For simplicity, this patch does not add support for booting
nuttx for any core, but force boot core to start core 0 and
let core 0 do the initialization.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
Inochi Amaoto
3cabc92427 arch/risc-v: add risc-v SSTC extension support
SSTC extension allows nuttx to implement S-mode timer directly,
which is useful for starting at S-mode.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
Inochi Amaoto
1d7afb571f arch/risc-v: report correct interrupt stack base
As `up_get_intstackbase` supports per cpu stack base, fix
the report value with the cpu specific one.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
Inochi Amaoto
a33313413d arch/risc-v: introduce dynamic stack allocation.
It is misleading to allocate stack from static array and heap,
make all stack allocated from heap area.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
Inochi Amaoto
1ef3767f85 arch/risc-v: unfiy IPI access
Add ipi process abstract function support.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
chao an
1f7147129a arch/risc-v: fix break on kernel mode
merge conflicts lead to incorrect ifdef/endif scope

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-26 12:44:57 +09:00
chao an
a51ebeab4b arch/risc-v: decouple Per-CPU scratch with ARCH_USE_S_MODE
In some special chipsets, multiple CPUs may be bundled in one hardware
thread cluster, which results in hartid and cpuindex not being exactly
the same. The new option will decouple Scratch-based Per-CPU storage
with S-Mode to distinguish the real cpu index.

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-25 09:48:59 -03:00
chao an
da4c229312 arch/riscv: replace atomic operations to AMO
RISC-V provided fetch-and-op style atomic primitives as they scale
to highly parallel systems better than LR/SC or CAS. A simple
microarchitecture can implement AMOs using the LR/SC primitives,
provided the implementation can guarantee the AMO eventually
completes. More complex implementations might also implement AMOs
at memory controllers, and can optimize away fetching the original
value when the destination is x0.

Signed-off-by: chao an <anchao@lixiang.com>
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-04-25 18:23:58 +09:00
chao an
6086b1410b arch/risc-v: remove the hard code array of cpu idle stack
Do not limit the number of CPU idle stacks by hard code

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-24 11:58:19 +08:00
Yanfeng Liu
5c3fc2796b tools/export: fix names for app linker script and program entry.
This fixes names of program entry and linker script files so that to
support building kernel mode apps using CMake and export package.

flat and protected mode should be the same as before.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-04-24 11:40:16 +08:00
chao an
28044f7d5a arch/risc-v: add support of save/restore vector registers
Reference:
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
https://github.com/torvalds/linux/blob/master/arch/riscv/include/asm/vector.h

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-23 16:18:46 -03:00
chao an
4b086f595e arch/risc-v: rename local variable name to avoid shadowed declaration
In file included from common/addrenv.h:33,
                 from common/riscv_initialstate.c:36:
common/riscv_initialstate.c: In function 'up_initial_state':
common/riscv_internal.h:136:16: warning: declaration of 'regval' shadows a previous local [-Wshadow]
  136 |      uintptr_t regval; \
      |                ^~~~~~
common/riscv_initialstate.c:74:12: note: in expansion of macro 'READ_CSR'
   74 |   regval = READ_CSR(CSR_VLENB);
      |            ^~~~~~~~
common/riscv_initialstate.c:63:13: note: shadowed declaration is here
   63 |   uintptr_t regval;
      |             ^~~~~~

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-22 16:22:51 +08:00
chao an
d59f9186ca arch/risc-v: add llvm experimental extensions into command line
LLVM supports (to various degrees) a number of experimental extensions.
All experimental extensions have experimental- as a prefix. There is
explicitly no compatibility promised between versions of the toolchain,
and regular users are strongly advised not to make use of experimental
extensions before they reach ratification.

Fix compile error:
riscv64-unknown-elf-clang: error: invalid arch name 'rv64gcv_zfh_zvfh', requires '-menable-experimental-extensions' for experimental extension 'zvfh'

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-19 20:13:54 +08:00
chao an
e863e3dd37 arch/risc-v: add LLVM clang support
Verified on LLVM-Metal:
$ riscv64-unknown-elf-clang --version
(LLVM-Metal 15.9.0-2023.03.0) clang version 15.9.0
Target: riscv64-unknown-unknown-elf
Thread model: posix

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-19 12:27:56 +08:00
Huang Qi
93d75129de riscv: Add Vector CSRs to csr.h
The CSR register definitions from RVV 1.0 spec: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-registers

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-04-19 00:31:07 +08:00
Almir Okato
f4bbe276e1 esp32[c3|c6|h2]: Fix simple boot map_rom_segments
Currently Simple Boot image have fixed 2 ROM segments and
2 RAM segments, then the parsing iterator must stop when all
ROM segments are found.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-04-17 00:09:58 +08:00
Yanfeng Liu
200424e59d arch/risc-v: fix RV32 up_addrenv_destroy
This patch fixes the issue/12122 for RV32, where the scanning should be
limited to user space only.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-04-14 14:49:36 +08:00
Jakub Janousek
3ce84d1ba0 arch and board esp32c3-legacy: Add optional iCE40 FPGA loading support
Signed-off-by: Jakub Janousek <janouja9@fel.cvut.cz>
2024-04-12 10:19:58 -03:00
Inochi Amaoto
412d2ce113 arch/riscv: add T-HEAD CSR mapping
Add T-HEAD CSR mapping file.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-11 22:20:39 +08:00
Inochi Amaoto
bae686e127 arch/riscv: force using encoding macro for CSR access
Using CSR name depends on compiler support heavily, but CSR
encoding does not have this problem. It also make it easy to
add new CSR support even if the compiler does not support.

Unify CSR access by using the CSR encoding macro.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-11 10:43:48 +08:00
Huang Qi
9e78b235fe riscv: Add more debug related CSR definitions
This patch adds more debug related CSR definitions
to arch/risc-v/include/csr.h.

These definitions are from the RISC-V Debug Specification
Version 1.0 rc1 (https://github.com/riscv/riscv-debug-spec).

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-04-10 21:10:39 +08:00
ligd
3844efb5b8 stack: update up_get_intstackbase API to support cpu id
For crash dump all the CPU intstack

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-04-09 16:59:00 -03:00
simbit18
9967989b02 Fix Kconfig style
Remove spaces from Kconfig files
Remove TABs
Add comments
2024-04-09 10:49:23 +08:00
Eren Terzioglu
c0d7419d11 esp32[c3|h2|c6]: Bugfixes for filesystem errors 2024-04-09 10:48:40 +08:00
W-M-R
0ede3fc377 kasan: Implementing global variable out of bounds detection
Extracting global variable information using scripts:
kasan_global.py:
1. Extract the global variable information provided by the -- param asan globals=1 option
2. Generate shadow regions for global variable out of bounds detection
Makefile:
1. Implement multiple links, embed the shadow area into the program, and call it by the Kasan module

Signed-off-by: W-M-R <mike_0528@163.com>
2024-04-07 23:31:13 +08:00
Tiago Medicci Serrano
65bd548521 esp32[c3|c6|h2]: Fix RTC data placement
RTC data was not being correctly placed on RTC's memory data due to
linker issues. Also, the image's RTC memory segment was not being
properly parsed by the bootloader.
2024-04-05 02:50:19 +08:00
Eren Terzioglu
19b58a78da risc-v/espressif: Fix empty cpuint number 2024-04-02 16:40:24 -03:00
Tiago Medicci Serrano
9520edeb16 espressif/rmt: Fix minor issues regarding formatting and comments
This commit only fix minor issues regarding formatting and comments
2024-04-02 14:50:59 -03:00
Yanfeng Liu
3a59644485 build/cmake: kernel mode revision
This fixes kernel mode regression caused by #12011

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-30 12:21:59 +08:00
xuxin19
741de4b450 cmake:init protected-mode for CMake build
adjust link options for userspace elf
specify system libs and apps lib to only link with nuttx target in flat build mode

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-03-27 23:01:08 +08:00
Eren Terzioglu
f5030573b7 esp32[c3|c6|h2]: Fix filesystem test support 2024-03-26 20:56:48 +08:00
Eren Terzioglu
d322140464 boards/esp32c6: Add esp32c6 DevKitM board support 2024-03-26 09:43:08 +08:00
Eren Terzioglu
cfcedab76b arch/espressif: Fix esp32c6 strange characters on boot 2024-03-26 09:39:12 +08:00
Yanfeng Liu
56b125bb82 risc-v/arch.h: revising comments
This revises comments about page tables to help understanding.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-25 20:39:24 +08:00
Jukka Laitinen
1f6079814a arch/risc-v/src/common/supervisor/riscv_perform_syscall.c: Record the currently running task in risc-v syscall
If a context switch occurs in syscall, the g_running_task need to be recorded for assert logic.
This copies the logic from arm platforms

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-03-21 18:45:41 +08:00
Jukka Laitinen
f1c877d67d arch/risc-v/src/common/riscv_exception.c: Just _exit the user task causing an exception
We shouldn't panic the kernel when a user task excepts, we can just kill the user task and
it's children. Do this by returning to _exit() in kernel context.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-03-20 18:03:15 -03:00
Stuart Ianna
401b3e682c arch/risc-v/litex: Allow FDT to be passed from previous boot change.
Allows a flattened device tree to be passed from either openSBI or the LiteX bios. The FDT is registered can be used, if supported.
2024-03-20 20:53:17 +08:00
Yanfeng Liu
ea8682572c build/cmake: add initial KERNEL mode support
Currently only FLAT mode development can enjoy cmake build system. This
patch tries to add initial kernel mode support. It can build NuttX kernel
and libproxies.a, the latter will be further checked though.

This can already help to build an AMP remote node image as it can share
userland apps living in the AMP master node.

Major changes:

- in top folder:
  - CMakeLists.txt    adjust for KERNEL mode, separate from PROTECTED mode.
- in `syscall`:
  - CMakeLists.txt    add mksyscall target for stubs/proxies generation
- in `syscall/stubs`:
  - CMakeLists.txt    use dependency to mksyscall
- in `syscall/proxies`:
  - CMakeLists.txt    use dependency to mksyscall
- in `arch`:
  - CMakeLists.txt    separate KERNEL from PROTECTED mode.
- in `arch/risc-v/src`:
  - CMakeLists.txt    separate from PROTECTED mode, add sub folders.
- in `arch/risc-v/common`:
  - CMakeLists.txt    add sources and sub-folders for KERNEL mode.
- in `arch/risc-v/k230`:
  - CMakeLists.txt    add sources for KERNEL mode.
- in `boards/risc-v/k230/canmv230/src`:
  - CMakeLists.txt    adjust k230 specific scripts for kernel mode.

New additions:

- in `arch/risc-v/src/nuttsbi/`           add CMakeLists.txt
- in `arch/risc-v/src/common/supervisor/` add CMakeLists.txt

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-15 16:21:23 +08:00