Summary:
- I noticed that qemu-armv8a:netnsh_smp_hv does not detect
GICv2 on Raspi4B (ubuntu 22.04 server + qemu-8.1.2)
- According to the GIC-400 TRM, it says that the architecture
version can be obtained from GICC_IIDR (See Table 3-7)
- This commit fixes this issue.
Impact:
- Should be none
Testing:
- Tested with qemu-armv8a:netnsh_smp_hv on
- Raspi3B+ (ubuntu 22.04 server + qemu-8.1.2)
- Raspi4B (ubuntu 22.04 server + qemu-8.1.2)
- M1/MacBook Pro 2021 (macOS 13.6 + qemu-8.1.2)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.
We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.
Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.
use instrument_register to register entry function and exit function.
They will be called by the instrumented function
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Summary:
- I noticed that irq is enabled explicitly in arm64_cpu_idle.S
- The code is unnecessary since tasks, including the idle task,
are created with irq enabled in up_initial_state()
Impact:
- Should be none
Testing:
- qemu-armv8a:netnsh_smp_hv with qemu-7.2.4
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Before code is executed after being loaded into memory,
it is necessary to ensure the consistency of I and D cache.
The up_coherent_dcache function will flush the dache and
invalidate the icache to ensure cache consistency.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Only when SCTLR_ELn.WXN is set to 1, regions that are writable at ELn
are treated as non-executable. Therefore, when SCTLR_ELn.WXN is set to
0, regions that are writable at ELn can be executed, so the writable
attribute cannot be used to restrict the executable attribute.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
To compile arm64 NuttX, use the following command:
./tools/configure.sh -l qemu-armv8a:nsh_fiq
To run，use the following command
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
The BIT macro is widely used in NuttX,
and to achieve a unified strategy,
we have placed the implementation of the BIT macro
in bits.h to simplify code implementation.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
When we build NuttX on macOS, it shows many `sed` messages (and the build still completes successfully):
```text
$ tools/configure.sh pinephone:nsh
$ make
sed: illegal option -- r
```
This is due to the Makefiles executing `sed -r` which is not a valid option on macOS.
This PR proposes to change `sed -r` to `sed -E` because:
- `sed -E` on macOS is equivalent to `sed -r` on Linux
- `sed -E` and `sed -r` are aliases according to the GNU `sed` Manual
- `sed -E` is already used in nuttx_add_romfs.cmake, nuttx_add_symtab.cmake and process_config.sh
test config: ./tools/configure.sh -l qemu-armv8a:nsh_smp
Pass ostest
No matter big-endian or little-endian, ticket spinlock only check the
next and the owner is equal or not.
If they are equal, it means there is a task hold the lock or lock is
free.
Signed-off-by: TaiJu Wu <tjwu1217@gmail.com>
Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
Summary
Add ARM PCSI (Power State Coordination Interface) Support
for qemu. With the interface, Poweroff/PowerReset can be support
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
Adding virtual evaluate platform GoldFish. Which is based on
Android Goldfish Emulator, it's a ARM virt board but Android enhance
it with more featue
The patch set goldfish as a chip
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
when using new gcc verion like:
GNU ld (Arm GNU Toolchain 12.2.Rel1 (Build arm-12.24)) 2.39.0.20221210)
we will get link warning like:
aarch64-none-elf-ld: warning: XXX/nuttx has a LOAD segment with RWX permissions
The patch fix the warning through add link option --no-warn-rwx-segments
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
make debug print hex again add board include
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
remove ccache, add board memory map
remove board reset
Summary
this is a old implement for Arm64 trace but will failed
compile when enable CONFIG_SCHED_INSTRUMENTATION_SWITCH
remove it since it will never use for trace framework
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
