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84 Commits

Author SHA1 Message Date
Nathan Hartman
5f9cb6faf4 drivers/serial: Fix docstrings on UART interrupt handlers 2023-02-07 04:41:36 +08:00
Petro Karashchenko
f952b8456c assert: switch from ASSERT(0/false) to PANIC 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2023-01-26 10:15:34 +08:00
Xiang Xiao
70290b6e38 arch: Change the linker generated symbols from uint32_t to uint8_t * 
and remove the duplicated declaration

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-09-24 21:26:56 +02:00
Xiang Xiao
3c1c29f2c4 arch: move non arm g_current_regs defintion to common place 
to avoid the code duplicaiton

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-09-21 22:23:11 +02:00
Ville Juven
cfebb5a5c1 risc-v: Move common memory map to its own file from riscv_internal 
Move the linker defined symbols to a separate file, so they can be
accessed without pulling in everything from riscv_internal.h and
whatever it includes (e.g. syscall.h drags in a lot).
 2022-06-28 14:41:56 +03:00
Huang Qi
9d9d591b93 arch/risc-v: Unify common source include 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-05-31 07:59:33 +03:00
chao.an
3f65b562bb arch: inline up_interrupt_context() 
inline the up_interrupt_context() to avoid unnecessary stack pushes

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-05-26 04:36:07 +08:00
Petro Karashchenko
0fee5a2b84 nuttx: fix typos in comments 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-05-14 23:45:52 +08:00
Ville Juven
a014daf44f RISC-V: Add implementation for vfork 2022-04-25 15:44:32 +08:00
chao.an
5bdfae66ce arch/arm: export arm_saveusercontext() 
rename arm_saveusercontext() -> up_arm_saveusercontext()

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 22:22:16 +08:00
Huang Qi
1975878835 arch/risc-v: Apply common mtime driver to mtime based chps 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-12 12:14:40 +03:00
Ville Juven
b0a71ce3e7 RISC-V: Remove riscv_cpuindex.c from platforms that don't need it 
riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.

Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
 2022-04-12 01:59:35 +08:00
Huang Qi
9284770f75 arch/risc-v: Move epc adjustment to riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Huang Qi
833211680a arch/risc-v: Attach exception handler in common place 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Xiang Xiao
3a26cf6a02 arch/risc-v: Remove the unnecessary inclusion of board header files 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-07 11:25:12 +03:00
Ville Juven
c15b6701ce RISC-V: Implement option to run NuttX in supervisor mode (S-mode) 
- Add config "ARCH_USE_S_MODE" which controls whether the kernel
  runs in M-mode or S-mode
- Add more MSTATUS and most of the SSTATUS register definitions
- Add more MIP flags for interrupt delegation
- Add handling of interrupts from S-mode
- Add handling of FPU from S-mode
- Add new context handling functions that are not dependent on the trap
  handlers / ecall

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
      thus S-mode is not usable as is, yet.
 2022-04-01 16:19:42 -03:00
Petro Karashchenko
36b0b95eb1 arch/risc-v: include csr.h indirectly through nuttx/irq.h 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-31 19:34:52 +08:00
Huang Qi
32fe25278a arch/risc-v: Merge duplicated logic by riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 19:33:08 +08:00
Huang Qi
494230a841 arch/risc-v: Improve performance of context switch 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-26 07:19:09 +09:00
Petro Karashchenko
7afedda89e arch/risc-v: improve style consistency accross chip variants 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-25 10:26:15 -03:00
Huang Qi
00efcd3308 arch/risc-v: Merge riscv_getnewintctx into common 
And also mask the bits which should be preserved (from ISA spec)

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-19 17:38:18 +08:00
Huang Qi
807304f283 arch/risc-v: Rework riscv_get_newintctx 
Some fields of mstatus were marked as Reserved Writes Preserve Values, Reads Ignore Values (WPRI),
so we must keep its origin value with addition flags.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-17 15:43:30 +08:00
Xiang Xiao
54e630e14d arch: Merge up_arch.h into up_internal.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 09:32:17 +02:00
Huang Qi
e383439dda risc-v: Replace all inline assembly with macro 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-03 19:55:54 +08:00
Huang Qi
64130b4775 risc-v: Use _ebss instead of _default_stack_limit as idle stack base 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-13 14:37:57 +08:00
Huang Qi
95b0c85f58 arch: Add xxx_tcbinfo.c to SoC level Make.defs 
Fix build break with CONFIG_DEBUG_TCBINFO enabled.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-12 21:07:35 +09:00
Huang Qi
7134220ae2 risc-v: Remove duplicated up_idle logic 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-10 13:09:32 +08:00
Huang Qi
8532feda78 arch/risc-v: Remove dupped irq code from fe310 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-21 00:44:43 +08:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-16 11:11:14 -03:00
Huang Qi
c6749fd6fd arch/risc-v: Refine exception_common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-13 14:53:18 +01:00
Huang Qi
e47a915f4c arch/risc-v: Refine riscv_vectors.S 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-12 18:53:01 +08:00
Huang Qi
10bb48b9b4 arch/risc-v: Merge rv32im and rv64gc into common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-11 23:24:33 +08:00
Huang Qi
33df35f003 arch/risc-v: Correct epc adjustment with C ISA 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-30 22:54:17 +09:00
Huang Qi
2de22980e5 arch/risc-v: Refine syscall interface 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-30 11:47:42 +08:00
Norman Rasmussen
091322ba4a Add backtrace to risc-v common sources 2021-12-30 01:30:08 +08:00
Huang Qi
c15195b126 arch/risc-v: Refine riscv_testset.S 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-12-29 06:06:01 -06:00
Gustavo Henrique Nihei
06f4ee850a arch/risc-v: Remove FAR qualifier for RISC-V-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Dong Heng
60fb1adaca riscv: Add inline IRQ process functions 
Remove functions from RISC-V chips.
 2021-06-15 23:25:16 -05:00
Xiang Xiao
c0fdddc5d7 arch: Remove all go_nx_start from chip specifc source 
since the idle stack color is done in the common code now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-10 06:50:41 -07:00
Xiang Xiao
2e54df0f35 Don't include assert.h from public header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-03 08:36:03 -07:00
Xiang Xiao
001e7c3e76 sched: Don't include nuttx/sched.h inside sched.h 
But let nuttx/sched.h include sched.h instead to
avoid expose nuttx kernel API to userspace.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-05-24 12:11:53 +09:00
Gustavo Henrique Nihei
e0da0bf6bd arch/risc-v: Fix interrupt stack alignment 2021-04-29 19:39:17 -07:00
Gustavo Henrique Nihei
7caebdd50f arch/risc-v: Fix stack alignment according to calling convention 
The RISC-V Integer Calling Convention states that the stack pointer
shall always be aligned to a 128-bit boundary upon procedure entry, both
for RV32* and RV64* ISAs (exception to the RV32E ISA, which must follow a
specific convention)
 2021-04-27 23:12:20 -05:00
Masayuki Ishikawa
44bc681daa arch: fe310: Add coloration for the idle stack 
Summary:
- This commit adds coloration for the idle stack
- Also, apply la pseudo-instruction instead of lui and addi

Impact:
- fe310 only

Testing:
- Tested with nsh with QEMU and dev board

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-04-19 01:05:40 -05:00
Xiang Xiao
8640d82ce0 arch: Rename g_intstackbase to g_intstacktop 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-16 12:41:41 +09:00
Xiang Xiao
3f67c67aaf arch: Fix the stack boundary calculation and check 
All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-10 08:39:54 -07:00
Xiang Xiao
d62ae03bf8 arch: Move setjmp/longjmp to libc/machine 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-04 16:30:37 -07:00
Abdelatif Guettouche
ea0dc8c1d2 arch/risc-v: up_allocate_heap is already declared in nuttx/arch.h 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-13 19:07:02 -03:00
Abdelatif Guettouche
44ada05549 arch/risc-v: Internal functions should be prefixed with riscv_ not up_ 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-13 19:07:02 -03:00
Masayuki Ishikawa
bb255d075c arch: risc-v: Author Masayuki Ishikawa: Update license to Apache 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-03-12 16:15:44 +08:00