Commit Graph

21575 Commits

Author SHA1 Message Date
Yanfeng Liu
cba993df85 risc-v/cmake: add support to Ubuntu stock toolchain
Ubuntu stock toolchain `gcc-riscv64-unknown-elf` complains about
current CMake system (see issue#11573). This tries to fix it so
that both newer XPack and stock toolchains can be used with CMake.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-23 01:23:44 -08:00
David Sidrane
6c186b6084 stm32h7:serial make TX DMA busy when there are an outstanding transaction
If a TX DMA completion interrups a forground write.
    The TX DMA completion can start a dma_send and it will
    then followed by the forground write's dma_send
    stoping the,then in progress DMA.

    By atomicaly marking the tx dma busy, the forground
    write will not perform the dma_send, and will only
    enqueue the data. At the next TX dma completion any
    data pending in the tx queue will be sent
2024-01-22 06:06:01 -08:00
ThomasNS
1c28bf2ed1 fix typo: it is P4.0 and not P0.4 2024-01-22 05:46:33 -08:00
Tiago Medicci Serrano
0ecc3aaad2 esp32: Explicitly fail on boot-up for unsupported ESP32 versions.
ESP32 is supported on NuttX starting from chip revision 3.0. This,
however, didn't prevent the user from using older chip revisions,
which caused unexpected behaviors. This commit checks chip revision
before finishing booting NuttX.
2024-01-21 06:33:25 -08:00
Tiago Medicci Serrano
2954551ef6 esp32/hardware/esp32_efuse.h: Update macros for registers.
This commit is intended to update the EFUSE's register content and
update related configs:
 - Remove duplicated configs from `esp32_soc.h`;
 - Add missing header files from APB registers;
 - Add missing macro definitions from EFUSE;
 - Update related code to use the new macros;
2024-01-21 06:33:25 -08:00
Tiago Medicci Serrano
8752e6d863 esp32/hardware: Rename efuse_reg.h to esp32_efuse.h. 2024-01-21 06:33:25 -08:00
Takeyoshi Kikuchi
bca8df7d65 arm: sama5: sam_ehci: fix transfer cancellation process.
The logic of the conditional expression that determines whether
the QH is a target QH or not is reversed in the process of canceling
a transfer in INPROGRESS state.

Therefore, the QH in INPROGRESS state is not released and subsequent
communication is not successful.

Checked with CDC-ACM driver and cu command.

Signed-off-by: Takeyoshi Kikuchi <kikuchi@centurysys.co.jp>
2024-01-20 19:54:26 -08:00
Dong Heng
85238fa4de xtensa/esp32s3: Fix USB pull-up and pull-down issue
ESP32-S3 USB OTG device can't call function esp32s3_pullup to notify USB host that it connects or disconnects.
2024-01-18 17:53:16 -08:00
ThomasNS
e966fff597 add GPIO_U1C0_SCLKOUT_3 P4.0 for spi2 on xm4 2024-01-18 17:49:56 -08:00
chao an
02acf2d2a4 risc-v/cmake: set nostdlib to c compiler
To avoid build break:

ld: riscv-none-elf/lib/rv64imafdc_zicsr/lp64d/crt0.o: in function `.L0 ':
(.text+0x8): undefined reference to `__bss_start'
ld: (.text+0x10): undefined reference to `_end'
ld: (.text+0x36): undefined reference to `main'
collect2: error: ld returned 1 exit status

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-18 09:53:53 +01:00
chao an
2fd95611cb risc-v/cmake: configurable vendor ISA extensions
merge below commit into cmake:

1. risc-v/toolchain: configurable vendor ISA extensions

This option allows the platform to enable some vendor-customized ISA extensions,
E.g OpenHW, SiFive, T-Head.

SiFive Intelligence Extensions:
    SiFive Vector Coprocessor Interface(VCIX): xsfvcp
    SiFive FP32-to-int8 Ranged Clip Instructions: Xsfvfnrclipxfqf
    SiFive Matrix Multiply Accumulate Instructions: Xsfvfwmaccqqq
    SiFive Int8 Matrix Multiplication Instructions: XSFvqmaccqoq
Command Line:
    xsfvcp0p1_xsfvfnrclipxfqf0p1_xsfvfwmaccqqq0p1_xsfvqmaccqoq0p1

2. "V" Standard Extension for Vector Operations
3. "Q" Standard Extension for Quad-Precision Floating-Point

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-18 09:53:53 +01:00
w2016561536
829ec6d5e4 esp32s3/pwm: Fix pwm output
1. Fix pwm output always low problem.
2. Add multi channel support in defconfig
2024-01-17 22:42:08 -03:00
Yanfeng Liu
1e9434e2db arch/: remove duplicated task exit logs
Newly added logging in `sched/task_exit.c` obsoletes the existing
ones in `arch/up_exit()`, thus remove the latter to reduce duplications.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-17 09:18:17 -08:00
Yanfeng Liu
87c9a0ee76 risc-v/k230: add NUTTSBI based kernel build support
Previously k230 kernel build needs OpenSBI wrapping for use on
target, thus leading to larger program and memory overheads.
This patch adds alternative small overhead kernel build support.

Changes:

- in arch/risc-v/src/k230:
  - k230_head.S          entrance renamed for sake of NUTTSBI
  - k230_irq.c           add M-mode handling for NUTTSBI case
  - k230_mm_init.c       add L3 table for smaller RAM case
  - hardware/k230_plic.h add PLIC_CTRL definition
  - Make.defs            use CHIP_ASRCS to fix entrance selection
- in boards/risc-v/canmv230/scripts:
  - Make.defs            add support for NUTTSBI case

Additions:

- in boards/riscv/canmv230/:
  - scripts/ld-nuttsbi.script  link script for NUTTSBI case
  - configs/nsbi/defconfig     config for NUTTSBI case

The artifact nuttx.bin from this configuration can be used directly
on target as OpenSBI wrapping is not needed.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>

fix typo
2024-01-17 10:31:29 -03:00
w2016561536
6a0eeb1b3e esp32s3/spi: Add SPI bus init in bringup and fix SPI bus 2 and 3 conflict
1. Add spi bus init in esp32s3_bringup.c
2. Fix IOMUX conflict between spi bus 2 and 3
3. Add spi defconfig
4. Follow the standard of NuttX
2024-01-17 09:29:20 -03:00
chao an
95fcc286a2 risc-v/toolchain: configurable vendor ISA extensions
This option allows the platform to enable some vendor-customized ISA extensions,
E.g OpenHW, SiFive, T-Head.

SiFive Intelligence Extensions:
    SiFive Vector Coprocessor Interface(VCIX): xsfvcp
    SiFive FP32-to-int8 Ranged Clip Instructions: Xsfvfnrclipxfqf
    SiFive Matrix Multiply Accumulate Instructions: Xsfvfwmaccqqq
    SiFive Int8 Matrix Multiplication Instructions: XSFvqmaccqoq
Command Line:
    xsfvcp0p1_xsfvfnrclipxfqf0p1_xsfvfwmaccqqq0p1_xsfvqmaccqoq0p1

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
ce201bba61 risc-v/kconfig: move ARCH_HAVE_MMU into mmu type define
Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
52e99bc66b risc-v/toolchain: move zicsr/zifencei extension into Kconfig
Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
f95bbb2949 risc-v/toolchain: add "V" Standard Extension into command line
"V" Standard Extension for Vector Operations

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
3ee4227668 risc-v/toolchain: add "Q" Standard Extension into command line
"Q" Standard Extension for Quad-Precision Floating-Point

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
90f24ec29d arch/risc-v: add ARCH_QPFPU for Quad-Precision Floating-Point
new options to enable toolchain support for quadruple precision
(128 bits or 16 bytes) floating point if both the toolchain and
the hardware support it.

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
45cca933f8 CMake: arm/armv8-r: init armv8-r cmake build
Test cmake build on aarch32 fvp:
$ cmake -B build -DBOARD_CONFIG=fvp-armv8r-aarch32/nsh -GNinja
$ cmake --build build

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 00:46:52 -08:00
chao an
7c89f943c0 armv8-r/perf: enable perf count only ARCH_PERF_EVENTS is enabled
Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 00:46:52 -08:00
Yanfeng Liu
3c327efd2f docs/comments: fix some typos
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-15 13:22:13 +08:00
Yanfeng Liu
78e8c0dea5 risc-v/nuttsbi: add device specific initialization hook
Some devices have special preparations before entering S-mode, thus
a hook is needed from NUTTSBI to give them the chance.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-14 01:28:10 -08:00
Tiago Medicci Serrano
8fb05d44bc esp32s3/wifi: Fix Wi-Fi connection to WPA3-SAE APs.
This commit fix the connection issues while trying to connect to
WPA3-SAE-secured Access Points (APs).
2024-01-12 16:57:49 +01:00
Yanfeng Liu
f221878204 risc-v/nuttsbi: use ARCH_RV_MMIO_BITS for mtimer access selection
Chips like K230 has ARCH_RV64 but only supports 32-bit MMIO. So using
ARCH_RV_MMIO_BITS is more proper here.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-11 21:48:44 -08:00
chenwen@espressif.com
b739b2b18a xtensa/esp32s3: Support WPA3 on softap mode
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-01-12 13:41:58 +08:00
Ville Juven
983387e6dd mpfs_mpucfg.c: Add mpfs_mpu_lock()
Add method to lock an MPUCFG entry. Locking means the value of the register
cannot be changed until the SoC is reset.
2024-01-11 06:57:16 -08:00
Ville Juven
a0901ec142 mpfs_usb.c: Remove PMPCFG configuration from the driver
This is not the right place to modify DMA memory protection values.

Why not? These are designed to protect other AMP mode instances. Opening
the entire SoC's memory for the USB DMA kind of defeats this purpose.

Also, the driver cannot know how to configure these registers correctly,
only opening up the whole SoC "works".
2024-01-11 06:50:51 -08:00
chao an
181a31801d arm/armv8r: remove unused serial_pl011.h
Signed-off-by: chao an <anchao@lixiang.com>
2024-01-11 13:39:06 +01:00
chao an
b7bd2e33b1 arm/armv8-r: wfi secondary cores if SMP is disabled
Check cpu affinity in single core mode to avoid secondary cores bootup

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-11 12:29:59 +01:00
chao an
6e940b74f5 arm/fvp-v8r: fix arm_earlyserialinit() is not called correctly
USE_EARLYSERIALINIT will depends on the definition in arm_internal.h

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-11 00:52:17 -08:00
chao an
5eef09b4a1 arm/armv8-r: fix compile warning
armv8-r/arm_gicv3.c: In function 'gic_validate_dist_version':
armv8-r/arm_gicv3.c:730:9: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=]
  730 |   sinfo("GICD_TYPER = 0x%x\n", typer);
      |         ^~~~~~~~~~~~~~~~~~~~~  ~~~~~
      |                                |
      |                                uint32_t {aka long unsigned int}
armv8-r/arm_gicv3.c:730:26: note: format string is defined here
  730 |   sinfo("GICD_TYPER = 0x%x\n", typer);
      |                         ~^
      |                          |
      |                          unsigned int
      |                         %lx

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-11 00:51:28 -08:00
Yanfeng Liu
a9372627d8 risc-v/rv-virt: use fully linked apps for kernel build
Fully linked apps take less storage and are efficient to load. This
is to enable them for rv-vrit configurations in KERNEL build.

Changes:

- arch/risc-v/Kconfig       select BINFMT_ELF_EXECUTABLE for QEMU-RV
- boards/risc-v/qemu-rv/rv-virt/configs
  - knsh32/defconfig        enable ELF_EXECUTABLE, LIBM, OSTEST
  - knsh64/defconfig        enable ELF_EXECUTABLE, LIBM, OSTEST
  - ksmp64/defconfig        enable ELF_EXECUTABLE, LIBM, OSTEST
  - knetnsh64/defconfig     enable ELF_EXECUTABLE, LIBM, OSTEST
  - knetnsh64_smp/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST

Additions:
- boards/risc-v/qemu-rv/rv-virt/scripts/
  - gnu-elf.ld              apps linker script

The ARCH_TEXT_VBASE of knsh32 is set to same as that of 64bit to reuse
the apps linker script.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-11 00:51:07 -08:00
Yanfeng Liu
da365c1cb0 risc-v/canmv230: enable fully linked apps for kernel build
Previously apps in kernel build are partially linked, thus are
big and inefficient. This enables full link for kernel mode apps
to reduce size and speed up loading.

Changes:

- arch/risc-v/Kconfig          select HAVE_ELF_EXECUTABLE for K230
- boards/../scripts/Make.defs  adjust LDELFLAGS
- boards/../knsh/defconfig     enable BINFMT_ELF_EXECUTABLE

Additions:
- boards/../scripts/gnu-elf.ld apps linker script

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-10 23:27:46 -03:00
chenwen@espressif.com
a774587088 esp32s3/rt_timer: Adjust spinlock position to avoid deadlock 2024-01-11 09:22:52 +09:00
Tiago Medicci Serrano
823a183c17 esp32s3/rt_timer: Fix deadlock on RT-Timer thread.
The RT-Timer thread may call the `start_rt_timer` function. This
function gets the spinlock with interrupts disabled to ensure
exclusive access. However, this was already being performed in the
RT-Timer thread, causing a deadlock.
2024-01-11 09:22:52 +09:00
Roy Feng
4761af7069 esp32[s2|s3] Following up update interrupt type constants.
Following up the 'Espressif HAL fullly integration for ESP32s2/s3'
changes in https://github.com/apache/nuttx/pull/11428
There are few missing interrupt type constants need update. So
update them to avoid the build error.
2024-01-10 09:54:55 -08:00
fangxinyong
c479ccb8aa sched: move etc romfs mount from nsh to sched/init
Usually the startup script is placed under /etc. The contents of the etc directory
are compiled and linked with Nuttx binary in the form of romfs. After startup,
it will be  mounted by Nsh.

etc is generated by the different boards, that use genromfs and xxd tools to generate
and compile it into the Nuttx, for example: boards/arm/at32/at32f437-mini/tool/mkromfs.sh
The more common method is etc image generated from the content in the corresponding
board/arch/board/board/src/etc directory, and added by Makefile for example:
boards/sim/sim/sim/src/etc.

But in kernel/protected mode, Nuttx kernel and apps are run in different privileged/
non-privileged mode or the isolated binarys, so as that nsh should use syscall to
access Nuttx kernel by exported API. In this scenario, nsh can not mount the etc image
content, because that is generated in board and as a part of Nuttx kernel.

changes:

- move etc romfs mount from nsh to Nuttx, but keep the script to parse and execute.
- move and rename the related CONFIG, move customized nsh_romfsimg.h to etc_romfs.c
  in boards, and no need declaration for romfs_img/romfs_img_len.

This commit changes and updates all configurations in Nuttx arch/board as much as possible,
but if any missing, please refer to the following simple guide:

- rename CONFIG_NSH_ROMFSETC to CONFIG_ETC_ROMFS, and delete CONFIG_NSH_ARCHROMFS in defconfig
- rename the etc romfs mount configs, for example CONFIG_NSH_FATDEVNO to CONFIG_ETC_FATDEVNO
- move customized nsh_romfsimg.h to etc_romfs.c in board/arch/board/board/src and no need
  declaration for romfs_img/romfs_img_len.
- delete default nsh_romfsimg.h, if ROMFSETC is enabled, should generate and compile etc_romfs.c
  in board/arch/board/board/src.

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2024-01-09 21:29:46 -03:00
Philippe Leduc
e59c95bc9b Fix mx8mp ecspi interruption management. 2024-01-09 05:48:12 -08:00
Yanfeng Liu
dd1365ef85 risc-v/canmv230: add PROTECTED build support
Additions:

- In arch/risc-v/src/k230/
  - k230_userspace.c      add user space initialization
  - k230_userspace.h      headers for user space initialization
- In boards/risc-v/k230/canmv230/kernel/
  - k230_userspace.c      userspace_s const data definition
  - Makefile              pass1 Makefile
- In boards/risc-v/k230/canmv230/scripts/
  - ld-protected.script   linker script for protected build kernel
  - ld-userland.script    linker script for protected build userspace
- In boards/risc-v/k230/canmv230/configs
  - pnsh/defconfig        defconfig for protected build

Changes:

- In arch/risc-v/src/k230/
  - k230_start.c          add protected build handling logic
  - Make.defs             add protected build support
- In boards/risc-v/k230/canmv230/scripts/
  - Make.defs             add protected build support
- In Documentation/platforms/risc-v/k230/boards/canmv230/
  - index.rst             add protected build usage

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-08 19:46:42 -03:00
Rodrigo Sim
21b02f176f stm32f401rc-rs485: Add rs-485 support 2024-01-07 17:15:59 -08:00
David Sidrane
73bfeccc3f imxrt:ENET Use multi PHY
Allow a board to specify a list of PHYs.
  Then use this list, at run-time, to select and use the
  PHY populated on the board.
2024-01-06 04:26:12 -08:00
YAMAMOTO Takashi
d0335f089f cmake: fix CONFIG_HAVE_CXXINITIALIZE on macOS
Note: This implementation is a bit more relaxed than what we do for
non-cmake builds. Mainly because I'm not familiar enough with cmake
to mirror what the non-cmake version does.
2024-01-06 04:21:52 -08:00
YAMAMOTO Takashi
32ea2914c0 cmake: use -fvisibility=default for "arch"
so that macos build can find "_sim_netdriver_setmacaddr" etc.
2024-01-06 04:21:52 -08:00
Yanfeng Liu
af15cd40aa risc-v/litex: fix typo in litex/irq.h
Current LITEX_LAST_IRQ looks like a typo that blocks compilation of
`arty_a7/knsh` configuration.

This fixes the build  but I have no such device for test.
Found it was LITEX_IRQ_LAST before commit #ee84ea3 so likely typo was
introduced by then.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-06 04:15:52 -08:00
Ville Juven
14b6f31c8c mpfs_mpu: Add driver to set MPUCFG registers
MPUCFG registers are used to enforce memory protection for DMA master
devices.
2024-01-06 04:15:22 -08:00
Yanfeng Liu
207efa047b risc-v/rv-virt: revise mstatus operations
- drop set of SUM as it is done in  riscv_set_idleintctx()
- fix the CLEAR_CSR() before setting MPP field

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-06 04:04:33 -08:00
TimJTi
438439c1a6 SAMA5 - add LCD backlight PWM cLock source selection 2024-01-05 12:56:27 -03:00