If using flow control with a high CTS the thread may be blocked forever
on the second transmit attempt due to waiting on the txdma semaphore.
The calling thread can then never make progress and release any
resources it has taken, thus may cause a deadlock in other parts of the
system.
The implementation differs in behavior from interrupt-driven TX and the
STM32F7 TXDMA . It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to do next.
Some APIs are implemented both in common code and CHIP-specific code,
and the link needs to be based on the implementation in CHIP, so move
NUTTX_CHIP_ABS_DIR before common src.
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
Because there is no pre-encoding length of the ssid, the ssid including
the Chinese characters whose length is less than 32 after encoding
cann't be translated.
For example, the ssid name is `word人`. After encoding it is `world\xe4\xba\xba` and will not be decoded.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
These flags are not used in the code.
SERIAL_HAVE_RXDMA and SERIAL_HAVE_TXDMA flags are used instead.
STM32_UART_TXDMA flag is not even defined in Kconfig
Connecting the static page tables to each other was done with the page
table virtual address (riscv_pgvaddr) when the page table physical address
is needed.
I can never remember whether the static page table list contains the
table's physical or kernel virtual address.. Add the fact as a comment
there.
Also add the limitations that come from this static page table approach
for Sv32.
The SSID can be configured with special symbols suach as single
quotations, double quotations and backslashes, which need to be escaped.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
This adds option to do PMP configuration via mpfs_board_pmp_setup instead
of just opening up everything. In this case, it is up to the specific
board to implement the PMP configuration in whichever way it sees fit.
With TCD set to loop, there is a window where the
DMA has raised Done, but not reloaded the TCD, resetting
count and clearing Done.
In this window imxrt_dmach_getcount could then return 0.
Resulting in imxrt_dma_nextrx returning RXDMA_BUFFER_SIZE.
Which is not a valid index in the FIFO.
Since the count will be set to RXDMA_BUFFER_SIZE. When the DMA
engine completes the TCD reload. The imxrt_dma_nextrx would
return 0. Therefore:
(RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE
accomplishes this.
With TCD set to loop, there is a window where the
DMA has raised Done, but not reloaded the TCD, resetting
count and clearing Done.
In this window imxrt_dmach_getcount could then return 0.
Resulting in imxrt_dma_nextrx returning RXDMA_BUFFER_SIZE.
Which is not a valid index in the FIFO.
Since the count will be set to RXDMA_BUFFER_SIZE. When the DMA
engine completes the TCD reload. The imxrt_dma_nextrx would
return 0. Therefore:
(RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE
accomplishes this.
With TCD set to loop, there is a window where the
DMA has raised Done, but not reloaded the TCD, resetting
count and clearing Done.
In this window imxrt_dmach_getcount could then return 0.
Resulting in imxrt_dma_nextrx returning RXDMA_BUFFER_SIZE.
Which is not a valid index in the FIFO.
Since the count will be set to RXDMA_BUFFER_SIZE. When the DMA
engine completes the TCD reload. The imxrt_dma_nextrx would
return 0. Therefore:
(RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE
accomplishes this.
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
The DMA can bring in more rx data, than the number of
DMA completions call backs. The call back happen on
idle, 1/2 and full events. But in between these events
the DMA can write more data to the buffers memory that
need to be brought in to the cache. (invalidate)
We do the invalidate on the reads from the fifo memory
if the the DMA as commited since the last read.
Previously, GPIO interrupts were not correctly mapped to the peripheral base register responsible for the interrupt.
Change the IRQ number calculation so the interrupts work correctly on all GPIO peripheral bases.
When ESP32's BLE is enabled, select the option to pin the HCI TX
thread to a specific core. This is necessary to avoid problems
with the BLE task that runs pinned to the PRO CPU (core 0) while
running with SMP enabled.
For TOR: Any size and 4-byte aligned address is required
For NA4: Only size 4 and 4-byte aligned address is good
For NAPOT: Minimum size is 8 bytes, minimum base alignment is 8 bytes,
and size must be power-of-two aligned with base
This commit simplifies these checks and removes all the nonsense added
by a misunderstanding of how the MPFS / Polarfire SoC's PMP works.
These options are just wrong and a result of misunderstanding of the
Polarfire SoC spec. There are no feature limitations in the CPU PMP
implementation -> remove any configuration options added.
Summary:
- I noticed that irq is enabled explicitly in arm64_cpu_idle.S
- The code is unnecessary since tasks, including the idle task,
are created with irq enabled in up_initial_state()
Impact:
- Should be none
Testing:
- qemu-armv8a:netnsh_smp_hv with qemu-7.2.4
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Fix case where NULL is de-referenced via tx/rx buffer or descriptor. Only
1 queue is currently set up for each, so the indices 1,2,3 are not valid
and should not be handled.
Before code is executed after being loaded into memory,
it is necessary to ensure the consistency of I and D cache.
The up_coherent_dcache function will flush the dache and
invalidate the icache to ensure cache consistency.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Only when SCTLR_ELn.WXN is set to 1, regions that are writable at ELn
are treated as non-executable. Therefore, when SCTLR_ELn.WXN is set to
0, regions that are writable at ELn can be executed, so the writable
attribute cannot be used to restrict the executable attribute.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
To compile arm64 NuttX, use the following command:
./tools/configure.sh -l qemu-armv8a:nsh_fiq
To run，use the following command
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Add the Sim WiFi function, which can provide the wifi operating on nuttx sim emulator,
and support two modes that simulate wifi, HWSIM and RNC(real network card).
- In the HWSIM mode, we simulates two wlan interfaces. The wlan0 is STA and
the wlan1 is AP. The wlan0 can connect to the wlan1 in the nuttx simulator.
- In the RNC mode, we can use the same wlan interface name on the nuttx simulator
to control the connection behavior of the real wireless card.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
The BIT macro is widely used in NuttX,
and to achieve a unified strategy,
we have placed the implementation of the BIT macro
in bits.h to simplify code implementation.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
or long time data transmission.
The spin_lock in the wlan_recvframe() function that receives
RX data packets from the wireless network card and the critical
section lock in the iob_remove_queue() processing are nested,
which causes the interrupt to be disabled for a longer period
of time, resulting in a risk of deadlock.
When we build NuttX on macOS, it shows many `sed` messages (and the build still completes successfully):
```text
$ tools/configure.sh pinephone:nsh
$ make
sed: illegal option -- r
```
This is due to the Makefiles executing `sed -r` which is not a valid option on macOS.
This PR proposes to change `sed -r` to `sed -E` because:
- `sed -E` on macOS is equivalent to `sed -r` on Linux
- `sed -E` and `sed -r` are aliases according to the GNU `sed` Manual
- `sed -E` is already used in nuttx_add_romfs.cmake, nuttx_add_symtab.cmake and process_config.sh
All kernel memory is mapped paddr=vaddr, so it is trivial to give mapping
for kernel memory. Only interesting region should be kernel RAM, so omit
kernel ROM and don't allow re-mapping it.
It looks like we do not need to send the 9 clock ticks whenever we reset
the FSM. We are already doing this in i2c_reset function if necessary.
This makes the i2c transfers much faster, for example the i2c(-tool) dev
scan feature.
test config: ./tools/configure.sh -l qemu-armv8a:nsh_smp
Pass ostest
No matter big-endian or little-endian, ticket spinlock only check the
next and the owner is equal or not.
If they are equal, it means there is a task hold the lock or lock is
free.
Signed-off-by: TaiJu Wu <tjwu1217@gmail.com>
Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
Whenever we enter/leave a critical section, the interrupt status is
saved and, then, restored. However, for the ESP32-S3's BLE adapter,
entering/leaving a critical section is done on separate functions
that need to be registered as a callback.
The status flag was being saved as a global variable. However,
calling nested enter_critical_section would overwrite this global
variable that was storing the previous flag and, when leaving the
last critical section, the restored status would be different from
the one expected. The proposed solution for this issue is to create
a global array to store the interrupt status flags for nested calls.
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
When allocating a CPU interrupt, make sure to select the correct
CPU core to query for it. Simply checking for the current CPU does
not satisfy this requirement because the CPU allocation thread may
be executed by the other core: it's necessary to stick with the
intended CPU passed as an argument of the `esp32s3_setup_irq`.
The registered `task_create_wrapper` receives the `core_id`, but
the current implementation ignores this parameter while calling
`esp_task_create_pinned_to_core`. This commit fix this.
When allocating a CPU interrupt, make sure to select the correct
CPU core to query for it. Simply checking for the current CPU does
not satisfy this requirement because the CPU allocation thread may
be executed by the other core: it's necessary to stick with the
intended CPU passed as an argument of the `esp32_setup_irq`.
The SHM physically backed memory does not belong to the user process,
but the page table containing the mapping does -> delete the page table
memory regardless.
This is a collection of tweaks / optimizations to the driver to limit
CPU usage as well as interrupt processing times.
The changes are as follows:
- setfrequency is now no-op if the frequency does not change. Accessing
MPFS_SPI_CONTROL requires synchronization to the FIC domain, which
takes unnecessary time if nothing changes
- load/unload FIFO loops optimized so !buffer, priv->nbits and i==last are
only tested once (instead of for every word written in loop).
- Disable the RX interrupt only once (again, FIC domain access is slow)
- In case a spurious MPFS_SPI_DATA_RX interrupt arrives, just wipe the
whole RX FIFO, instead of trying to read it byte-by-byte
stm32_ifdown() holds critical section when calling stm32_ethreset().
That function used to call up_mdelay(10) while waiting for the ethernet
peripheral reset to complete. This resulted in excessively long
critical section time with interrupts disabled.
The actual expected delay is a few clock ticks of the 50 MHz clock domain.
This commit changes polling interval to 1us and maximum to 10us.
if not unlink shm, the shared memory object still exists in host /dev/shm after quit
if nuttx is started with administrator privileges, or if it is restarted with user
privileges, there will be a problem with the permission to open this shm file
Signed-off-by: yintao <yintao@xiaomi.com>
PMPCFG_A_TOR region may have zero size. The pmp configuration
currently fails for zero-sized TOR. This patch bypasses such a
restriction.
Also replace log2ceil with LOG2_CEIL from lib/math32.h.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This commit adds support for 1 wire interface over serial driver. SAMv7
MCU does not have build in one wire support therefore external hardware
still has to be used (connection of RX/TX for example).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
UART/USART peripheral can be used for more than just standard serial
driver. It can for example be used for 1 wire interface communication
(with external circuitry added). This changes the Kconfig for SAMv7 to
allow future implementation of these drivers. Now user can select
what kind of a driver he wants on UART/USART (serial or something else).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Follow other risc-v based chips, and fix:
```
chip/rv32m1_irq.c: In function 'up_irqinitialize':
Error: chip/rv32m1_irq.c:98:3: error: array subscript -2048 is outside array bounds of 'uint8_t[2147483647]' {aka 'unsigned char[2147483647]'} [-Werror=array-bounds]
98 | riscv_stack_color(g_intstacktop - intstack_size, intstack_size);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from /github/workspace/sources/nuttx/arch/risc-v/src/common/riscv_internal.h:40,
from chip/rv32m1_irq.c:36:
/github/workspace/sources/nuttx/arch/risc-v/src/common/riscv_common_memorymap.h:72:16: note: at offset -2048 into object 'g_intstacktop' of size [0, 2147483647]
72 | EXTERN uint8_t g_intstacktop[]; /* Initial top of interrupt stack */
| ^~~~~~~~~~~~~
cc1: all warnings being treated as errors
```
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Summary
Add ARM PCSI (Power State Coordination Interface) Support
for qemu. With the interface, Poweroff/PowerReset can be support
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
Adding virtual evaluate platform GoldFish. Which is based on
Android Goldfish Emulator, it's a ARM virt board but Android enhance
it with more featue
The patch set goldfish as a chip
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
when using new gcc verion like:
GNU ld (Arm GNU Toolchain 12.2.Rel1 (Build arm-12.24)) 2.39.0.20221210)
we will get link warning like:
aarch64-none-elf-ld: warning: XXX/nuttx has a LOAD segment with RWX permissions
The patch fix the warning through add link option --no-warn-rwx-segments
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
The MPFS eMMC DMA has some requirements that are only fulfilled by
enabling separate DMA access buffers (FAT DMA buffers) and by forcing
indirect access to the media via FAT_FORCE_INDIRECT.
Why? Direct access to user buffers violates two things:
- Buffer alignment is not ensured
- Buffers are user memory (problematic in BUILD_KERNEL)
When unwind instruction is 0xb2,the subsequent instructions
are uleb128 bytes.
For now,it uses only the first uleb128 byte in code.
For vsp increments of 0x204~0x400,use one uleb128 byte like below:
0xc06a00e4 <unwind_test_work>: 0x80b27fac
Compact model index: 0
0xb2 0x7f vsp = vsp + 1024
0xac pop {r4, r5, r6, r7, r8, r14}
For vsp increments larger than 0x400,use two uleb128 bytes like below:
0xc06a00e4 <unwind_test_work>: @0xc0cc9e0c
Compact model index: 1
0xb2 0x81 0x01 vsp = vsp + 1032
0xac pop {r4, r5, r6, r7, r8, r14}
The unwind works well since the decoded uleb128 byte is also 0x81.
For vsp increments larger than 0x600,use two uleb128 bytes like below:
0xc06a00e4 <unwind_test_work>: @0xc0cc9e0c
Compact model index: 1
0xb2 0x81 0x02 vsp = vsp + 1544
0xac pop {r4, r5, r6, r7, r8, r14}
In this case,the decoded uleb128 result is 0x101(vsp=0x204+(0x101<<2)).
While the uleb128 used in code is 0x81(vsp=0x204+(0x81<<2)).
The unwind aborts at this frame since it gets incorrect vsp.
To fix this, add uleb128 decode to cover all the above case.
Signed-off-by: chao an <anchao@xiaomi.com>
Summary
include/arch/syscall.h: Assembler messages:
include/arch/syscall.h:133: Error: bad instruction `struct arm_smccc_res'
include/arch/syscall.h:134: Error: junk at end of line, first unrecognized character is `{'
include/arch/syscall.h:135: Error: bad instruction `unsigned long a0'
include/arch/syscall.h:136: Error: bad instruction `unsigned long a1'
include/arch/syscall.h:137: Error: bad instruction `unsigned long a2'
include/arch/syscall.h:138: Error: bad instruction `unsigned long a3'
include/arch/syscall.h:139: Error: bad instruction `unsigned long a4'
include/arch/syscall.h:140: Error: bad instruction `unsigned long a5'
include/arch/syscall.h:141: Error: bad instruction `unsigned long a6'
include/arch/syscall.h:142: Error: bad instruction `unsigned long a7'
include/arch/syscall.h:143: Error: junk at end of line, first unrecognized character is `}'
include/arch/syscall.h:145: Error: bad instruction `typedef struct arm_smccc_res
Signed-off-by: wangming9 <wangming9@xiaomi.com>
- There are occasional extra STOPs being sent due to an IP bug when using an
FPGA based I2C. Add a flag "inflight" to mask out extra STOP interrupts when
using the FPGA based implementation
- There are no MPFS_I2C_ST_STOP_SENT irq's "initally". It is just already
either success or still in progress
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
The framebuffer of the emulator is a single buffer mode, and the pan_display method is not implemented, so as long as the fb device is created and poll notify once, the fb can be kept in a writable state.
Signed-off-by: pengyiqiang <pengyiqiang@xiaomi.com>
The typo s/.timid/.tcid prevents to compile NuttX with
quadrature encoder configured for timer1 (CONFIG_SAMV7_TC1_QE)
and s/SAM_TC789_BASE/SAM_TC678_BASE prevented use of the
of the timer 2.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
In an implementation that supports the ARM Security Extensions, only
software executing in a Secure PL1 mode can write to CNTFRQ
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Summary:
Adding virtual evaluate platform GoldFish. Which is based on
Android Goldfish Emulator, it's a ARM virt board but Android
enhance it with more featue.
The patch set goldfish as a arm chip.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
In an implementation that supports the ARM Security Extensions, only
software executing in a Secure PL1 mode can write to CNTFRQ
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This adds initialization of the ksz9477 switch when used instead of
a PHY, directly connected to SGMII
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This change fixes the issue when SAMv7 GMAC sometimes does not start packet
transmission. The issue is that EMAC_NCR_TSTART is written to EMAC_NCR register
while tx descriptor is not delivered to memory.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
According to the current implementation, "cxd56_cpu1siguninit" will only
be called once during the NuttX startup phase,
and it won't involve scenarios of multi-threaded concurrent access.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Some SD card connectors do not have separate card detection pin. In that
case card detection has to be done on CD/DAT3 data line. This means
software (i.e. architecture level driver) has to take care of pin
configuration switching (pin has to be set as data pin in case of
transfer and as interrupt card detection pin when there is no action
on data line).
This commit adds CD/DAT3 line card detection support for SAMv7 MCU.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Add a function to read PolarFire's serial number from system controller, and use the first five digits as device's mac address
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Workaround to avoid deadlock situation: The RX shall not try to wait for complete
frame in case there is RX errors detected.
In case mpfs_receive is called, it keeps waiting for complete frame and
also keeps the net_lock locked. In the mean while, the TX may run out of free
descriptors, but can not get net_lock mutex lock to be able to release used
descriptors. If there are no free TX descs it disables RX interrupts because
it may require to send response to the received frame.
So, TX side keeps RX interrupts disabled due to lack of free descriptors and
RX blocks TX to release those descs by stubbornly waiting for complete frame.
RPMSG is associated with the use of HPWORK / LPWORK queues.
After sending a message to the remote end (Linux), the system
waits for an ack before proceeding. Unfortunately this may
take sometimes more time than one would expect. Ack waiting is
also unnecessary: nothing is done with that information. Even
worse, the net_lock() is also held during the blocked time so
it blocks other network stacks that are unrelated to this.
Also reorganize the mpfs_opensbi_*.S so that the trap
handler is easily relocated in the linker .ld file without
the need to relocate the utils.S. This makes it easier to
separate the files into own segments. The trap file should be
located in the zero device.
Moreover, provide support for simultaneous ACK and message
present handling capabilities in both directions. There are
times when both bits are set but only other is being handled.
In the end, the maximum throughput of the RPMSG bus increases
easily 10-20% or even more.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This commits adds support of UART2 for EPS32S3 and fixes pin mode
assignment for iomux mode
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
The master clock frequency should be multiple of the sample rate
and bit clock at the same time. Then, check if the current master
clock satisfies such a condition and set it accordingly otherwise.
In order to gracefully stop the I2S stream, add an interface to set
a `streaming` status variable that sets the `AUDIO_APB_FINAL` flag
that will be handled by the upper layers of the audio subsystem.
According to RX/TX operation, the DMA descriptors (inlink/outlink)
should be set differently. When setting the inlink, the `suc_eof`
field must be cleared by software (it will be set by hardware when
a packet is received). Similarly, the `length` field will be set
by hardware a packet is received.
Define macros used to access the registers of the GDMA channels
according to the selected channel in the header file, enabling them
to be used by other drivers.
By splitting into two different functions the setup of the DMA
descriptors and the action of loading it to the GDMA outlink
register, it enables us to "cache" DMA descriptors ready to be send
and, then, just load them whenever we are able to actually send it.
The macro `SET_BITS` only sets the bits according to the bit mask
and, once it's being used to set the address field of the GDMA
inlink/outlink register, it's necessary to clean all the bits
corresponding to that field that were eventually setup previously
to avoid messing with the bits that correspond to the current
address being setup.
This option enables architecture-specific memory copy for dynamic code loading.
For example, Ambiq has MRAM regions for instruction which can't load by
the memcpy directly.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
