Commit Graph

244 Commits

Author SHA1 Message Date
Gregory Nutt
1f23ad9bad Misc fixes to repair some of the breakage to the SAMA5D4-EK elf configuration caused by changes for the knsh configuration 2014-09-11 10:31:12 -06:00
Gregory Nutt
006cf7d745 Add logic to initialize the per-process user heap when each user process is started 2014-09-10 15:55:36 -06:00
Gregory Nutt
2da0392ae2 SAMA5D4-EK: These configurations now use the fixed DRAM mapping for manipulating the page memory pool. 2014-09-10 08:44:09 -06:00
Gregory Nutt
6238e87aaa Add configuration to use the fixed DRAM mapping for the page pool (if available) instead of remapping dynamically to access L2 page tables and page data. Also, add logic in address environment creation to initialize the shared data at the beginning of the .bss/.data process memory region. 2014-09-10 08:41:01 -06:00
Gregory Nutt
8a99c421ff pcDuino: Several fixes so that it still builds after other Cortex-A changes. 2014-09-10 06:24:39 -06:00
Gregory Nutt
aaf190dcf6 ELF relocations. Some relocation types do not have a named symbol associated with them. The design did not account for that case 2014-09-09 16:52:51 -06:00
Gregory Nutt
8b64dc003e SAMA5D4-EK: In kernel build with address environment, need logic to map user virtual addresses to physical addresses, and vice versa 2014-09-07 19:25:30 -06:00
Gregory Nutt
53bd807186 Fix loop counter... was overrunning a table on larger ELF files 2014-09-07 14:42:04 -06:00
Gregory Nutt
dcc711f3f2 Correct size comparison (pages vs. sections) 2014-09-07 13:47:01 -06:00
Gregory Nutt
3dd3b1f5e2 The 'make export' target needs to bundle up the user C startup file (crt0), not the kernel head object 2014-09-04 13:31:34 -06:00
Gregory Nutt
70e5350942 Mostly cosmetic changes 2014-09-04 10:28:38 -06:00
Gregory Nutt
15e439d6de I love/hate conditional compilation 2014-09-03 11:43:23 -06:00
Gregory Nutt
12775801c9 Add support for delivery of use-mode signals in the kernel build. 2014-09-02 15:58:14 -06:00
Gregory Nutt
8557f1a1bb Space at the beginning of the process data space is now reserved for user heap management structures. In the kernel build mode, these heap structures are shared between the kernel and use code in order to allocate user-specific data. 2014-09-02 11:21:23 -06:00
Gregory Nutt
4d8367a009 sbrk() need to initialized the memory manager on the first call 2014-09-02 08:05:11 -06:00
Gregory Nutt
587520a7d2 Completes the implementation of sbrk() (untested) 2014-09-01 10:46:51 -06:00
Gregory Nutt
4537a905f6 ARMv7 address environment: Static functions not marked static 2014-09-01 08:49:08 -06:00
Gregory Nutt
05b6217876 ARMv7-A: A little more logic and a few more fixes for Cortex-A kernel build 2014-08-31 07:15:46 -06:00
Gregory Nutt
e11679acf8 Rename CONFIG_NUTTX_KERNEL to CONFIG_BUILD_PROTECTED; Partially integrate new CONFIG_BUILD_KERNEL 2014-08-29 14:47:22 -06:00
Gregory Nutt
67721c50f1 Fix hard coded values in dispatch_sysall inline assembly. Back out/corect part of last change; that was going the wrong direction. 2014-08-29 10:10:47 -06:00
Gregory Nutt
48c2c9ed08 Fix a cloned typo 2014-08-29 10:09:07 -06:00
Gregory Nutt
27e463dfaa Various fixes to the ARMv7-A system call logic 2014-08-29 08:24:00 -06:00
Gregory Nutt
8196b629a4 Rename arch/arm/src/armv7-a/syscall.h to svcall.h to work around some include path name collisions; fix some compilation errors in SYSCALL logic when debug is enabled 2014-08-29 07:48:16 -06:00
Gregory Nutt
8dd679e875 ARMv7-A: Add SYSCALL handling logic 2014-08-28 14:52:14 -06:00
Gregory Nutt
cbf0141d6c Add an ARMv7-A system call definition header file 2014-08-28 13:21:36 -06:00
Gregory Nutt
4fa5b52e43 Cortex-A address environments: Fix issue with page privileges 2014-08-28 11:00:41 -06:00
Gregory Nutt
26f6d90fa9 Remove a warning 2014-08-28 10:04:41 -06:00
Gregory Nutt
35b11a7533 Fix an error introduced into ALL implmentations of interrupt dispatch logic 2014-08-28 08:41:57 -06:00
Gregory Nutt
8bdde7b2d1 Add address environment support to ALL implementatins of up_release_pending() 2014-08-28 08:10:19 -06:00
Gregory Nutt
1b24afe6fc Add address environment support to ALL implementatins of up_reprioritize_rtr() 2014-08-28 07:54:07 -06:00
Gregory Nutt
0e9a0150ba ARM: Move address environment switch from the task switchers to the interrupt handler. That may save doing the actin multiple times per interrupt 2014-08-28 06:49:05 -06:00
Gregory Nutt
540a7e4a35 ARM: Move address environment switch from the task switchers to the interrupt handler. That may save doing the actin multiple times per interrupt 2014-08-28 06:34:09 -06:00
Gregory Nutt
7055bce8b4 Add ADDRENV support to ALL implementations of up_unblock_task() 2014-08-27 16:15:46 -06:00
Gregory Nutt
5bf114e604 Add ADDRENV support to all implementations of up_block_task() 2014-08-27 15:36:52 -06:00
Gregory Nutt
8ec74b1a9e Minor address environment clean-up. Cannot generate debug contexts in certain contexts 2014-08-27 14:22:00 -06:00
Gregory Nutt
032ff50313 Add up_addrenv_coherent which will be called before address environment switches 2014-08-26 14:53:19 -06:00
Gregory Nutt
d6a4eb6266 up_coherent_dcache should do nothing the the length is zero 2014-08-26 14:51:53 -06:00
Gregory Nutt
e8094292e3 Rename up_addrenv_assign() to up_addrenv_clone() and generalize its arguments so that can be used for other purposes 2014-08-26 12:16:05 -06:00
Gregory Nutt
b1066775a2 Fix confusion about what is a page of data and what is a page of L2 page table; restructure functions to reduce duplicated logic 2014-08-26 10:41:43 -06:00
Gregory Nutt
45d0b2c5fb Add lots of debug output 2014-08-26 07:54:43 -06:00
Gregory Nutt
b3473bfa26 Cortex-A address environment: Fix some section mapping and address increments 2014-08-26 06:33:26 -06:00
Gregory Nutt
a593729cb2 ARMv7-A: Use of write back might be unpredictable 2014-08-25 16:34:22 -06:00
Gregory Nutt
cfa8174fe4 Bugfixes.. still integrating SAMA5 ELF with address environment 2014-08-25 15:27:58 -06:00
Gregory Nutt
699a54a022 Misc changed to get the SAMA5 ELF configuration with address environments working 2014-08-25 13:28:13 -06:00
Gregory Nutt
8907616478 Cortex-A/SAMA5 address environment support is code complete (untested) 2014-08-25 11:18:32 -06:00
Gregory Nutt
2566ba7b1d Change naming of ELF interfaces from arch_ to up_ for consistency 2014-08-25 06:47:14 -06:00
Gregory Nutt
1f5813a763 After cached related fix, the ELF example is now functional 2014-08-24 14:12:45 -06:00
Gregory Nutt
dde84a0a20 addrenv interface changes: up_addrenv_create() may need to create .text and .bss/.data separately because of differing access privileges (read/execute vs read/write). And, as a consequence, up_addrenv_vaddr() needs to be split into up_addrenv_vtext(0 and up_addrenv_vdata(). 2014-08-24 11:54:14 -06:00
Gregory Nutt
95c79c675c Add addrenv.h; First cut at Cortex-A address environment structures; Add configuration options to setup address enviornment 2014-08-24 09:57:53 -06:00
Gregory Nutt
66abb71c57 Change CONFIG_ADDRENV to CONFIG_ARCH_ADDRENV; change how it is selected -- the architecure must first declare support 2014-08-24 06:42:11 -06:00
Gregory Nutt
41196945d6 ARMv7-A: Add skeleton environment and build support for process address environments 2014-08-23 18:59:24 -06:00
Gregory Nutt
6455f60c60 Remove os_internal.h it has been replace by several new header files under sched/. There have been some sneak inclusion paths via os_internal.h, so expect a few compilation errors for some architectures 2014-08-08 18:39:28 -06:00
Gregory Nutt
4dc151097e Replace os_internal.h with sched/sched.h in files that actually reference something in sched.h 2014-08-08 17:53:55 -06:00
Gregory Nutt
1c99d53bb1 Move clock functions from sched/ to sched/clock 2014-08-08 14:43:02 -06:00
Gregory Nutt
39183d37b8 Change all time conversions. Yech. New timer units in microseconds breaks all existing logic that used milliseconds in the conversions. Something likely got broken doing this, probably because I confused a MSEC2TICK conversion with a TICK2MSEC conversion. Also, the tickless OS no appears fully functional and passes the OS test on the simulator with no errors 2014-08-07 18:00:38 -06:00
Gregory Nutt
dd4be66f1c ARM: Move L2 cache initialization to much later in the sequence 2014-07-27 10:03:33 -06:00
Gregory Nutt
b57d2182ab ARMv7-A L2 Cache currently depends on EXPERIMENTAL because it does not yet work properly 2014-07-26 18:48:54 -06:00
Gregory Nutt
6f5280d284 ARMv7 L2 Cache: Minor bugfixes/improvements 2014-07-26 18:48:26 -06:00
Gregory Nutt
873788bf5a New cache.h file. Renames cp15_XYZ_cache() to arch_XYZ_cache() and addes L2 cache support if L2 cache is enabled 2014-07-26 18:46:52 -06:00
Gregory Nutt
2eb526253b Rename ARMv7-A cache.h to cp15_cache.h. Things will be broken on this commit until I get the new cache.h in place. 2014-07-26 16:54:19 -06:00
Gregory Nutt
6d9ca195ee arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig: Add initiali support for the ARM L2CC-PL310 L2 cache. 2014-07-26 16:50:08 -06:00
Gregory Nutt
fcbf89c6f6 ARMv7-A: L2CC PL310 address filtering is an optional feature 2014-07-25 19:46:09 -06:00
Gregory Nutt
a007fa3f5e ARMv7-A: Add missing L2CC PL310 bit definitions 2014-07-25 19:41:35 -06:00
Gregory Nutt
e74f37445b rch/arm/armv7-a/l2cc_pl310.h: Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h. Adjust the two corresponding Kconfig files as well. 2014-07-25 17:25:17 -06:00
Gregory Nutt
0a134f0158 Need to enable FIQ in initial task state; Improve H32/64 test in IRQ handling 2014-06-21 09:55:09 -06:00
Gregory Nutt
40b7ddf68e SAMA5: FIQs should be disabled along with IRQs on most exeptions in most configuratinons. arm_decodefiq and arm_decodeirq are mutually exclusive and, hence, can use the same interrupt stack 2014-06-20 18:49:01 -06:00
Gregory Nutt
c68d2532be SAMA5D4: Add support for secure/FIQ interrupts; SAIC supports need to be be enabled unconditionally 2014-06-20 18:16:41 -06:00
Gregory Nutt
0a2133b57f SAMA5D4: Add partial support for secure interrupt controller (SAIC) 2014-06-20 15:22:00 -06:00
Gregory Nutt
1636d7cb2f Ooops... last (cosmetic) changes were still in the editor 2014-05-06 15:00:39 -06:00
Gregory Nutt
422a9c9bfd Optimized memcpy() functin for the ARMv7-A from David Sidrane 2014-05-06 14:58:48 -06:00
Gregory Nutt
e4fd434a60 Cosmetic update to comments and README files 2014-04-24 12:44:30 -06:00
Gregory Nutt
0d2e525bd4 Updated comments; minor correction in some naming 2014-04-23 14:46:39 -06:00
Gregory Nutt
9d12aa82fe Sourceforge Patch #37: Missing semicolon 2014-04-16 09:43:34 -06:00
Gregory Nutt
25d4ff745b More trailing whilespace removal 2014-04-13 16:22:22 -06:00
Gregory Nutt
c708eff608 Make sure that there is one space after for 2014-04-12 13:28:22 -06:00
Gregory Nutt
78607a7ea9 SAMA5: Don't use MMU PMD bufferable bit to try to control write-through vs write-back. It does not work that way 2014-04-04 16:05:20 -06:00
Gregory Nutt
489651d041 ARMv7-A: Typo fix from David Sidrane 2014-04-03 15:43:13 -06:00
Gregory Nutt
362d539914 If LOWVECTORS is selected, then we need to clear the VBAR register. A bootloader may have left the VBAR in an bad state 2014-04-03 13:09:30 -06:00
Gregory Nutt
e3d2117b29 SAMA5: Make sure the MMU and caches are disabled on power up; flush the vector region D-Cache after copying interrupt vectors; make sure that D-Cache, I-Cache, and TLBs are invalidated after modifying the AXI MATRIX remapping 2014-04-02 16:27:00 -06:00
Gregory Nutt
7372485e16 Updated comments and README 2014-04-02 09:03:29 -06:00
Gregory Nutt
5ac5506b35 All ARM assertion logic will show stack usage on assertion if DEBUG_STACK is enabled 2014-03-23 10:06:48 -06:00
Gregory Nutt
5b9f1f54c2 Add option to dump buffered USB trace data on an assertion 2014-03-20 10:56:30 -06:00
Gregory Nutt
306271d151 Buildroot EABI (vs OABI) is now the default 2014-02-28 07:49:15 -06:00
Gregory Nutt
6e6b048e5a SAMA5: Fix logic for running with data in SDRAM 2014-01-29 07:49:23 -06:00
Gregory Nutt
e29e0f1cc4 ARMv7-A: Conditionally compile out more unneeded logic when .data and .bss are in SDRAM 2014-01-28 16:39:08 -06:00
Gregory Nutt
93bd80b080 SAMA5: Mostly cosmetic 2014-01-28 15:54:03 -06:00
Gregory Nutt
c930554c2c Add support for .data and .bss in SDRAM 2014-01-28 14:35:03 -06:00
Gregory Nutt
a26b03d0d0 rename up_led*() functions to board_led_*() 2014-01-24 14:28:49 -06:00
Gregory Nutt
231889c888 The optimization level can now be selected as part of the configuration 2014-01-24 07:45:35 -06:00
Gregory Nutt
363d44b7d0 Cosmetic spaces to tabs change 2013-12-08 10:38:33 -06:00
Gregory Nutt
c131e94d04 Add more nops after enabling MMU for Cortex-A8 2014-01-07 08:38:00 -06:00
Gregory Nutt
f1e44300c6 A10: Fix error in IRQ dispatch; vector table seems to be offset by 64 bytes? 2013-12-07 08:36:30 -06:00
Gregory Nutt
e86f940374 SVC is the preferred mnemonic vs. SWI for cortex A 2014-01-05 16:21:41 -06:00
Gregory Nutt
1705b3f894 Fix some missing parameters in macros 2013-12-22 16:29:36 -06:00
Gregory Nutt
d28622a628 Replace explicit hex MMU value with definition 2013-12-18 12:47:43 -06:00
Gregory Nutt
9462db3d3c A10: Extend register debug logic 2013-12-18 11:26:48 -06:00
Gregory Nutt
b48685b34b Cortex-A: Fix start-up cache invalidation logi 2013-12-18 09:01:43 -06:00
Gregory Nutt
9ab637d218 Remove executable mode bits 2013-11-17 08:27:11 -06:00
Gregory Nutt
77c2cf2aa8 Cosmetic changes to comments and README files 2013-12-16 13:48:20 -06:00
Gregory Nutt
05d6d3c252 Trivial updates to comments and README files 2013-12-16 11:13:55 -06:00
Gregory Nutt
ccd5763003 Review Cortex-A9 CP15 registers and update register definitions 2013-12-16 10:23:29 -06:00
Gregory Nutt
0ef05b06d7 ARMv7-A: If the page table does not like in same address range as .text and primary RAM, then we will need to set up an additional mapping for the page table at boot time. 2013-12-16 08:26:07 -06:00
Gregory Nutt
04de5c4452 Port IDLE/interrupt stack coloration to ARM and ARMv7-A architectures 2013-11-01 15:30:18 -06:00
Gregory Nutt
b8085906b9 Extend stack debug logic to include IDLE and interrupt stacks. Also color the heap as well. Based on suggestions from David Sidrane 2013-11-01 11:16:51 -06:00
Gregory Nutt
98ffd096a0 SAMA5 LCDC: Correct how framebuffer memory was being mapped; Remove options to get framebuffer memory in various. Because of the mapping and aligment requirements, those options really cannot be supported 2013-10-13 13:08:05 -06:00
Gregory Nutt
245f5ad32d Slightly improved debug output 2013-09-24 13:47:03 -06:00
Gregory Nutt
b2e3a95565 Un-neccesary, cosmetic changes to label names and comments 2013-09-22 08:54:06 -06:00
Gregory Nutt
d1ac44242f ARMv7-A: Fix some error in alignment to cache line boundaries in the cache operations 2013-09-21 15:47:00 -06:00
Gregory Nutt
c9050ae5fd ARMv7-A: Clarify end address paramet in cache operations: It is the end+1 address, not the end address 2013-09-21 12:16:34 -06:00
Gregory Nutt
56f9092a87 Fix all occurrences of "the the" in documentation and comments 2013-08-27 09:40:19 -06:00
Gregory Nutt
b00d72a7f2 SAMA5: More MMU-related changes to properly initialize SDRAM 2013-08-02 11:11:57 -06:00
Gregory Nutt
35c3a49e1c ARMv7-A: Map all of .text, .bss, .data., stacks before enabling the MMU and caching. This is simpler and avoids fears I have about caching 2013-08-01 10:05:33 -06:00
Gregory Nutt
f0e6d4f101 ARMv7-A: Separate CONFIG_PAGING start-up logic into a different startup file. Too much conditional compilation. 2013-08-01 07:41:00 -06:00
Gregory Nutt
db20c5fc43 Fix Cortex-A CPSR register field definition 2013-07-30 19:05:24 -06:00
Gregory Nutt
16371b50e4 ARMv7-A: Add cp15_disable_dcache(); SAMA5: nor_main.c no disables MMU and caches; Should not remap ISRAM to address 0x0 unless we booted into ISRAM 2013-07-30 13:20:33 -06:00
Gregory Nutt
547f9be80f SAMA5: More cache and mmu inline utility functions 2013-07-29 19:57:15 -06:00
Gregory Nutt
95998c715f SAMA5: Separate cache operations into separate files 2013-07-29 18:38:02 -06:00
Gregory Nutt
f658bcdb13 Changes to ARMv7-A boot logic to handle the case where we execute out of NOR FLASH 2013-07-29 17:54:56 -06:00
Gregory Nutt
27a9da98f4 SAMA5: Add file structure to support board-specific initialization of NOR flash 2013-07-29 07:41:53 -06:00
Gregory Nutt
65c8abddb8 SAMA5: The ostest configuration have been converted to run out of NOR flash. There is more to be done, however 2013-07-28 15:07:35 -06:00
Gregory Nutt
7dfabf3507 SAMA5: Correct a clock configuration bug; clarify some MMU memory types 2013-07-28 12:44:06 -06:00
Gregory Nutt
f191ac94c0 SAMA5: Correct vector mapping 2013-07-28 09:44:11 -06:00
Gregory Nutt
9a5311296f Removed unused ARMv7-A cache function 2013-07-27 14:03:02 -06:00
Gregory Nutt
ae6ed8ca52 SAMA5: Fix heap allocation bugs 2013-07-27 11:28:31 -06:00
Gregory Nutt
3d16c9afc7 SAMA5 page table is cached; need to flush the cache each time that the page table is updated 2013-07-27 09:27:37 -06:00
Gregory Nutt
87af1517ed Correct an error in Cortex-A5 intermediate MMU mapping 2013-07-26 17:26:53 -06:00
Gregory Nutt
14093ef76a Add a hello world configuration to help with the SAMA5 bringup 2013-07-26 15:28:01 -06:00
Gregory Nutt
2f772c84fd Finally... renamed all CONFIG_DRAM_ settings to CONFIG_RAM_ 2013-07-26 10:09:17 -06:00
Gregory Nutt
f87963accd SAMA5: If the page table is in high memory, make sure that it is excluded from the heap 2013-07-26 09:16:46 -06:00
Gregory Nutt
696f6d0482 Misc Cortex-A5 MMU-related fix -- still does not boot 2013-07-25 16:37:55 -06:00
Gregory Nutt
d1be1e6698 Fix an uninitialized register error that crept into the ARM9 start up code many years ago and was recently cloned into the Cortex-A5. Obviously no on has used NuttX with ARM9 for years 2013-07-24 20:12:04 -06:00
Gregory Nutt
f337f3a977 Fix SAMA5 vector linking issue 2013-07-24 12:51:42 -06:00
Gregory Nutt
213780bc43 Update SAMA5D3x-EK board configuration to support on-board UART connections, LEDs, and push buttons 2013-07-24 12:27:12 -06:00
Gregory Nutt
a81abd3514 Improve Cortex-A5 context switching so that a little less copying is done 2013-07-24 07:47:51 -06:00
Gregory Nutt
2e8fcc7229 ARMv7-N: Fix a copy error introduced in the previous check-in 2013-07-23 19:09:17 -06:00
Gregory Nutt
cb3f394d53 Improve some ARMv7-A/M floating point register save time; Add floating point register save logic for ARMv7-A 2013-07-23 17:52:06 -06:00
Gregory Nutt
9e24c4fcd5 ARMv7-A: Need 8-byte stack alignment when callign C code from interrupt handlers. This change needs to be ported to other ARM architectures as well 2013-07-23 14:47:16 -06:00
Gregory Nutt
fb8a7a91fb SAMA5 interrupt handling logic 2013-07-22 11:54:39 -06:00
Gregory Nutt
ca9b52b07f SAMA5/Cortex-A: Improve irqsave/restore inlines + add irqenable. Add skeleton file for SAMA5 interrupt management. Also change from last commit that was left in the editor 2013-07-21 17:08:40 -06:00
Gregory Nutt
0b46176b43 A few more Cortex-A5 and SAMA5 files 2013-07-21 12:52:38 -06:00
Gregory Nutt
0d9250fae5 Misc Cortex-A5 changes include new file for cache operations 2013-07-20 13:06:00 -06:00
Gregory Nutt
6f0e07d071 A few more SAMA5D3 files 2013-07-19 17:45:28 -06:00
Gregory Nutt
c294e9b374 More ARMv7-A files that are just copies of the ARMv4/5 files for now 2013-07-19 11:43:04 -06:00
Gregory Nutt
28a90ba46d Some initial frame for Cortex-A5 support. No much yet 2013-07-18 15:20:47 -06:00