Gregory Nutt
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cbf98ae0a0
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ARMv7 GIC: SGIs are non-maskable but go through the same path as other, maskable interrupts. Added logic to serialize SGI processing when necessary.
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2016-11-27 13:18:34 -06:00 |
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Gregory Nutt
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21e42d18c1
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ARMv7-A/i.MX6 SMP: Move SMP coherernt cache setup to earlier in initialization of CPUn, n>0
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2016-11-27 11:28:24 -06:00 |
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Gregory Nutt
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cd54c71dc1
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ARMv7-A/i.MX6: Modify handling of the SMP cache coherency configuration so that it is identical to the steps from the TRM. Makes no differenct, however.
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2016-11-27 10:21:46 -06:00 |
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Gregory Nutt
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278d8330d6
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arm_scu.c edited online with Bitbucket. Fux some typos.
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2016-11-27 02:59:42 +00:00 |
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Gregory Nutt
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3f6eadc238
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ARMv7-A: Fix some SCU SMP logic
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2016-11-26 18:41:48 -06:00 |
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Gregory Nutt
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546e352830
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i.MX6: Add some controls to enable SMP cache coherency in SMP mode
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2016-11-26 17:46:20 -06:00 |
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Gregory Nutt
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3353d9280f
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i.MX6: Disable non-cached region support. Add SCU register definitions.
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2016-11-26 17:03:57 -06:00 |
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Gregory Nutt
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b2ba12e02a
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SMP: Basic function
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2016-11-26 14:23:23 -06:00 |
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Gregory Nutt
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785ed5faf2
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SMP: A few more compile/link issues. Still problems.
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2016-11-26 13:20:11 -06:00 |
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Gregory Nutt
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aae306e942
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i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region.
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2016-11-26 12:04:02 -06:00 |
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Gregory Nutt
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e3fe320e08
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SMP: Add support for linking spinlocks into a special, non-cached memory region.
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2016-11-26 08:47:03 -06:00 |
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Gregory Nutt
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b08fb33c28
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SMP: Fix typos in some conditional compilation
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2016-11-24 17:59:45 -06:00 |
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Gregory Nutt
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7f636f2280
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SMP: Add spin_trylock(). Use this in conditions where other CPUs need to stopped but we cannot call enter_critical_section.
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2016-11-24 13:33:43 -06:00 |
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Gregory Nutt
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f77dcdf323
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ARMv7-A SMP: Add a little logic to signal handling.
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2016-11-24 11:45:05 -06:00 |
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Gregory Nutt
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c03d126da6
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arm_cpupause.c edited online with Bitbucke. What was I thinking... Back out previous change.
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2016-11-24 04:45:07 +00:00 |
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Gregory Nutt
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19e7f2210e
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arm_cpupause.c edited online with Bitbucket. Fix a typo in a comment.
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2016-11-24 04:24:40 +00:00 |
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Gregory Nutt
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4b0bbf41ca
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SMP: Fix backward condition in test.
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2016-11-23 22:24:14 -06:00 |
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Gregory Nutt
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f90525a5d1
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SMP: Update some comments; trivial improvement by inlining static function.
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2016-11-22 16:48:57 -06:00 |
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Gregory Nutt
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bac7153609
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SMP: Add logic to avoid a deadlock condition when CPU1 is hung waiting for g_cpu_irqlock and CPU0 is waitin for g_cpu_paused
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2016-11-22 11:34:16 -06:00 |
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Gregory Nutt
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130bfa3f6b
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Remove a assertion condition that appears to rarely cause false-alarm assertions. Teported by Petteri Aimonen
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2016-11-21 14:43:56 -06:00 |
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Gregory Nutt
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bb19f1b499
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spinlocks should be volatile.
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2016-11-17 10:04:22 -06:00 |
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Gregory Nutt
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841e1aa77f
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Fix a cloned typo
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2016-10-19 09:14:21 -06:00 |
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Gregory Nutt
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7f16548f57
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Replaces last three commits. Does the same thing, but does it in a way that does not change the usage model.
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2016-06-21 05:26:08 -06:00 |
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Gregory Nutt
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c05da80a27
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Eliminate a warning
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2016-06-20 22:54:58 -06:00 |
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Gregory Nutt
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505ca542e8
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Remove some last traces of lowvsyslog that were missed; Add a SYSLOG emergency channel for handling assertion output more cleanly
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2016-06-20 16:11:50 -06:00 |
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Gregory Nutt
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43eb04bb8f
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Without lowsyslog() *llinfo() is not useful. Eliminate and replace with *info().
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2016-06-20 11:59:15 -06:00 |
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Gregory Nutt
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15c260a428
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armv7-a/armv6-m/arm/a1x: Convert *err() to either *info() or add ERROR:, depending on if an error is reported
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2016-06-17 16:44:50 -06:00 |
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Gregory Nutt
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b39e53391d
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Add underscore at beginning of alert() as well
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2016-06-16 12:38:05 -06:00 |
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Gregory Nutt
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0c8c7fecf0
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Add _ to the beginning of all debug macros to avoid name collisions
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2016-06-16 12:33:32 -06:00 |
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Gregory Nutt
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6f08216621
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Centralize definitions associated with CONFIG_DEBUG_SYSCALL
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2016-06-16 08:12:38 -06:00 |
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Gregory Nutt
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c4e6f50eac
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Centralize definitions associated with CONFIG_DEBUG_IRQ
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2016-06-15 08:35:22 -06:00 |
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Gregory Nutt
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a98bc05f65
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New debug macro: alert(). This is high priority, unconditional output and is used to simplify and stanardize crash error reporting.
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2016-06-14 09:07:53 -06:00 |
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Gregory Nutt
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0f249016a0
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Eliminate some warnings
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2016-06-13 14:01:32 -06:00 |
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Gregory Nutt
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be80a0b99c
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Eliminate some warnings
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2016-06-11 16:40:53 -06:00 |
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Gregory Nutt
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a1469a3e95
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Add CONFIG_DEBUG_ERROR. Change names of *dbg() * *err()
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2016-06-11 15:50:49 -06:00 |
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Gregory Nutt
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e99301d7c2
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Rename *lldbg to *llerr
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2016-06-11 14:55:27 -06:00 |
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Gregory Nutt
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1cdc746726
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Rename CONFIG_DEBUG to CONFIG_DEBUG_FEATURES
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2016-06-11 14:14:08 -06:00 |
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Gregory Nutt
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fc3540cffe
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Replace all occurrences of vdbg with vinfo
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2016-06-11 11:59:51 -06:00 |
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Gregory Nutt
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3a74a438d9
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Rename CONFIG_DEBUG_VERBOSE to CONFIG_DEBUG_INFO
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2016-06-11 11:50:18 -06:00 |
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Gregory Nutt
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80d0b2736e
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Reorder some logic: (1) set initial CPU IDLE task regsters AFTER allocating stack, (2) invalidate cache in CPU start-up BEFORE handling first interrupt.
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2016-05-22 15:01:49 -06:00 |
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Gregory Nutt
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356692d70e
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SMP: Need to enable FPU on other CPUs as well
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2016-05-20 13:35:58 -06:00 |
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Gregory Nutt
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07acd5327a
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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Gregory Nutt
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f454b38d6e
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ARMv7-A SMP: Allow CONFIG_SMP_NCPUS=1 for testing purposes
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2016-05-18 09:17:02 -06:00 |
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Gregory Nutt
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e6728bac29
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Cortex-A9 GIC: Add an interface to set interrupt edge/level trigger
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2016-05-16 14:42:55 -06:00 |
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Gregory Nutt
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4feeb0c2b4
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Cortex-A9 GIC: Some fixes that I don't fully understand but do indeed give me serial interrupts
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2016-05-16 12:50:35 -06:00 |
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Gregory Nutt
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a3f3cc12c0
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Update some comments; Fix grammatic error in ChangeLog.
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2016-05-13 17:36:08 -06:00 |
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Gregory Nutt
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faca2fb1e7
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ARMv7-A/i.MX6: Add logic to handle allocation of CPU IDLE thread stacks more efficiently
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2016-05-13 11:39:42 -06:00 |
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Gregory Nutt
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d14d84c1a6
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ARMv7M/i.MX6: Implement CPUn n=1,2,3 startup logic
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2016-05-13 09:11:55 -06:00 |
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Gregory Nutt
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70782b0f14
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ARMv7-A i.MX6: More SMP logic. Still untested.
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2016-05-12 15:04:46 -06:00 |
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Gregory Nutt
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99e695398c
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Rename up_boot to arm_boot
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2016-05-12 13:42:49 -06:00 |
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