With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
The DMA can bring in more rx data, than the number of
DMA completions call backs. The call back happen on
idle, 1/2 and full events. But in between these events
the DMA can write more data to the buffers memory that
need to be brought in to the cache. (invalidate)
We do the invalidate on the reads from the fifo memory
if the the DMA as commited since the last read.
Previously, GPIO interrupts were not correctly mapped to the peripheral base register responsible for the interrupt.
Change the IRQ number calculation so the interrupts work correctly on all GPIO peripheral bases.
When ESP32's BLE is enabled, select the option to pin the HCI TX
thread to a specific core. This is necessary to avoid problems
with the BLE task that runs pinned to the PRO CPU (core 0) while
running with SMP enabled.
For TOR: Any size and 4-byte aligned address is required
For NA4: Only size 4 and 4-byte aligned address is good
For NAPOT: Minimum size is 8 bytes, minimum base alignment is 8 bytes,
and size must be power-of-two aligned with base
This commit simplifies these checks and removes all the nonsense added
by a misunderstanding of how the MPFS / Polarfire SoC's PMP works.
These options are just wrong and a result of misunderstanding of the
Polarfire SoC spec. There are no feature limitations in the CPU PMP
implementation -> remove any configuration options added.
Summary:
- I noticed that irq is enabled explicitly in arm64_cpu_idle.S
- The code is unnecessary since tasks, including the idle task,
are created with irq enabled in up_initial_state()
Impact:
- Should be none
Testing:
- qemu-armv8a:netnsh_smp_hv with qemu-7.2.4
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Fix case where NULL is de-referenced via tx/rx buffer or descriptor. Only
1 queue is currently set up for each, so the indices 1,2,3 are not valid
and should not be handled.
Before code is executed after being loaded into memory,
it is necessary to ensure the consistency of I and D cache.
The up_coherent_dcache function will flush the dache and
invalidate the icache to ensure cache consistency.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Only when SCTLR_ELn.WXN is set to 1, regions that are writable at ELn
are treated as non-executable. Therefore, when SCTLR_ELn.WXN is set to
0, regions that are writable at ELn can be executed, so the writable
attribute cannot be used to restrict the executable attribute.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
To compile arm64 NuttX, use the following command:
./tools/configure.sh -l qemu-armv8a:nsh_fiq
To run，use the following command
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Add the Sim WiFi function, which can provide the wifi operating on nuttx sim emulator,
and support two modes that simulate wifi, HWSIM and RNC(real network card).
- In the HWSIM mode, we simulates two wlan interfaces. The wlan0 is STA and
the wlan1 is AP. The wlan0 can connect to the wlan1 in the nuttx simulator.
- In the RNC mode, we can use the same wlan interface name on the nuttx simulator
to control the connection behavior of the real wireless card.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
The BIT macro is widely used in NuttX,
and to achieve a unified strategy,
we have placed the implementation of the BIT macro
in bits.h to simplify code implementation.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
or long time data transmission.
The spin_lock in the wlan_recvframe() function that receives
RX data packets from the wireless network card and the critical
section lock in the iob_remove_queue() processing are nested,
which causes the interrupt to be disabled for a longer period
of time, resulting in a risk of deadlock.
When we build NuttX on macOS, it shows many `sed` messages (and the build still completes successfully):
```text
$ tools/configure.sh pinephone:nsh
$ make
sed: illegal option -- r
```
This is due to the Makefiles executing `sed -r` which is not a valid option on macOS.
This PR proposes to change `sed -r` to `sed -E` because:
- `sed -E` on macOS is equivalent to `sed -r` on Linux
- `sed -E` and `sed -r` are aliases according to the GNU `sed` Manual
- `sed -E` is already used in nuttx_add_romfs.cmake, nuttx_add_symtab.cmake and process_config.sh
All kernel memory is mapped paddr=vaddr, so it is trivial to give mapping
for kernel memory. Only interesting region should be kernel RAM, so omit
kernel ROM and don't allow re-mapping it.
It looks like we do not need to send the 9 clock ticks whenever we reset
the FSM. We are already doing this in i2c_reset function if necessary.
This makes the i2c transfers much faster, for example the i2c(-tool) dev
scan feature.
test config: ./tools/configure.sh -l qemu-armv8a:nsh_smp
Pass ostest
No matter big-endian or little-endian, ticket spinlock only check the
next and the owner is equal or not.
If they are equal, it means there is a task hold the lock or lock is
free.
Signed-off-by: TaiJu Wu <tjwu1217@gmail.com>
Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
Whenever we enter/leave a critical section, the interrupt status is
saved and, then, restored. However, for the ESP32-S3's BLE adapter,
entering/leaving a critical section is done on separate functions
that need to be registered as a callback.
The status flag was being saved as a global variable. However,
calling nested enter_critical_section would overwrite this global
variable that was storing the previous flag and, when leaving the
last critical section, the restored status would be different from
the one expected. The proposed solution for this issue is to create
a global array to store the interrupt status flags for nested calls.
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
When allocating a CPU interrupt, make sure to select the correct
CPU core to query for it. Simply checking for the current CPU does
not satisfy this requirement because the CPU allocation thread may
be executed by the other core: it's necessary to stick with the
intended CPU passed as an argument of the `esp32s3_setup_irq`.
The registered `task_create_wrapper` receives the `core_id`, but
the current implementation ignores this parameter while calling
`esp_task_create_pinned_to_core`. This commit fix this.
When allocating a CPU interrupt, make sure to select the correct
CPU core to query for it. Simply checking for the current CPU does
not satisfy this requirement because the CPU allocation thread may
be executed by the other core: it's necessary to stick with the
intended CPU passed as an argument of the `esp32_setup_irq`.
The SHM physically backed memory does not belong to the user process,
but the page table containing the mapping does -> delete the page table
memory regardless.
This is a collection of tweaks / optimizations to the driver to limit
CPU usage as well as interrupt processing times.
The changes are as follows:
- setfrequency is now no-op if the frequency does not change. Accessing
MPFS_SPI_CONTROL requires synchronization to the FIC domain, which
takes unnecessary time if nothing changes
- load/unload FIFO loops optimized so !buffer, priv->nbits and i==last are
only tested once (instead of for every word written in loop).
- Disable the RX interrupt only once (again, FIC domain access is slow)
- In case a spurious MPFS_SPI_DATA_RX interrupt arrives, just wipe the
whole RX FIFO, instead of trying to read it byte-by-byte
stm32_ifdown() holds critical section when calling stm32_ethreset().
That function used to call up_mdelay(10) while waiting for the ethernet
peripheral reset to complete. This resulted in excessively long
critical section time with interrupts disabled.
The actual expected delay is a few clock ticks of the 50 MHz clock domain.
This commit changes polling interval to 1us and maximum to 10us.
