sergiotarxz/nuttx
sergiotarxz/nuttx
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41 Commits

Author SHA1 Message Date
Mark Schulte
b3222bbc8a irq_dispatch: Add argument pointer to irq_dispatch 
Provide a user defined callback context for irq's, such that when
registering a callback users can provide a pointer that will get
passed back when the isr is called.
 2017-02-27 06:27:56 -06:00
Gregory Nutt
bca0adec2b Update comments in file headers. 2017-02-26 14:40:57 -06:00
David Sidrane
bce382da52 Kinetis Support ARMV7 Common Vector and FPU 2016-10-18 12:00:01 -10:00
Gregory Nutt
5386403476 Rename Kinetis version of CONFIG_GPIO_IRQ to CONFIG_KINETIS_GPIOIRQ 2016-07-22 14:30:37 -06:00
Gregory Nutt
0d3ecb3ddd Fix another victim of the mass name changes: xyz_errmonitor->xyz_dbgmonitor 2016-06-17 07:00:33 -06:00
Gregory Nutt
0c8c7fecf0 Add _ to the beginning of all debug macros to avoid name collisions 2016-06-16 12:33:32 -06:00
Gregory Nutt
c4e6f50eac Centralize definitions associated with CONFIG_DEBUG_IRQ 2016-06-15 08:35:22 -06:00
Gregory Nutt
a1469a3e95 Add CONFIG_DEBUG_ERROR. Change names of *dbg() * *err() 2016-06-11 15:50:49 -06:00
Gregory Nutt
e99301d7c2 Rename *lldbg to *llerr 2016-06-11 14:55:27 -06:00
Gregory Nutt
1cdc746726 Rename CONFIG_DEBUG to CONFIG_DEBUG_FEATURES 2016-06-11 14:14:08 -06:00
Gregory Nutt
4e04b3e931 Correct configuration of GPIO pin interrupts on Kinetis K60. Fromo mrechte. 2016-04-20 06:41:51 -06:00
Gregory Nutt
51be83aa3a ARM: Fix missing header file. Update comments in all *_irq.c files. 2016-03-09 15:08:58 -06:00
Gregory Nutt
4d4f54a789 Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
Gregory Nutt
666cc280f4 Rename irqenable() to up_irq_enable(); rename irqdisable() to up_irq_disable() 2016-02-14 16:54:09 -06:00
Gregory Nutt
83bc1c97c3 Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore() 2016-02-14 16:11:25 -06:00
Gregory Nutt
70e502adb0 Replace irqsave() with enter_critical_section(); replace irqrestore() with leave_critical_section() 2016-02-13 19:11:09 -06:00
Gregory Nutt
71c289ce4f Rename all architecture files of form xyz_internal.h to just xyz.h 2015-12-29 18:07:11 -06:00
Gregory Nutt
dfec6a0dd0 Rename CONFIG_ARMV7M_MPU to CONFIG_ARM_MPU so that we can reuse the configuration settings for the ARMV7R MPU 2015-12-14 13:56:21 -06:00
Paul A. Patience
52454cf79b Fix typo 2015-11-11 13:06:15 -05:00
Gregory Nutt
beb060d422 Yet more spacing issues 2015-10-07 20:24:19 -06:00
Gregory Nutt
d0d62668e7 Make some spacing comply better with coding standard 2015-10-06 18:32:16 -06:00
Gregory Nutt
3fdd914203 Costmetic fixes to C coding style 2015-10-05 17:13:53 -06:00
Gregory Nutt
da6c5aabdf All ARMV7-M IRQ setup: Always set the NVIC vector table address. This is needed in cases where the code is running with a bootload and when the code is running from RAM. It is also needed by the logic of up_ramvec_initialize() which gets the vector base address from the NVIC. Suggested by Pavel Pisa 2015-08-21 08:42:24 -06:00
Gregory Nutt
ae15c6963c Make some file section headers more consistent with standard 2015-04-08 08:04:12 -06:00
Gregory Nutt
6455f60c60 Remove os_internal.h it has been replace by several new header files under sched/. There have been some sneak inclusion paths via os_internal.h, so expect a few compilation errors for some architectures 2014-08-08 18:39:28 -06:00
Gregory Nutt
a1b862580b Fix an error introduced in the last commit 2014-04-19 07:54:52 -06:00
Gregory Nutt
6f26d834b6 LPC17xx, TIVA, and Kinetis interrupt initialization: use the NVIC ICTR register to determine how many interrupt lines/registers are supported by the MCU 2014-04-17 14:51:53 -06:00
Gregory Nutt
1061e67f14 Fix error in last ARMv7-M up_disable_irq checkin 2014-01-15 15:26:32 -06:00
Gregory Nutt
e43f86071d Fix all Cortex-M3/4 implementations of up_disable_irq(). They were doing nothing. Thanks to Manuel Stühn for the tip. 2014-01-15 09:56:30 -06:00
Gregory Nutt
4de5e40669 Individual IRQs are not longer disabled on each interrupt. See ChangeLog for detailed explanation 2014-01-15 08:09:19 -06:00
Gregory Nutt
3855ce04e8 Beginning of high priority nested interrupt support for the ARMv7-M family 2013-12-21 11:03:38 -06:00
Gregory Nutt
8b317e9ea3 Standard configuration variables used to enable interupt controller debug; SAMA5: Correct handling of spurious interrupts 2013-08-03 08:22:37 -06:00
Gregory Nutt
3aa94411be Remove up_assert_code 2013-04-25 15:19:59 -06:00
patacongo
65fb38bbcf Add support for ram vectors to the ARMv7-M architecture 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5756 42af7a65-404d-4744-a932-0658087f49c3
 2013-03-18 21:10:08 +00:00
patacongo
a001227981 Use of BASEPRI to control ARM interrupts is now functional 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5548 42af7a65-404d-4744-a932-0658087f49c3
 2013-01-22 16:09:10 +00:00
patacongo
30d1159097 More logic to use BASEPRI to control interrupts -- still doesn't work 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5547 42af7a65-404d-4744-a932-0658087f49c3
 2013-01-22 14:37:17 +00:00
patacongo
5ab31d456e Add option to use BASEPRI instead of PRIMASK to disable interrupts in all ARMv7-M architectures 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5546 42af7a65-404d-4744-a932-0658087f49c3
 2013-01-22 01:25:40 +00:00
patacongo
36df84c843 Email address change in nuttx/ 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5145 42af7a65-404d-4744-a932-0658087f49c3
 2012-09-13 18:32:24 +00:00
patacongo
5347c159fb Add LPC43 interrrupt control logic 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4905 42af7a65-404d-4744-a932-0658087f49c3
 2012-07-04 19:34:11 +00:00
patacongo
e3fa7cffab Add beginning of Kinetis pin interrupt/dma logic 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3880 42af7a65-404d-4744-a932-0658087f49c3
 2011-08-14 22:47:44 +00:00
patacongo
3575d64b9f Add Kinetis startup logic 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3874 42af7a65-404d-4744-a932-0658087f49c3
 2011-08-12 19:57:12 +00:00