arch/arm/src/max326xx/max32660/max32660_spim.c: SPI0 master mode support is complete (sans DMA and completely untested). configs/max32660-evsys/src: Add framework for SPI support.
arch/arm/src/max326xx/max32660/max32660_spim.c: Fleshes out some of the data transfer logic. More needs to be done. Also removes leveraged DMA support. It will be a long time (if ever) before DMA is supported. No point in dragging all of that bogus logic around.
Squashed commit of the following:
arch/arm/src/max326xx/max32660/max32660_spim.c: A few updates tot he SPI master driver. Still incomplete and does not even compile.
Update some comments
arch/arm/src/max326xx: Clean up some general build issues. Still STM32 code posing as MAX32660.
arch/arm/src/max326xx: Starting SPI driver. Initial commit is just the STM32 SPI driver with name changes.
arch/arm/src/max326xx and configs/max32660-evsys/src: Fix some issues with GPIO setup of output pins. Correct polarity of on-board LED output. The on-board LED is now functional.
arch/arm/src/max326xx: WFI instruction in IDLE loop seems to interfere with stability. Commented out for now. Needs to be investigated further.
arch/arm/src/max326xx: Fixes for GPIO configuration problems and serial driver problems. I now get the NuttShell prompt (if I also band on ENTER to force all of the characters out). Progress, but not yet ready.
configs/max32660-evsys: Support CONFIG_BOOT_RUNFROMISRAM=y.
arch/arm/src/max326xx/max32660/max32660_clockconfig.c: Fix an error in a register name.
arm/src/max326xx/max32660: Fix a few new compilation errors when DEBUG is enabled.
Improvements in STM32 ADC, minor changes in STM32 PWM, DMA, HRTIM and add some highpri ADC examples
arch/arch/src/stm32/stm32_adc: fix RCC reset logic
arch/arch/src/stm32/stm32_adc: move sample time change functions to low-level ADC ops
arch/arch/src/stm32/stm32_adc: configurable ADC DMA mode (one shot mode, circular mode)
arch/arch/src/stm32/stm32_pwm: remove llops_get interface. We can use structure casting to get pwm low-level ops
arch/arch/src/stm32/stm32_pwm: add timer enable/disable and frequency update to low-level ops
arch/src/arm/stm32: remove redundant stm32f33xxx_dma.c
arch/arm/src/stm32/stm32f40xxx_dma.c: add interfaces to interact with highp priority DMA interupts
arch/src/arm/stm32/stm32_hrtim: do not enable timers on startup if option from Kconfig selected and add interface to enable/disable timers
arch/src/arm/stm32/stm32_hrtim: fix some warnings
configs/nucleo-f334r8/highpri: update configuration due to changes in stm32_adc
configs/stm32f334-disco/buckboost: update configuration due to changes in stm32_adc
configs/nucleo-f334r8/highpri: add support for ADC injected sequence, add triggering from TIM1
configs/nucleo-f302r8/highpri: add high priority ADC interrupts example
configs/stm32f429i-disco/highpri: add high priority ADC interrupts example
Approved-by: GregoryN <gnutt@nuttx.org>
The user of this invalidation are mmcsd_sdio currently. The mmcsd_sdio driver makes calls for dcache invalidation through the chip specific architecture function SDIO_DMARECVSETUP(). I changed the arch/arm/stm32f7 chips to use arch_invalidate_dcache_by_addr() instead of arch_invalidate_dcache().
This commit includes additional changes to mmcsd_sdio.c. I created SDIO_DMADELYDINVLDT() (DMA delayed invalidate) to invalidate store-into mode dcaches after the DMA transfer. I have been using SDIO_DMADELYDINVLDT() for several weeks now and it has fixed the problems that I previously reported regarding non-cache aligned buffer invalidation errors (for my store-through dcache). However, it does not permit use of unaligned DMA buffers for store-into mode dcaches.
SDIO_DMADELYDINVLDT() is a NoOp unless the chip specific Kconfig file selects CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT. I have modified all the stm32f7 chips to select it.
arch/arm/src/max326xx/max32660/max32660_serial.c: Add a mostly commented out serial driver. With this, we can accomplish a complete build with many warnings for 'Missing logic'
configs/max32660-evsys/src/max326_button.c: Add support for the on-board button.
arch/arm/src/max326xx: Add a mostly empty max326_lowputc.c file mostly so that we can get further in the compilation. Fixed several more compile errors revealed by this.
arch/arm/src/max326xx: Add peripheral clock control header file.
Author: Gregory Nutt <gnutt@nuttx.org>
A few trivial updates from review of changes.
Remove references to NRF52-PCA10040 from documentation. Replace with NRF52-generic.
Remove configs/nrf52-pca10040/ Replaced with configs/nrf52-generic.
Author: Zou Hanya <hanyazou@gmail.com>
Improve LED handling #if~#endif in nrf52_autoleds.c and nrf52_userleds.c
Add Adafruit Feather nRF52 board LED support
Add Adafruit Feather nRF52 board
Add nrf52-generic
Replace 'pca10040' with 'generic'
Copy from nrf52-pca10040 to nrf52-generic
Squashed commit of the following:
arch/arm/src/max326xx and configs/max32660-evsys/nsh/defconfig: Work out some issues related to MAX326xx configuration.
configs/max32660-evsys: Add unverified board support framework.
stm32/stm32_adc: major refator
stm32/stm32_adc: use STM32 ADC IP core version and ADC available functions instead of chip family names in conditional compilation
stm32/chip: replace family specific ADC headers with STM32 ADC IP core version headers
stm32/stm32_adc: configurable sample time supported for all chips, not only L1
stm32/stm32_adc: enable/disable interrupts supported for all chips, not only L1
stm32/stm32_adc: resolution configuration
stm32/stm32f33xxx_adc: remove wrong assertion
configs/nucleo-f303ze: support for ADC and ADC example
configs/stm32f429i-disco: support for ADC and ADC example
Approved-by: GregoryN <gnutt@nuttx.org>
NuttX: STM32F407VG has only one DAC
NDAC=2 causes compilation error when trying to use e.g. STM32_DAC1_CR macro.
Approved-by: GregoryN <gnutt@nuttx.org>
imxrt:Clock config fixes and board.h sets sources and divisors
* imxrt:clockconfig bug fix & Board config set clocks
Fixed logic that was not clearing bits as ~ was
mising in &= mask operations.
Use valuse from the board.h file so set the Mux that
selects the clock sources.
Use board defined PODF values to select clock.
Only configure USDHC2 clocks when board defines clocks.
* imxrt1050-evk:Board setting used to set LSPI and USDHC Clocks
Approved-by: GregoryN <gnutt@nuttx.org>
When MIPS port is built for microMIPS and then loaded as an application, the __start entry point is entered in microMIPS mode, but the CPU core initialization code there misses to set the config3ISAOnExc bit to 1. Subsequently, exceptions are entered in MIPS32 mode, but the code base was built for microMIPS.
This change is needed specifically for the case where a bootloader sets the SPE bit before starting NuttX. In that case, the test in the SPI driver is bogus. This change fixes that by assuring that NuttX has booted and initialized at least once (whether or not SPE is set) before the driver starts refusing to initialize.
arch/arm/stm32*: Don't rely on SPI_CR1_SPE to determine if peripheral has been initialized yet.
Approved-by: GregoryN <gnutt@nuttx.org>
Fixes Kconfig options to include all STM32F20XX processors, not just STM32F207
* arch/arm/src/stm32: Fixes Kconfig options to include all STM32F20XX processors, not just STM32F207
* arch/arm/src/stm32: Removes redundant STM32_STM32F429 depends from Kconfig. STM32F4XXX already does this
Approved-by: GregoryN <gnutt@nuttx.org>
Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
Completes review of configs/gapuino.
arch/risc-v/include/gap8/chip.h: Replace the moved chip.h header file with a dummy chip.h header file just to keep the system happy.
Move include/gap8/chip.h to src/gap8/chip.h. Internal details should not be exposed outside of arch/ and configs/. Review all headers files in src/gap8
Review of arch/risc-v/include.
Author: hhuysqt <hyq9606@126.com>
corrected author and email
Add app initialization, add signal support, cleanup irq context and configs
fix some warnings
gapuino initial port
GAP8 initial port
In addition to the problems that were previously identified there were a few other bits and pieces outstanding;
* Timing was dependent on CPU speed rather than absolute time
* End of transfer handling was a bit mixed up
* It's possible for data to still be in the FIFO (i.e. not have reached
the card) when a next write is requested, so we need to wait for that to
complete
* Interrupt Status could be carried over from one transfer episode to the
next, corrupting progress
* Multi-descriptor DMA writing simply wasn't implemented, but there were no
indications ... it just failed silently
Master imxrt
* imxrt:Fix typos bit# and names
* imxrt:wdog Registers are 16 Bits
* imxrt:wdog Update has to be within 255 clocks of unlock
* imxrt:clockconfig Fix comments
* imxrt1050-evk:board.h Fix comments
* imxrt:imxrt_ccm.h Define Mux Selects for board.h use
* imxrt:clockconfig Allow better control from board.h
1) Allows a board config clock setting to be defined
in terms of the /n values shown in Figure 18-2.
Clock Tree of the i.MX RT1050 Processor Reference
Manual, Rev. 1, 03/2018
2) Allows the clock multipelx selection to be made in
The board config.
* imxrt1050-evk:Define board clocking based on divisor and muxes
Approved-by: GregoryN <gnutt@nuttx.org>
* Clocks were wrongly configured - way too fast because there is no primary divider on LPC4330
This is fixed by means of changing the definitions in the board.h file. I've edited the one for the lpc4330-xplorer board because I'm actually working with Versiboard and don't want to contribute that config just yet while I've still got the drains up on it.
* The LPC43_SDMMC_DELAY register was not being set
I suspect, in the 'real world', it's possible to get away without setting this, but I've added a register definition, default value and register access macros into arch/arm/src/lpc43xx/chip/lpc43_scu.h and then used them in arch/arm/src/lpc43xx/lpc43_sdmmc.c.
* The LPC43_SDMMC_BLKSIZ and LPC43_SDMMC_BYTECNT registers had the wrong values.
The management have already implemented a rather nice block level interface for the stm32 so I've just re-used that to write to these registers as required. I'm slightly nervous that accessing the configuration registers (SCR being the prime example) which has a much smaller block size may not be being done in the right way but it does seem to work correctly, so let's assume it's all OK until someone tells me otherwise.
These fixes have been tested with DMA-based read/write on a LPC4330. Speed via nsh is pretty low but I'm assuming that's just a buffering/implementation issue for now.
Improvements in STM32 PWM low level driver
stm32_pwm: remove some impossible PWM configurations
stm32_pwm: support for complementary outputs
stm32_pwm: deadtime configuration
stm32_pwm: output polarity and IDLE state configuration
nucleo-f302r8: pwm support
stm32f429i-disco: pwm support
configs: update some configurations according to changes in STM32 PWM driver
Approved-by: GregoryN <gnutt@nuttx.org>
(1) Now the Ethernet is completely re-initialized when an error occurs by means of taking the interface down and back up but the PHY is _not_ renegotiated for that case because that is very time consuming and an error in the Ethernet is no reflection on the state of the PHY anyway.
(2) Explicitly sets the expected PHY address to zero (this could be moved into the config) rather than searching for it which takes ages, and it's zero anyway for this board (that's the broadcast address, and anything that cannot respond on that has multiple PHYs, so that would be a new board).
(3) Allows for the renegotiation of the PHY to be optional when a reset is needed. If a non-renegotiated reset doesn't result in good comms to the PHY then it'll automatically be escalated to a renegotiated one.
(4) Only performs a reset for errors that need it (the CRITICAL_ERROR define). The list of errors that need reset are somewhat arbitrarily chosen based on my prejudices and might need to be revisited, but certainly the jabber errors don't need reset, the partial packet is thrown away by the layer above anyway.
(5) Re-loads the multicast table on reset.
(6) Adds a bit more logging into the imxrt Ethernet module.
arch/arm/src/lc823450: Fix up_allocate_heap() in lc823450_allocateheap2.c
For lc823450, heap area in flat build mode must start just after
_eronly. Because bss/data area is allocated in lower address than
text area in SRAM. See ld.scripts for details. Also, this change
removes unsed up_allocateheap.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: GregoryN <gnutt@nuttx.org>
Pull request for mtd/progmem refactoring.
* mtd/progmem: change up_progmem_npages to up_progmem_neraseblocks
page is a unit for read/write operation.
eraseblock is a unit for erase operation.
up_progmem_npages is a little bit confusing because it returns number of
erase blocks in flash memory. This patch changes up_progmem_npages to
up_progmem_neraseblocks. There is no logical change.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* mtd/progmem: up_progmem_erasesize.
Change argument name to be more readable.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* mtd/progmem: up_progmem_eraseblock
Change up_progmem_erasepage to up_progmem_eraseblock.
eraseblock is more readable name than erasepage.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* mtd/progmem: change up_progmem_eraseblock's return value.
up_progmem_eraseblock erase a block. so it's better to return the erase block
size than page size.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* arm/cortex-r : fix wrong cp15_flash_dcache.
change mcrne to mcr for unconditional dcache.
Signed-off-by: sungduk.cho <sungduk.cho@samsung.com>
Approved-by: GregoryN <gnutt@nuttx.org>
kinetis:i2c On faild reset re-init i2c and clocking
If a reset fails, we still must reinitializes the
i2c block so that subsequent transfers will not
cause a hardfault due to the clock being off.
If that transfer fails it can try to reset
again.
Approved-by: GregoryN <gnutt@nuttx.org>
arch/arm/src/lpc43xx: Fix ethernet TX_EN pin definitions
TX_EN on LPC43xx can be routed via P0.1 and PC.4 in both
MII and RMII mode.
Before, P0.1 was hardcoded for MII and PC.4 was hardcoded for RMII.
Also, the definitions used inconsistent naming (TXEN vs. TX_EN).
Approved-by: GregoryN <gnutt@nuttx.org>
arch/arm/src/lpc43xx: Make WWDT usable again
LPC43xx WWDT driver was not updated when irq_dispatch grew an argument
flag in b3222bbc8a.
Also fixes two typos and a naming inconsistency (WWDT vs. WWDG).
Approved-by: GregoryN <gnutt@nuttx.org>
Pull request for cortex-r4 codes
* arm/armv7-r: Add general interrupt controller.
This is based on armv7-a gic controller code.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* arm/armv7-r: add invalidate dcache in arm_head.S
Adding invalidate dcache as a comment in arm_head.S.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* arm/armv7-r: Fix some wrong configuration of program status register.
PSR_E_BIT bit should be set for big endian system.
PSR_A_BIT bis is set automatically as arm cortex-r4 reference manual 3.7.4.
So we don't need to set this bit.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* arm/armv7-r: Fix some wrong MPU register definition.
Change MPU_RBAR_ADDR_MASK and MPU_RACR_TEX_SHIFT mask as
arm cortex-r4 reference manual.
Region Base Address Register 0-4 bits are reserved.
MPU Region Access control register type 3-5 bits.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* driver/mtd: fix compilation error.
This commit fixes below compilation errors.
CC: mtd/smart.c
mtd/smart.c:182:22: error: 'gWearBitToLevelMap4' defined but not used [-Werror=unused-const-variable=]
static const uint8_t gWearBitToLevelMap4[] =
^~~~~~~~~~~~~~~~~~~
mtd/smart.c:170:22: error: 'gWearLevelToBitMap4' defined but not used [-Werror=unused-const-variable=]
static const uint8_t gWearLevelToBitMap4[] =
^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make[1]: *** [smart.o] Error 1
Signed-off-by: Junyeon LEE <junyeon2.lee@samsung.com>
Approved-by: GregoryN <gnutt@nuttx.org>
drivers/serial/uart_16550.c: Add a configuration, analogous to the STM32 configuration option, to suppress the NuttX standard re-ordering for /dev/ttySN for special case of the 16550 UART.
config/serial: UART 16550: Add CONFIG_SERIAL_UART_ARCH_MMIO option so the a memory mapped device doesn't need to provide uart_getreg() and uart_putreg() implementations.
u16550_txempty() should check UART_LSR_TEMT to avoid some data left in the transmit FIFO
kinetis:i2c ensure timeout on bus error
The code had a dead wait on I2C_S_BUSY. Noise on the
bus would cause the driver to hang.
Add timeout on invalid states of I2C_S_BUSY to allow
the upper layers do deal with restart or abort.
Approved-by: GregoryN <gnutt@nuttx.org>
include/nuttx/arch.h: Add prototype for an architecture-specific up_trigger_irq function
arch/, include/nuttx, sched/sched: Add the garbage collection hook so each architecture can do custom memory cleanup if necesary.
arch/Kconfig: Add configureation CONFIG_ARCH_GNU_NO_WEAKFUNCTIONS to suppress use of weak functions. Some gnu derived toolchains do not support weak symbols
Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/kinetis: Cosmetic changes from review of coding standard.
Author: David Sidrane <david_s5@nscdg.com>
Merged in david_s5/nuttx/master_kinetis (pull request #710)
kinetis:Add DMA and use it as RX FIFOs on Serial
* Add initial implementation of the DMA
* Add across Kxx family support [WIP]
* Incorporate the DMA into the serial
Add polling to serial
do DMA initialisation at UART startup and fix DMA mux setting.
Fix circular DMA handling in the serial driver.
* Adapt defconfig to enable UART1,4 RXDMA
* [WIP] - refactor this with new CONFIG DMA settings
* kinetis/Kconfig:Bring inline with upstream stucture
1. Use the Serial console configuration from drivers/serial/Kconfig
and friends.
2. Prefix arch specific featurs as such
UARTx_RXDMA->KINETIS_UARTx_RXDMA
* Kinetis:Serial formatting and clean up
* kinetis:DMA Formating and Cleanup
* kinetis:serial Use cleaner DMA API
* kinetis:Make.defs fix duplicate/errant kinetis_dma.o
* kinetis:serial Fix warning/error on only one uart using DMA
The driver can support no DMA on any UART, DMA on some
UARTs or DMA on all UARTs.
In the case of no DMA we disable the DMA based variables
and logic. In the case of all DMA we disable the non
DMA variables and logic, and in the mixed case both
DMA and non DMA variable and logic are enabled.
* kinetis:dma config fix formatting
* kinetis:chip/dma fix formatting
* kinetis:DMA config assume Unknown
Assume KINETIS_DMA_VERSION_UKN for all SoC not versioned
This is as the code was in nuttx prior to this commit
* kinetis:DMAMUX contain versioning- use HAS pattern define Unknown
The pattern for chip versioning is to define 'HAS' constants.
Define KINETIS_DMAMUX_HAS_MONOTONIC_CHCFG to contain the
version numbers to the include soc header and use that define
in the chip headers.
Define the KINETIS_DMAMUX_VERSION_UKN for the default as prior
this commit addressing was by default monotonic for CHCFG
* freedom-k66f:Disable Serial RXDMA
The application has to add calling of the kinetis
serial dma poll as it is application specific.
Approved-by: GregoryN <gnutt@nuttx.org>
* kinetis:PIT add Liftime and Chaining
* kinetis:flexcan fix dup line and ordering
* kinetis:kinetis_lowput.c LPUART data format with parity fix
The 9-bit data mode is typically used with parity to allow
eight bits of data plus the parity
* kinetis:pindma fix warning
* kinetis:lowputc LPUART_BAUD_INIT has to be defined
build fails with test case enable LPUART0 and make
UART1 console
if HAVE_LPUART_DEVICE is defined then LPUART_BAUD_INIT
has to be defined even if the lpuart is not the console
* kinetis:lpserial fix warning
While this is a good idea and a proper thing to do, it also creates a circular dependency and errors during configuration. RTC depends on STM32_RTC which depends on RTC_EXTERNAL with depends on RTC. No can do.
This reverts commit 714e8c1f9e.
Fix http streaming with lc823450
* arch/arm/src/lc823450: Change C-Buffer under-level control
The under-level setting was changed from 1KB to 55KB.
In previous implementation, the setting can ben changed
by the tx threshold but it is fixed at startup.
Also, check write size and adjust alignment if needed.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Change IOB related params for rndis.
Since TCP flow control scheme was changed, HTTP audio streaming
has not been working. These IOB params are not optimized but
HTTP audio streaming now works.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: GregoryN <gnutt@nuttx.org>
configs/olimex-stm32-p407: Various changes as necessary to get the new kelf configuration working.
configs/olimex-stm32-p407: Add kernel ELF (kelf) configuration.
This update is required to be serialized to the instruction stream meaning that after this update completes, it takes effect immediately and no exceptions of lower priority than the new boosted priority can pre-empt execution. Because of this erratum, the priority boosting does not take place immediately, allowing the instruction after the MSR to be interrupted by an exception of lower priority than the new boosted priority. This effect is only limited to the next instruction. Subsequent instructions are guaranteed to see the new boosted priority.
This was raised in Bitbucket issue 113 from Vadzim Dambrouski.
Squashed commit of the following:
arch/arm/src/samd5e5/sam_usb.c: USB driver now compiles with some issues.
arch/arm/src/samd5e5/chip/sam_fuses.h: Add fuse definition header file.
arch/arm/src/samd5e5: Bring USB driver in from SAMD2L2.
arch/arm/src/samd5e5/sam_clockconfig.c: Implement DFLL support. This completes coding the the re-architected clock configuration logic.
arch/arm/src/samd5e5/sam_clockconfig.c: Add data structures and definitions to support the FDLL and the DFPLL0/1.
arch/arm/src/samd5e5: Completes GCLK configuration logic. Still FDPLL and FDLL support.
arch/arm/src/samd5e5: A little more GCLK configuratino logic. Still incomplete.
arch/arm/src/smad5e5: Beginning of GCLK configuration logic.
arch/arm/src/samd5e5: Add MCLK configuration logic.
arch/arm/src/samd5e5: Add XOSC0/1 configuration logic.
arch/arm/src/samd5e5: Add XOSC32 configuration logic.
arch/arm/src/samd5e5: Rip out all of the leveraged clock configuration logic and start from scratch.
Squashed commit of the following:
arch/arm/src/samd5e5: Clean-up EIC logic.
arch/arm/src/samd5e5: Fix some compilation issues; Still issues with the EIC logic from samd2x.
arch/arm/src/samd5e5: Fix some compilation issues; bring in some EIC logic from samd2x.
arch/arm/src/samd5e5: Add NVMCTRL header file, fix some compiler problems, misc. clean-up.
configs/metro-m4: Add LED support.
arch/arm/src/samd5e5: Bring in SAML21 clock configuration. This is a WIP; it cannot possible even compile yet.
arch/arm/src/samd5e5: Leverage Cortex-M4 interrupt and SysTick logic from the SAM3/4.
arch/arm/src/samd5e5: Add SERCOM utility function.
arch/arm/src/samd5e5: Bring all SERCOM USART logic from SAMD2L2 to SAMD5E5. This is a brute coy with nothing more than more that name changes and extension from 5 to 7 SERCOMs.
arch/arm/src/samd5e5: Add sam_config.h header file
arch/arm/src/samd5e5/: Add Generic Clock (GCLK) utility functions.
arch/arm/src/samd5e5: Add EVSYS register definition file
arch/arm/src/samd5e5 and configs/metro-m4: Use SERCOM3 for the Arduino serial shield as console.
arch/arm/src/samd5e5/chip: Add SERCOM USART, SPI, I2C master, and slave register defintions header files
arch/arm/src/samd5e5/chip: Add AES, PM, TRNG, and WDT header files.
arch/arm/src/samd5e5/chip: Add pin multiplexing header files.
Various fixes to configuration system; fix metro-m4/nsh defconfig file.
configs/metro-m4: Add initial support for the Adafruit Metro M4 board.
arch/arm/src/samd5e5: Add peripheral clock helpers.
arch/arm/src/samd5e5/chip: Add PAC register definition header file. Fix some errors in the memory map header file.
arch/arm/src/samd5e5: Add chip.h headerf file.
arch/arm/src/samd5e5: Add PORT register definitions and support from SAML21.
arch/arm/include/samd5e5: Add interrupt vector definitions.
arch/arm/src/samd5e5: Add some boilerplate files. Correct some typos.
arch/arm/src/samd5e5/chip/sam_eic.h: Add EIC register definitions.
arch/arm/src/samd5e5/chip: Add OSC32KCTRL and OSCCTRL register definitions.
arch/arm/src/samd5e5/chip: Add GCLK, MCLK, and RSTC header files.
arch/arm/src/samd5e5/chip/sam_cmcc.h: Add CMCC register definitions
arch/arm/src/samd5e5/chip/sam_supc.h: Add SUPC header file.
arch/arm/src/samd5e5: Add start-up logic.
arch/arm/src/samd5e5: Add Make.defs file
arch/arm/src/samd5e5/chip: Add memory map header file.
arch/arm/include/samd5e5: Add chip.h header file.
arch/arm/Kconfig and arch/arm/src/samd5e5/Kconfig: Add configuration logic for the SAMD5x/Ex family.
