The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.
This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s3 targets and removes the need
for running 'make bootloader' command for it.
Other related fix, but not directly to Simple Boot:
- Instrumentation is required to run from IRAM to support it during
initialization. `is_eco0` function also needs to run from IRAM.
- `rtc.data` section placement was fixed.
- Provide arch-defined interfaces for efuses, in order to decouple
board config level from arch-defined values.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
The DS1307 was used as board specific, but it is better move it to
stm32/common to be easily used by other boards as well.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Currently Simple Boot image have fixed 2 ROM segments and
2 RAM segments, then the parsing iterator must stop when all
ROM segments are found.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
- Add missing include guard
- Add missing C++ guard
- Fix the initialization ordering in IOMUX_PADCFG macro. Why ? Becaused of:
imx9_iomuxc.h:54:3: error: designator order for field 'iomux_padcfg_s::dsyreg' does not match declaration order in 'iomux_padcfg_s'
54 | }
|
The original assumption was that the interrupt numbers are divided
so that 16 pins from 1 port are handled by a single interrupt source.
So source 0 would handle pins 0-15 and source 1 would handle pins 16-31.
This assumption is wrong, each pin has two sources, thus there are two
interrupt lines for each pin.
The driver uses source 0, and leaves source 1 disabled.
This disables the leading spaces removal for block comments to
avoid changing well-formatted blocks.
Based on test with uncrusity 0.72.0+dfsg1-2 on Ubuntu 22.04, the
leading spaces of block comment lines are unexpectedly removed by
current version w/o this patch.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
According to the qemu source code, hw/arm/virt.c.
The secure memory of the ARM Virt board is [0xe000000~0xf000000]
and the non-secure memory is configured as [0x40000000~0xffffffff].
We made the following adjustments based on the above virt board configuration
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This patch supports listing configs for a given board like
- `tools/configure.sh -L sama5`
- `tools/configure.sh -L rv-virt`
- `tools/configure.sh -L virt`
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
I found `struct ipv*_nat_entry` is missing `_s` suffix, but the name is too long in some cases, so maybe `ipv*_nat_entry_t` could be better.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
1. The critical section does not prevent task scheduling
2. If the critical section is in sched_lock, there is no need to check,
scheduling is not going to happen
3. If sched_lock is in the critical section, sched_unlock will also
trigger scheduling without waiting for the exit of the critical section
4. After exiting the critical section, if there is an interrupt,
the scheduling will be automatically triggered
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Notes:
1. This version of NAT66 is a stateful one like NAT44, corresponding to Linux's MASQUERADE target of ip6tables. We can support stateless NAT66 & NPTv6 later by slightly modify the address & port selection logic (maybe just match the rules and skip the entry find).
2. We're using same flag `IFF_NAT` for both NAT44 & NAT66 to make control easier. Which means, if we enable NAT, both NAT44 & NAT66 will be enabled. If we don't want one of them, we can just disable that one in Kconfig.
3. Maybe we can accelerate the checksum adjustment by pre-calculate a difference of checksum, and apply it to each packet, instead of calling `net_chksum_adjust` each time. Just a thought, maybe do it later.
4. IP fragment segments on NAT66 connections are not supported yet.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
To prepare for future IPv6 NAT functions.
- Rename common ipv4_nat_xxx to nat_xxx
- Move some common definitions into header
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
Using CSR name depends on compiler support heavily, but CSR
encoding does not have this problem. It also make it easy to
add new CSR support even if the compiler does not support.
Unify CSR access by using the CSR encoding macro.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
This patch adds more debug related CSR definitions
to arch/risc-v/include/csr.h.
These definitions are from the RISC-V Debug Specification
Version 1.0 rc1 (https://github.com/riscv/riscv-debug-spec).
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
