arch/arm/src/tiva/common/tiva_flash.c: Fix several mistakes in
tiva_write() but note that this function needs more work. (1) Fix wrong
use of && when & was intended. (2) Add compile- time warning directive
because according to this function's interface, it is supposed to
support unaligned writes and/or writes of arbitrary numbers of bytes to
FLASH. However, this function does NOT support that at this time. This
needs to be fixed. (3) Fix wrong preprocessor conditional. Was written
to use the 32-word write buffer only for TM4C1294NCPDT. This buffer is
available on all TM4C123 and TM4C129 parts. Now conditioned upon
CONFIG_ARCH_CHIP_TM4C123 or CONFIG_ARCH_CHIP_TM4C129. (4) Add comments
to document the intent of the above preprocessor logic.
stm32l4_otgfs: enable OTGFS for STM32L4+ series
The OTGFS peripheral on stm32l4x6 and stm32l4rxxx reference manual is
exactly the same. This patch also adds missing bits and fixes errors in
stm32l4x5xx and stm32l4x6xx OTGFS register maps.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Add DMA support for STM32L4+ series
* Add DMA support for STM32L4+
* stm32l4xrxx_rcc: enable "Range 1 boost" mode if any PLL freq above 80 Mhz
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards: cxd56xx: spresense: cleanup and new defconfig
* arch: cxd56xx: remove NVIC_SYSH redefinition
The NVIC_SYSH is already defined in nvicpri.h
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: spresense: configs: enable SPRESENSE_EXTENSION
Enable high current mode for the Spresense Extension board on all examples
that have SDCARD support
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: spresense: ifdef SDCARD_TXS02612
The SD Card TXS02612 port expander is hosted on the Extension board and
should not be enabled if the extension board is not prezent.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: spresense: configs: increase MQ_MAXMSGSIZE
This change is needed by the display driver on spresense platform
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: spresense: config: add lcd examples defconfig
This is a configuration for the basic nx examples
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards: cxd56xx: spresense: add board_timerhook function
* boards: cxd56xx: spresense: add board_timerhook function
in preparation for SDK we muts have a weak board_timerhook function
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* drivers: usbhost: add missing endif
By accident an endif was missing.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: audio: add build barrier
The audio implementation should not be beuilt if the config
CONFIG_CXD56_AUDIO is not set.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch:arm:cxd56xx: add ge2d.h header
The header is used by imageproc.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards: arm: cxd56xx: audio: add power_control and audio_tone_generator
* boards: arm: cxd56xx: audio: add power_control
Add a simeple way to control the audio power for userspace apps
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: audio: add audio_tone_generator
Add a simple way to control the audio buzzer with defined frequency
for userspace apps
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
1. Serial (UART) driver (13 ports)
2. Ethernet driver
This port is provided on two boards
1. RSK RX65N-2MB
2. GR-Rose
The port is built on Cygwin environment.
As part of this port, we have created two documents
1. Readme.txt for each board
2. User manual to provide information about development environment setup
Both these documents are placed under
1. /boards/renesas/rx65n/rx65n-grrose
2. /boards/renesas/rx65n/rx65n-rsk2mb
We have run 'nxstyle' for coding guidelines and 'ostest' for testing NuttX features on test platform.
We have shared the log with no errors as confirmation of valid port.
arch/arm/src/stm32f0l0g0: Pinmap TIM1 GPIOs available for STM32G0
arch/arm/src/stm32f0l0g0: Add TIM driver lowerhalf
arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c: Handle 32-bit overflow on some calculations.
arch: armv7-m: Fix a deadlock in up_sigdeliver() in SMP mode.
In previous implementation, up_disable_irq() was called before
recovering local context. However, I noticed a deadlock happens
in the following situation. For example, if up_sigdevliver() is
in progress on CPU0 and CPU1 has called up_cpu_paused to CPU0,
hence g_cpu_irqlock has been locked by CPU1, in this case,
we would see a deadlock in later call of enter_critical_section()
to restore irqcount.
To avoid this situation, we need to call enter_critical_section()
to break the deadlock.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Spresense smp
* arch: arm: Add ARCH_GLOBAL_IRQDISABLE to ARCH_CHIP_CXD56XX in Kconfig
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch: arm: cxd56xx: Make fpuconfg() public in cxd56_start.c
NOTE: fpuconfig() is called in both cxd56_start.c and cxd56_cpustart.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch: arm: cxd56xx: Add support for SMP
NOTE: To run cxd56xx in SMP mode, new boot loader which will be
released later must be used.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch: arm: cxd56xx: Add irq routing for SMP in cxd56_irq.c
NOTE: In cxd56xx, each external interrupt controller can be
accessed from a local APP_DSP (Cortex-M4F) only. This commit
supports IRQ routing for SMP by calling up_send_irqreq() in
both up_enable_irq() and up_disable_irq().
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* boards: spresense: Add smp configuration
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
cxd56xx: various fixes
* arch: arm: cxd56xx: Support to set any i2c frequency
This commit supports to be able to set the i2c frequency other than just
100 or 400 Hz.
* arch: arm: cxd56xx: Enable SD clock during access to SD card
- Improve GNSS low sensitivity with SD card inserted
- Reduce power consumption by stopping SD clock
* arch: arm: cxd56xx: Do PANIC() when cpu rx fifo is overflow
If CPU Rx FIFO is overflow, it's fatal error for system. In such a case,
this commit changes to allow the user to notice by calling PANIC() for
debuggability enhancement.
* arch: arm: cxd56xx: Fix compile error in sdhci debug code
* arch: arm: cxd56xx: Remove assertion in cpu tx queue
When CPU Tx queue is overflow, it returns -EAGAIN instead of assertion
to be able to retry.
* arch: arm: cxd56xx: Add configurations for cpu fifo elements
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: Fix LPADC configuration
LPADC options defined in the same symbol name, so kconfig tool
couldn't process them correctly.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: Update loader and gnssfw ver.17660
* arch: arm: cxd56xx: Fix hang-up when error interrupt occurs
Fix a problem that error interrupts are not cleared.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: Fix sdhci semaphore
Fix inital value of semaphore in sdhci drive.r
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: Treat the initial value of LNA power as off
LNA is always turned power on when GNSS is started. So it is desirable
that the initial value of the LNA power is off by default.
* boards: cxd56xx: Remove initial setting of PIN_AP_CLK
PIN_AP_CLK is used as a port selector of SDIO expander on the extension
board, and is set output low in initalizing. Therefore, this pin cannot
be used for other board. To avoid this restriction, remove this initial
operation because this pin is pulled down by default on the extension
board.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Most of the bluetooth and wifi chips appear to need external firmware, and the 43438 is no exception. Fortunately, since Cypress got involved, these are much more straightforward to obtain and are shipped as part of their SDK, which is downloadable from their website. Those firmwares are already provided as C arrays, so their names just need updating to;
const unsigned char bt_firmware_hcd -> The bt firmware array.
const int bt_firmware_len = sizeof(bt_firmware_hcd);
arch/arm/src/stm32f0l0g0/stm32g0_rcc.c: Set VOS and flash wait states properly
arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c: Renamed from arch/arm/src/stm32f0l0g0/stm32_pwr.c
arch/arm/src/stm32f0l0g0/stm32g0_pwr.c: Preliminary implementation of PWR module for STM32G0 (stm32_pwr_setvos() only)
arch/arm/include/stm32f0l0g0: add support for STM32G070CB, STM32G070KB, STM32G070RB
arch/arm/src/stm32f0l0g0: add support for STM32G070CB, STM32G070KB, STM32G070RB
stm32h7: bbsram issues causing no writes and hardfaults
* stm32_pwr:Ensure data is flushed on backup domain access changes
* stm32h7:bbsram convince compiler to perform 32 bit write
Approved-by: Gregory Nutt <gnutt@nuttx.org>
noards: arm: cxd56xx: migrate common code
* boards: arm: cxd56xx: common: move boot to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: move flash to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: move I2C driver to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: move uid to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: move usbmsc to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56: add SPH
The SPH is used by the ASMP implementation from the SDK.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards: cxd56xx: add SCU sensors (2/2)
* boards: cxd56xx: add cxd56_bh1721fvc initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bh1745nuc initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bm1383glv initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bm1422gmv initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bmi160 initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bmp280 initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_kx022 initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_lt1pa01 initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_rpr0521rs initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_sensors initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56: add Backup Log driver
The driver will be used to backup logs on crash.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: add crashlog driver
Add Crashlog driver with support for reset on crash
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: move gs2200m initialization
Move the board gs2200m initalization to the common board folder
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: move ili9340 initialization
Move the board ili9340 initalization to the common board folder
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: move lpm013m091a initialization
Move the board lpm013m091a initalization to the common board folder
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: typo fixes
HEADER: Updates on file location
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Squashed commit of the following:
arch/arm/src/s32k1xx: Update peripheral input clocking for the way that things are done for the S32K1XX. Fix other misc. compilation/configuration issues.
arch/arm/src/s32k1xx: Clean up LPSPI and LPI2C naming for S32K1XX. Using S32K1XX clock functions to get peripheral input clock.
arch/arm/src/s32k1xx: Clone i.MXRT LPSPI and LPI2C support. i.MXRT uses the same IP as S32K1XX.
arch/arm/src/s32k1xx/s32k1xx_lowputc.c: Fix a typo that prevented LPUART1 from working.
arch/arm/src/s32k1xx/s32k1xx_periphclocks.c and related files: Fix yet another case of confusion between pre-decremented and non-decremented divider values. Enforce the rule that dividers are not decremented until the moment they are written into registers.
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c: Fix another problem related to whether a divider is pre-decremented or not. The answer must be the divder values are never pre-decremented. They are decremented just before being written to hardware.
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c: Clean up some bad conditional logic. Precedence of operators problem.
boards/arm/s32k1xx/s32k118evb: Add support for execution out of SRAM. This is helpful for bringup when you want to avoid putting a lethal image in FLASH.
arch/arm/src/s32k1xx/s32k1xx_clockconfig.h: Remove crystal frequency, it is not used.
arch/arm/src/s32k1xx/s32k1xx_wdog.h: Fix a typo in a register name.i
boards/arm/s32k1xx/s32k*evb/configs/nsh/defconfig: Create Motorola SREC output format.
boards/arm/s32k1xx/s32k118evb/include/board.h: Add LPUART0 pin disambiguation.
arch/arm/src/s32k1xx/hardware: Add pin mux definitions for S32K116, 118, 142, 144, 146, and 148.
arch/arm/src/s32k1xx/s32k1xx_pin.c and .h: Add support for PIDR register that disables a gneral purpose pin from acting as an input.
arch/arm/src/s32k1xx/s32k1xx_pin.c and .h: The device does not support slew rate controls or open drain (on all the pins). Only pins that are configured for a protocol that requires open-drain (e.g;, LPI2C, LPUART single-wire) will work in open-drain mode.
arch/arm/src/s32k1xx/: Add logic to look up the peripheral clock frequency. Fix baud calcuation logic in s32k1xx_lowputc.c: In no longer tries to enable clocking. That must be done with board logic. Now gets the peripheral functional clock frequency to determine the baud rate.
arch/arm/src/s32k1xx: Add peripheral feature arrays.
Finishes peripheral clock initialization:
arch/arm/src/s32k1xx/s32k11x/s32k11x_clockmapping.c
arch/arm/src/s32k1xx/s32k14x/s32k14x_clockmapping.c
Provide MCU-specific mapping of clock names to PCC control registers.
boards/arm/s32k1xx/s32k118evb/src/s32k118_periphclocks.c
Provides initial clocking for for the S32K118EVB
arch/arm/src/s32k1xx/s32k1xx_periphclocks.c: Add logic to initialize peripheral clocking.
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c: Add SIM clock configuration.
stm32h7 RTC and friends support
* stm32h7:Removed f7 in file path
* stm32f7:Fix overwritten IRQ enabled
System boot order calls clock_initialize then up_initalize.
clock_initialize was setting up the alarm IRQ
up_initalize is initializing the NVIC.
This most likely worked in the past due to a bug in the
NVIC init code that failed to clear the Interrupt enables.
That was fixed in 510b0f7e arch/arm/src: Correct all ARMv7-M
architectures. Interrupts were not be disabled correctly
on power up.
* stm32h7:Ported over F7 RTC
* nucleo-h743zi:Add RTC
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c: Finishes the implementation of the core clock configuration logic.
arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h: Add SMC register definition header file.
arch/arm/src/s32k1xx: Bring in GPIO logic from Kinetis. Looks like the same IP.
serial single-wire: add possibility to specify pull-up instead of open drain
Approved-by: David Sidrane <david.sidrane@nscdg.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Master
* Revert "Merged in yanqil-br/feature-multi_chan_pwm (pull request #973)"
This reverts commit aef0e0b538.
* arch/arm/src/{stm32/stm32f7/stm32h7/stm32l4}/stm32_pwm.c: configure multi-channel duty only if channel specified. This allows you to update duty cycle for a single channel
* nucleo-f303re/configs: add basic NSH configuration
* nucleo-f303re/configs/pwm: enable console on UART2 and set entry point to nsh_main
Approved-by: Gregory Nutt <gnutt@nuttx.org>
stm32f7: USART1_RXDMA is dependent on STM32F7_DMA2 not STM32F7_DMA1
Approved-by: David Sidrane <david.sidrane@nscdg.com>
Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/tiva/Kconfig:
Remove EXPERIMENTAL dependency on TIVA_TIMER16_PWM.
arch/arm/src/tiva/common/tiva_timerlib.c:
Fix wrong 32/16-bit ifdef checks.
Add tiva_pwm16_sel_event() to choose GPTMCTL.TnEVENT value.
Implement tiva_pwm_mode16().
tiva_timer16_setinterval(): Fix wrong check for TIMER16_MODE_ONESHOT
and TIMER16_MODE_PERIODIC. Was comparing to config->cmn.mode
which can never have those values. This prevented interrupts being
enabled. Compare to timer->mode instead.
Add tiva_timer16pwm_setperiodduty() to set initial period, duty cycle,
and enable interrupts if requested in GPTM peripheral. Interrupts
are not enabled in NVIC until tiva_timer16_start() is called.
Add tiva_timer16pwm_setduty() to update duty cycle at any time.
arch/arm/src/tiva/hardware/lm/lm3s_timer.h,
arch/arm/src/tiva/hardware/lm/lm4f_timer.h,
arch/arm/src/tiva/hardware/tm4c/tm4c123_timer.h,
arch/arm/src/tiva/hardware/tm4c/tm4c129_timer.h:
Add missing defines; make surrounding defines consistent.
arch/arm/src/tiva/tiva_timer.h:
Add new TIMER_FLAG_* configuration flags to enable configuring the
16-bit PWM feature. Extend type of "flags" in tiva_timer32config_s
and tiva_timer16config_s from 8- to 32-bits to allow more flags.
If we are using the BASEPRI register to disable interrupts, then the answer is that we must disable ONLY the "normal interrupts". That is because we cannot disable SVCALL interrupts and we cannot permit SVCAll interrupts running at a higher priority than the high priority interrupts (otherwise, they will introduce jitter in the high priority interrupt response time.)
Hence, if you need to disable the high priority interrupt, you will have to disable the interrupt either at the peripheral that generates the interrupt or at the NVIC. Disabling global interrupts via the BASEPRI register cannot effect high priority interrupts.
arch/arm/src/tiva/common/tiva_timerlib.c:
* tiva_gptm_configure() and tiva_gptm_release(): Fix error: Was calling
tiva_emac_periphrdy() instead of tiva_gptm_periphrdy().
arch/arm/src/tiva/tiva_timer.h:
* Fix error in "abcde" description of bit flag defines.
