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12259 Commits

Author SHA1 Message Date
Konstantin Berezenko
42ee88fe89 STM32F411 and STM32F446 map i2c2_sda_4 to different alternate function numbers 2016-08-17 11:01:44 -07:00
Piotr Mienkowski
5d5851a5cd sam_tc_clockselect() reworked to calculate frequency error using smallest possible divisor minimizing the frequency error rather than largest possible divisor which maximized the error. 2016-08-17 09:51:54 -06:00
Gregory Nutt
17e5da96ea SAMV7: DAC1 not available GMAC is enabled 2016-08-17 07:14:59 -06:00
Gregory Nutt
e57891b41f Kinetis I2C: Review and extend I2C register definitions for K40 and K60 2016-08-16 12:17:23 -06:00
Gregory Nutt
a337494221 Kinetis I2C: Remove literal hex register values. Replace with symbolic definitions from kinetis_i2c.h 2016-08-16 11:44:04 -06:00
Gregory Nutt
7f4488dc80 Review I2C register definitions and add support for the K64 2016-08-16 10:18:52 -06:00
Gregory Nutt
a3b061e54f Kinetis: Add support for I2C2 2016-08-16 10:02:28 -06:00
Gregory Nutt
be83e73957 Kinetis I2C: Add comments, DEBUGASSERTions, and some I2C debug output. 2016-08-16 08:42:30 -06:00
Gregory Nutt
32c1189f51 Re-order some fields so that the structure packs better and so is smaller. 2016-08-16 08:20:55 -06:00
Gregory Nutt
f40bb14495 Kinetis: Add support for I2C1 2016-08-16 07:21:03 -06:00
Gregory Nutt
b2be0be3a6 Simulated oneshot max_delay() method should not return a failure. 2016-08-15 11:43:55 -06:00
Gregory Nutt
3f48392974 Add defaults in SAMV7 configuration for all DAC settings 2016-08-15 10:22:12 -06:00
Gregory Nutt
e53118ffc2 SAMV7 DAC configuration needs some conditional logic 2016-08-15 08:55:11 -06:00
Gregory Nutt
c367e4985f Add configuration logic for the SAMV7 DAC module 2016-08-15 08:21:46 -06:00
Piotr Mienkowski
053aea552f Add support for SAMV7 DACC module 2016-08-15 08:00:36 -06:00
Gregory Nutt
f84780f36e Changes from review of PR 114 2016-08-14 13:38:47 -06:00
Gregory Nutt
2b32869b49 Merged in v01d/nuttx/kinetis-i2c-norestart (pull request #114) 
support NORESTART on kinetis i2c
 2016-08-14 13:27:39 -06:00
v01d
239c56f3b9 support NORESTART 2016-08-14 16:25:18 -03:00
Gregory Nutt
014b8268cc Minor stylistic corrections 2016-08-14 10:14:28 -06:00
Gregory Nutt
45e71a140a Fix some alignment and long line issues 2016-08-13 18:04:09 -06:00
Gregory Nutt
3023724cf2 Changes from review of PR 113 2016-08-13 17:32:35 -06:00
Gregory Nutt
8315b051ca Merged in v01d/nuttx/kinetis_i2c (pull request #113) 
I2C and RTC support for Kinetis
 2016-08-13 16:54:14 -06:00
Gregory Nutt
8052dc4955 STM32 SPI: nbits should be unsigned. Valid range is 4-16 for F3 and L4. 8 or 16 for others. 2016-08-13 16:01:50 -06:00
v01d
5a97def131 kinetis k20 i2c fixed 2016-08-13 18:48:45 -03:00
Gregory Nutt
1a10518dae Update ChangeLog 2016-08-13 12:03:12 -06:00
Gregory Nutt
eed5e41626 Add some comments 2016-08-13 10:24:40 -06:00
Gregory Nutt
172761163b STM32F3 SPI: Cannot write 16-bit value to DR register because of how the F3 implements data packing. 2016-08-13 10:11:23 -06:00
Gregory Nutt
51fcd89b98 Add and fix some SPI debug output 2016-08-13 08:31:37 -06:00
Gregory Nutt
42202c6365 STM32 and STM32L4: Enabling DMA loses other bits in CR2 2016-08-13 08:01:41 -06:00
Gregory Nutt
efc9f674d2 Trivial changes to comments and spacing 2016-08-13 07:50:54 -06:00
Alan Carvalho de Assis
805cb5c752 STM32F3 SPI: Fix a typo 2016-08-13 07:23:48 -06:00
Gregory Nutt
da5563c0e7 STM32: Add conditional logic for STM32F37xx 2016-08-13 06:43:13 -06:00
Gregory Nutt
10f90a1738 STM32 F3: Fix more SPI issues 2016-08-12 19:00:34 -06:00
Gregory Nutt
3383a25c38 Some logic missing from last commit 2016-08-12 18:40:25 -06:00
Gregory Nutt
afb02b56d4 STM32F3 SPI: Fix the number of bit setting for the F3. It works differently than for other parts. 2016-08-12 18:32:37 -06:00
Gregory Nutt
ab16ad7530 Fix some bugs in the oneshot driver logic 2016-08-12 14:19:11 -06:00
Gregory Nutt
046acf6b54 Add a simulated oneshot lowerhalf driver 2016-08-12 13:14:03 -06:00
Gregory Nutt
b4e8876b09 Correct some spacing 2016-08-12 12:41:49 -06:00
Gregory Nutt
82b86cdcf3 oneshot interface: max_delay method should return time in a standard struct timespec form. 2016-08-12 11:33:10 -06:00
Gregory Nutt
89135c55e4 drivers/timer: Add an upper-half, oneshot timer character driver. 2016-08-12 10:40:07 -06:00
Gregory Nutt
61b0ac06bf Missed a dependency in last set of commits 2016-08-11 17:20:12 -06:00
Gregory Nutt
1965e25da4 STM32L4: Add oneshot lower half driver. 2016-08-11 17:14:41 -06:00
Gregory Nutt
a5a776e223 SAM4CM: Add option to support oneshot timer without free-running timer. Add oneshot lower half driver. 2016-08-11 17:04:19 -06:00
Gregory Nutt
fa6866b046 SAMA5: Add option to support oneshot timer without free-running timer. Add oneshot lower half driver. 2016-08-11 16:47:17 -06:00
Gregory Nutt
b4d4a74059 SAMV7: Add option to support oneshot timer without free-running timer. Add oneshot lower half driver. 2016-08-11 16:27:01 -06:00
Gregory Nutt
d0ce5b1d1e Cosmetic changes to comments and function prototypes 2016-08-11 15:15:37 -06:00
Gregory Nutt
fb349508fd STM32 oneshot lower-half: Missed some data initialization. 2016-08-11 14:57:17 -06:00
Gregory Nutt
eb3a565153 STM32: Add oneshot lower half to build system. Fix some build problems. 2016-08-11 14:53:39 -06:00
Gregory Nutt
1bb93021df STM32: Add a experimental oneshot, lower-half driver for STM32 2016-08-11 14:07:43 -06:00
Gregory Nutt
0e35bad987 Update some comments 2016-08-11 10:12:04 -06:00
Gregory Nutt
accbccd78a Merged in mlyszczek/nuttx/stm32f1connline_pllfix (pull request #111) 
Fix bad pllmul values for stm32f1xx connectivity line.
 2016-08-11 06:44:19 -06:00
Michał Łyszczek
81df56086a Fix bad pllmul values for stm32f1xx connectivity line. 
stm32f1xx connectivity line supports only x4, x5, x6, x7, x8, x9 and x6.5 values
 2016-08-11 10:49:57 +02:00
Young
e30a3b780c Fix two bugs of tiva pwm lower-half driver impl. 2016-08-10 13:25:43 +08:00
Gregory Nutt
7823a1680e Update a comment 2016-08-09 17:08:03 -06:00
Gregory Nutt
698d6d1294 SAM3/4: Extend clocking logic to enable clocking on ports D-F 2016-08-09 17:05:11 -06:00
Gregory Nutt
0918dd98ab Merged in gnagflow/nuttx (pull request #109) 
SAM3/4 GPIO: Enable peripheral clock for GPIO port when GPIO is configured as input.
 2016-08-09 16:40:48 -06:00
Gregory Nutt
fdcf0f7e5f Correct some comments 2016-08-09 15:15:21 -06:00
Wolfgang Reissnegger
cf35bb0b18 SAM3/4 GPIO: Enable peripheral clock for GPIO port when GPIO is configured as input. 
The value of a GPIO input is only sampled when the peripheral clock for
the port controller the GPIO resides in is enabled. Therefore we need
to enable the clock even when polling a GPIO.
 2016-08-09 13:23:05 -07:00
Gregory Nutt
b5b7a21bb6 Make reference count a uin16_t and save a couple of bytes. 2016-08-09 13:54:57 -06:00
Gregory Nutt
8b5833f7fe A consequence of Max's change to the logic to enable access to the backup domain is that every call to enabledbkp(true) must be followed by a matching call to enablebkp(false). There was one cse in both RTCC drivers where that may not always be true. 2016-08-09 11:33:47 -06:00
v01d
f715e9b787 RTC working, I2C in progress 2016-08-09 14:01:27 -03:00
Gregory Nutt
5d91b8cabb With last change, stm32_pwr_enablebkp() no longer returns a value 2016-08-09 07:50:31 -06:00
Max Neklyudov
1e3ccbac12 Make stm32_pwr_enablebkp thread safe 2016-08-09 07:36:13 -06:00
Alan Carvalho de Assis
8499f42bf9 Add STM32F37XX DMA channel configuration 2016-08-08 13:29:53 -06:00
Alan Carvalho de Assis
fcf1ae7e05 stm32f37xx: Fix SYSCFG_EXTICR_PORTE defined twice 2016-08-08 12:59:29 -06:00
Alan Carvalho de Assis
834f058573 I'm using NuttX on STM32F373 and saw the config was missing SPI2 and 
SPI3, see datasheet:
www.st.com/resource/en/datasheet/stm32f373cc.pdf

I searched for other members of STM32F37XX family and they also have 3 SPIs:
http://www.st.com/content/st_com/en/search.html#q=STM32F37-t=keywords-page=1
 2016-08-08 12:25:15 -06:00
Gregory Nutt
caea59b340 SPI bit order: Add configuration setting to indicate if an architecture-specif SPI implementation does or does not support LSB bit order. 2016-08-08 12:21:20 -06:00
Gregory Nutt
6df28bc74e Make bit-order SPI H/W feature configurable for better error detection 2016-08-08 11:54:13 -06:00
Gregory Nutt
c3cfd37791 Fix cloned variable error in all SPI drivers 2016-08-08 11:04:01 -06:00
Gregory Nutt
2ae3953f9e STM32/EFM32: If any hardware feature other and LSBFIRST is selected, return -ENOSYS. 2016-08-08 10:37:28 -06:00
Gregory Nutt
7d4cb73bd6 STM32 and EFM32 SPI drivers adopted an incompatible conventions somewhere along the line. The set the number of bits to negative when calling SPI_SETBITS which had the magical side-effect of setting LSB first order of bit transmission. This is not only a hokey way to pass control information but is supported by no other SPI drivers. 
This change three things:  (1) It adds HWFEAT_LSBFIRST as a new H/W feature.  (2) It changes the implementations of SPI_SETBITS in the STM32 and EFM32 derivers so that negated bit numbers are simply errors and it adds the SPI_HWFEATURES method that can set the LSB bit order, and (3) It changes all calls with negative number of bits from all drivers: The number of bits is now always positive and SPI_HWFEATUREs is called with HWFEAT_LSBFIRST to set the bit order.
 2016-08-08 08:28:13 -06:00
v01d
d483f7939f I2C0 support for kinetis/teensy-3.x (to be tested) 2016-08-06 22:23:59 -03:00
Gregory Nutt
56f2454c86 Fix names of pre-processor variables used in header file idempotence 2016-08-06 18:48:45 -06:00
Gregory Nutt
d41008e220 Update some header commments 2016-08-06 18:16:31 -06:00
Gregory Nutt
2b23d4b0e7 Correct some comments 2016-08-06 16:25:02 -06:00
Gregory Nutt
5aaba42b0d Update Renesas REAMDE files 2016-08-06 15:43:27 -06:00
Gregory Nutt
f43ded46e6 Rename arch/sh to arch/renesas, cont'd 2016-08-06 14:03:38 -06:00
Gregory Nutt
8ee155da3d Rename arch/sh to arch/renesas 2016-08-06 13:33:41 -06:00
Gregory Nutt
f5ae207516 Changes from Review of last PR adding Tiva PWM driver 2016-08-05 07:17:42 -06:00
Young
2994decd3c Add tiva PWM lower-half driver implementation 2016-08-05 18:53:25 +08:00
Gregory Nutt
3d5df2e5af Extend I/O Expander interrupt controls; Add test of level sensitve interrupt to Simulated I/O expander 2016-08-04 16:19:52 -06:00
Gregory Nutt
1f9799b68d I/O Expanders: Interrupt detection logic should not ignore the no-change case. Still need to handle level interrupts even with no change. 2016-08-03 13:10:20 -06:00
Gregory Nutt
803b540e8a Fix various issues with I/O expander and GPIO lower half drivers from testing with simulated I/O expander 2016-08-03 12:46:54 -06:00
Gregory Nutt
c11473657c SIM I/O Expander: Add logic to simulate inverted pins and to generate toggle values on interrupt input pins 2016-08-03 11:19:16 -06:00
Gregory Nutt
778a8131bf SIM: Add a simulated I/O Expander driver 2016-08-03 09:44:48 -06:00
Gregory Nutt
b7c1544f0f Sim build: Add sigaddset to nuttx-names.dat 2016-08-01 17:32:55 -06:00
Gregory Nutt
d9314c1034 LPC43xx ADC: board.h should be included last; Also, unreleated, update tools/README.txt 2016-07-30 07:05:10 -06:00
Gregory Nutt
309480d0f9 Merge branch 'timekeeping' of bitbucket.org:nuttx/nuttx 2016-07-28 09:34:00 -06:00
Gregory Nutt
59f626313d Changes from review of last PR 2016-07-25 15:16:51 -06:00
Gregory Nutt
250b9d5597 Merged in JordanMacIntyre/nuttx/PWM_driver (pull request #106) 
Pwm_driver
 2016-07-25 14:59:45 -06:00
jmacintyre
f5ea811c97 create PWM driver, still having issues with building 2016-07-25 14:17:07 -05:00
Stefan Kolb
899a8aa2f0 SAMV7 TRNG: Missing endif. 2016-07-25 12:30:39 -06:00
Gregory Nutt
e895e19b9f Minor changes from review of last PR 2016-07-24 07:45:46 -06:00
Wolfgang Reissnegger
c0fa319f2b SAM3/4 UDP: Fix handling of endpoint RX FIFO banks. 
This fixes a race condition where the HW fills a FIFO bank while the SW is
busy, resulting in out of sequence USB packets.
 2016-07-23 20:11:04 -07:00
Wolfgang Reissnegger
cc191a977d SAM3/4 UDP: Remove redundant EP state assignment. 2016-07-23 20:11:03 -07:00
Wolfgang Reissnegger
f3a6a40f62 SAM3/4 Serial: Fix warning when CONFIG_SUPPRESS_UART_CONFIG is set. 2016-07-23 16:23:49 -07:00
Gregory Nutt
9b9b721406 Rename alarm_enable to rtc_alarm_enabled; mark inline 2016-07-23 12:01:57 -06:00
Gregory Nutt
5a0f9fcb7d Fix STM32 RTC Alarm interrupts. They were being enabled BEFORE the interrupt system was being initialized. 2016-07-23 10:36:06 -06:00
Gregory Nutt
14de4b99f8 Simplify some computations 2016-07-23 08:13:25 -06:00
Gregory Nutt
0984fcda44 Back out last RTC alarm changes. I am mistaken, the interrupts are enabled by stm32[l4]_exti_alarm(). 2016-07-23 07:53:08 -06:00
Gregory Nutt
65ac11692d STM32L4 RTC is cloned from F4; needs same fix. 2016-07-23 07:33:44 -06:00
Gregory Nutt
829c5610da STM32 F4 RTC ALARM: Was not enabling interrupts. 2016-07-23 07:19:14 -06:00
Gregory Nutt
e77872057d Fix up a few remaining incorrect CONFIG_GPIO_IRQ 2016-07-22 15:01:00 -06:00
Gregory Nutt
e897ccb940 Rename x86 QEMU version of CONFIG_GPIO_IRQ to CONFIG_QEMU_GPIOIRQ 2016-07-22 14:54:00 -06:00
Gregory Nutt
5a9519d636 Rename HCS12 version of CONFIG_GPIO_IRQ to CONFIG_HCS12_GPIOIRQ 2016-07-22 14:53:17 -06:00
Gregory Nutt
c00ad93165 Rename HC version of CONFIG_GPIO_IRQ to CONFIG_HCS12_GPIOIRQ 2016-07-22 14:46:54 -06:00
Gregory Nutt
e6137ff129 Rename SAMD/L version of CONFIG_GPIO_IRQ to CONFIG_SAMDL_GPIOIRQ 2016-07-22 14:38:33 -06:00
Gregory Nutt
3aea9b8bf3 Rename KL version of CONFIG_GPIO_IRQ to CONFIG_KL_GPIOIRQ 2016-07-22 14:34:21 -06:00
Gregory Nutt
5386403476 Rename Kinetis version of CONFIG_GPIO_IRQ to CONFIG_KINETIS_GPIOIRQ 2016-07-22 14:30:37 -06:00
Gregory Nutt
264578135d Rename LP11xx version of CONFIG_GPIO_IRQ to CONFIG_LPC11_GPIOIRQ 2016-07-22 14:23:31 -06:00
Gregory Nutt
360efe03c1 Rename LP17xx version of CONFIG_GPIO_IRQ to CONFIG_LPC17_GPIOIRQ 2016-07-22 14:18:30 -06:00
Gregory Nutt
369c942605 uint8_t is big enough for global. Range of values only 2-10 2016-07-21 15:18:27 -06:00
Gregory Nutt
67900beaaa LP43 Heap: REALLY eliminate the warning this time 2016-07-21 15:15:56 -06:00
Gregory Nutt
d5acc120a4 Kinetis K60: Fix some bad conditional compilation 2016-07-21 14:22:00 -06:00
Gregory Nutt
a2035f7efd Move include/nuttx/1wire.h to include/nuttx/drivers/1wire.h 2016-07-21 13:51:28 -06:00
Gregory Nutt
96d5b734a8 Add missing TWI definitions 2016-07-21 08:01:59 -06:00
Gregory Nutt
0d98507af1 Eliminate a warning 2016-07-20 16:47:23 -06:00
Gregory Nutt
ee9c66186c ramdisk.h moved from include/fs/nuttx/ to include/nuttx/drivers. 2016-07-20 14:02:18 -06:00
Gregory Nutt
1b9b3a7b47 pwm.h moved from include/nuttx/ to include/nuttx/drivers. 2016-07-20 13:48:24 -06:00
Gregory Nutt
ddcaa3d425 can.h moved from include/nuttx/ to include/nuttx/drivers. 2016-07-20 13:38:36 -06:00
Gregory Nutt
4b4dbc79a2 Move driver related prototypes out of include/nuttx/fs/fs.h and into new include/drivers/drivers.h 2016-07-20 13:15:37 -06:00
Sagitta Li
e07bd757ba STM32 F107: TIM8 not supported in F105/F107 2016-07-20 08:51:03 -06:00
Ken Pettit
b926334a19 Add file was not included in the original commit 2016-07-19 10:39:43 -06:00
Vytautas Lukenskas
ac2a5e079c Add change missing in Make.defs for last LPC43xx change 2016-07-19 09:28:15 -06:00
Gregory Nutt
8eeecff79d Replace some C99 comnents with C89 comments 2016-07-19 08:19:53 -06:00
Ken Pettit
148cf1ac22 Adds the simulated QSPI (N25Q) flash to the simulation and modify sim up_spiflash.c to enable it to run with different MTD drivers based on config options (currently m25p, sst26 and w25). 2016-07-19 07:33:44 -06:00
Vytautas Lukenskas
f222d37aa7 Extend LPC43xx EMC code to support SDRAM on a dynamic memory interface. 2016-07-19 07:11:04 -06:00
Gregory Nutt
2119c5ce19 Fix another function naming error 2016-07-18 12:40:27 -06:00
Gregory Nutt
d36da2b560 Fix bad dev[u]random_register() function return value. 2016-07-18 12:25:05 -06:00
Gregory Nutt
d5388eca05 devrandom_register() must be called before devurandom_register() 2016-07-18 11:24:04 -06:00
Gregory Nutt
078bbe5e5c All H/W RNG Drivers: Can now be configured to register as /dev/random and/or /dev/urandom 2016-07-18 11:10:37 -06:00
Gregory Nutt
1660329d06 Rename up_rnginitialize to devrandom_register 2016-07-18 10:55:37 -06:00
Gregory Nutt
fe315f867a Costmetic 2016-07-17 17:01:35 -06:00
Gregory Nutt
006f4a5818 HOSTFS: Fix some errors in first cut at repartitioning 2016-07-17 16:31:14 -06:00
Gregory Nutt
2b28a1f3e5 SIM HOSTFS: First cut at changes to get it working on Cygwin. 2016-07-17 15:59:45 -06:00
Gregory Nutt
76dc238baf Add more name mappings to nuttx-names.dat 2016-07-17 09:44:27 -06:00
David Alessio
6cefbc0c3f This change provides an option to add /dev/urandom to all architectures. The pseudo-random algorithm I choose strikes an arguably-good balance between being "random" and small/fast enough for 8/16 bit MCUs. It’s the well-documented xorshift128 algorithm. It has an internal state of 128 bits that can be [re-]seeded with a write. 2016-07-17 06:42:26 -06:00
Alan Carvalho de Assis
91ba0be667 Enable TERMIOS support in stm32discovery/pseudoterm configuration 2016-07-16 17:49:37 -06:00
Gregory Nutt
ba62b49190 SIM: Add more names to nuttx-namex.dat 2016-07-16 16:14:18 -06:00
Gregory Nutt
873f1f6da5 Merged in HeathPetersen/nuttx (pull request #102) 
EXEEXT only needs to be appended once
 2016-07-15 17:11:22 -06:00
Heath Petersen
c57672aeab EXEEXT only needs to be appended once 2016-07-15 17:50:00 -05:00
Gregory Nutt
e7f0a56498 Correct some comments 2016-07-15 13:13:53 -06:00
Gregory Nutt
7b298a828d up_pminitialize() needs to be called from instances of up_initialize() 2016-07-15 13:11:28 -06:00
Gregory Nutt
d3b3c71d97 All architectures: Add logic to automatically register /dev/ptmx a boot time 2016-07-15 11:54:41 -06:00
Young
7005fafb95 Fix a bug of tiva i2c ports configuration 2016-07-15 11:03:48 +08:00
Gregory Nutt
18059d6821 Restore Wolfgang Reissnegger's PR as submitted. My mistake is it late here. 2016-07-14 18:39:51 -06:00
Wolfgang Reissnegger
f982180ec7 SAM3/4 Timer: Remove broken definitions for BMR register. 
Per documentation SAM4S and SAM4E have the BMR register values
as they are already defined. No need for chip specific values.

In addition:
 - CONFIG_ARCH_CHIP_SAM4s has wrong lower case 's' so the definitions would
   not be used anyways for SAM4S builds.
 - TC_BMR_TC2XC2S_TIOA2 does not make sense. There is no way to loop back
   TC2's TIOA2 into itself.
 2016-07-14 18:17:05 -06:00
Gregory Nutt
54bc6c88dd Fix cast of return value 2016-07-14 10:21:31 -06:00
Gregory Nutt
3f6835fda9 If CONFIG_SPIFI_SECTOR512 undefined, lpc43_bwrite doesn't do actual write (probably copy/paste errors). Still not sure about current state of lpc43_spifi implementation, but for me NXFFS works with this patch. From Vytautas Lukenskas. 2016-07-14 10:11:19 -06:00
Pierre-noel Bouteville
76f12b1f69 I'm using syslog through ITM. In this case syslog_channel function is call before ram initialisation in stm32_clockconfig. But syslog channel uses a global variable that is reset to default by the RAM initialization. 2016-07-14 07:29:39 -06:00