Commit Graph

14195 Commits

Author SHA1 Message Date
raiden00pl
f3fdd5a019 arch/arm/src/nrf52/Kconfig: select IRQPRIO for SoftDevice 2021-12-18 09:13:36 -06:00
raiden00pl
a6c64795f4 arch/arm/src/nrf52/nrf52_sdc.c: raise error if BT device not selected 2021-12-18 09:13:36 -06:00
raiden00pl
cf2dae8d79 arch/arm/src/nrf52/nrf52_sdc.c: nxstyle fixes 2021-12-17 12:35:17 -06:00
raiden00pl
af143c96fc arch/arm/src/nrf52/nrf52_sdc.c: public device address and static device address support 2021-12-17 12:35:17 -06:00
raiden00pl
c7f6ac63b0 arch/arm/src/nrf52/nrf52_sdc.c: add option to register UART H4 device 2021-12-17 12:35:17 -06:00
raiden00pl
23ef3ea64c arch/arm/src/nrf52/nrf52_sdc.c: remove nedless new lines 2021-12-17 12:35:17 -06:00
raiden00pl
26951f5018 arch/arm/src/nrf52/nrf52_sdc.c: print HCI opcode as hex 2021-12-17 12:35:17 -06:00
raiden00pl
07c9204fd6 arch/arm/src/nrf52/nrf52_sdc.c: fix status byte offset 2021-12-17 12:35:17 -06:00
raiden00pl
ab66800e13 arch/arm/src/nrf52/Kconfig: fix typos 2021-12-17 12:35:17 -06:00
raiden00pl
ba6e8696b2 arch/arm/src/nrf52/hardware/nrf52_ficr.h: add device address types 2021-12-17 12:35:17 -06:00
raiden00pl
07d295b8db add 5-Clause Nordic License barrier for Nordic SoftDevice Controller 2021-12-17 11:22:39 -06:00
Gerson Fernando Budke
2dd5578d50 arch/arm/src/samv7/Kconfig: Define mem sizes
Current samv7 platform does not define SoC memories sizes. This define
both internal flash and sram memories sizes and update all defconfig
files.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2021-12-16 06:56:42 -03:00
Alexander Lunev
0aecfe8691 stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode.
When it was in slow speed mode (by default), the output SDMMC_CK clock rise and
fall times were about 13 ns each, that were very slow and
prevented some SDIO devices from working.
2021-12-16 01:28:05 -06:00
chao.an
b11833cbba arch/assert: flush the syslog before stack dump
flush the syslog before stack dump to avoid buffer overwrite

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-15 12:00:35 -06:00
Petro Karashchenko
51a2db6ffc Kconfig: improve uniformity
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-14 07:32:48 -06:00
Petro Karashchenko
af614ac77d tls: restore C89 compatibility for TLS
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-13 21:14:53 -06:00
chao.an
c2fd66bfab arch/arm/risc-v/xtensa: add support of all symbols for debugging
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-13 08:31:13 -06:00
chao.an
89e2f00dad arch/assert: fix the stack dump overflow
[ EMERG] kasan_report: kasan detected a read access error, address at 0x3c24fca8, size is 4
[ EMERG] up_assert: Assertion failed at file:kasan/kasan.c line: 104 task: init
[ EMERG] backtrace|10:  0x2c334666 0x2c35f0d6 0x2c359ef6 0x2c35f830 0x2c360ed4 0x2c3615c0 0x2c324e0c 0x2c30a168
[ EMERG] up_registerdump: R0: ffffffff R1: 00000004 R2: ffffffff R3: ffffffff
[ EMERG] up_registerdump: R4: 3c20d4f0 R5: 2c35acd5 R6: 00000000 FP: 3c24fae8
[ EMERG] up_registerdump: R8: 3c20d504 SB: ffffffff SL: 2c413e7c R11: 2c411eb8
[ EMERG] up_registerdump: IP: 00000002 SP: 3c24fae8 LR: 00000003 PC: 2c35f0d6
[ EMERG] up_registerdump: xPSR: 61010000 BASEPRI: 000000e0 CONTROL: 00000004

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-13 01:43:18 -06:00
chao.an
0b7b8d274f arm/cortex-m: enhance the crash dump
1. add irq stack information to list
2. add cpu loading into list

before:

Idle Task: PID=0 PRI=0 Stack Used=512 of 3048
hpwork: PID=1 PRI=224 Stack Used=304 of 2016
lpwork: PID=2 PRI=100 Stack Used=304 of 2016
rptun: PID=4 PRI=224 Stack Used=856 of 2008

after:

[ EMERG] [ap] up_showtasks:    PID    PRI      USED     STACK   FILLED       CPU   COMMAND
[ EMERG] [ap] up_showtasks:   ----   ----       928      2048    45.3%      ----   irq
[ EMERG] [ap] up_dump_task:      0      0       512      3048    16.7%     99.4%   Idle Task
[ EMERG] [ap] up_dump_task:      1    224       304      2016    15.0%      0.0%   hpwork
[ EMERG] [ap] up_dump_task:      2    100       304      2016    15.0%      0.0%   lpwork
[ EMERG] [ap] up_dump_task:      4    224       856      2008    42.6%      0.0%   rptun

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-12 21:40:29 -06:00
Matheus Castello
294694bb2f arch: arm: select LIBC_ARCH_ATOMIC when config ARCH_CHIP_RP2040
Use the common atomic operations when needed.

Signed-off-by: Matheus Castello <matheus@castello.eng.br>
2021-12-11 11:32:17 -06:00
Juha Niskanen
a35d205f3b arch/arm/src/stm32l4/stm32l4_pwm.c: fix printf format
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-12-10 12:30:26 -06:00
Daniel Agar
efc949bceb arch/arm/src/stm32/Kconfig STM32_STM32F412 add SPI2 & SPI3 2021-12-09 21:30:41 -06:00
chao.an
3d75c25737 cortex-m/hardfault: enhance the dump information of mem/hard-fault
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
66e604b40e cortex-m/hardfault: add usage-fault handler
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
2f449245cc cortex-m/hardfault: add bus-fault handler
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
99fa58c871 arm/cortex-m23: armv8-m baseline do not support mem-fault
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 05:36:00 -06:00
chao.an
3e812dd88c cortex-m/fault: add CFSR(Configurable Fault Status Register) Definitions
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 04:30:06 -06:00
Xiang Xiao
6357523892 arch: Add _wchar_t typedef like other basic types
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-09 16:57:23 +09:00
chao.an
9b502dca05 arm/backtrace: disable the sanitize address check
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 01:05:46 -06:00
chao.an
7a61588b00 cortex-m/backtrace: remove the push process to simplify backtrace
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 01:05:46 -06:00
chao.an
437c81f8d0 cortex-m/assert: dump all registers with alias
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 00:16:04 -06:00
Michal Lenc
ae57492189 samv7: enable MCAN driver support for both rev A and rev B
This commit enables the MCAN driver to function with both rev A and rev B
version of the chip. The version of the chip is selected automtically from
SAM_CHIPID_CIDR register so there is no need to predefined it in the
configuration.

The functonality was tested on rev B version of the chip. The rev A was
not tested since I do not have the functional board but the code remains
the same as in the previous NuttX version so it should not cause any
additional troubles.

The code is co-authored by Miloš Pokorný who wrote the initial transition
to rev B of the chip.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Co-authored-by: Miloš Pokorný <milos.pokorny@seznam.cz>
2021-12-07 23:36:11 -06:00
Huang Qi
58e0781e2e arch/arm: Implement TLS support
Signed-off-by: Huang Qi <no1wudi@qq.com>
2021-12-07 23:31:41 -06:00
Masayuki Ishikawa
bec9058b4c arch: lc823450: Replace the critical section with spinlock in lc823450_serial.c
Summary:
- This commit replaces the critical section with spinlock
- The logic is the same as cxd56_serial.c

Impact:
- None

Testing:
- Tested with lc823450-xgevk:bt

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-12-07 23:28:54 -06:00
fenghang
c39ef4420e 1.phyplus update files to accord with the requirement of chcekpatch.sh
2.fix some files to fix compile warning

3.remove blueteeth header files, which are not used in nuttx core.

4.fix configs and add lost files

5.update defconfig, remove useless items

6.fix compile warning for nuttx phyplus

7.delete useless: ble, h4, zblue defconfig files form phyplus configure folder

8.fix file format check error on phyplus source code

9.fix phyplus kconfig param error

10.update configure file for nuttx
2021-12-07 01:37:29 -06:00
fenghang
073c9880a3 phyplus first submit 2021-12-07 01:37:29 -06:00
chao.an
437a30d117 arch/tcbinfo: fix build break if task name disabled
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-06 00:47:58 -06:00
Xiang Xiao
a0990ee416 arch: Remove the duplicated up_tls_info implementation
Define up_tls_info in arch/arch.h directly if the general one isn't suitable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-05 20:59:53 -06:00
Xiang Xiao
19e5ee6ce0 arch: Remove FILE dump code from _up_dumponexit
since the kernel build can't access the userspace memory
inside other process directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-06 11:23:58 +09:00
Xiang Xiao
b65c7c26cf arch: Dump task name through tcb_s::name instead of argv[0]
since argv is defined in task_tcb_s not tcb_s

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-01 16:04:15 +01:00
Gerson Fernando Budke
c3307fce6b arch/arm/Kconfig: Add ARCH_HAVE_PROGMEM config
The Atmel samv7 implements progmem functionality. However, there is
missing ARCH_HAVE_PROGMEM Kconfig symbol. This add missing symbol.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2021-11-29 21:31:08 -06:00
Petro Karashchenko
31809724e1 boards/same70-xplained: disable systick before loading MCUboot application
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-28 20:33:53 -06:00
Petro Karashchenko
fae27cc945 arch/samv7: fix unaligned address write for progmem interface
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-28 11:04:28 -06:00
Michal Lenc
ce53ea5da6 arch/arm/src/samv7: add DMA and TC trigger support to AFEC driver
This commit adds DMA and TC support to SAMV7 AFEC driver. The AFEC (ADC)
can now be triggered by Timer/counter at chosen frewuency and samples can
be transfered via DMA with configurable number of samples. Timer/counter
trigger is now set as a default option with the possibility to change it
to software generated trigger.

DMA is inspired by SAMA5 driver and also uses ping pong buffers.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-11-27 06:17:45 -06:00
Michal Lenc
6f2e23ad0c arch/arm/src/samv7/sam_tc.c: fix compile warnings and errors
Just a minor change fixing some compile warnings and errros, does not have
any impact on functionality.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-11-27 06:17:45 -06:00
Petro Karashchenko
0d9425676d arch/arm/src/samv7: add flash progmem erasestate ioctl support
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-26 14:55:34 -03:00
Petro Karashchenko
134b2e6ec9 arch/arm/include/samv7: fix typo in samv7 irq header files
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-26 14:55:34 -03:00
Petro Karashchenko
dd647d200e arch/samv7/sam_progmem: fix page size flash writing
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-26 08:47:08 -06:00
zhuyanlin
1b3005accf arch:cache_invalidate: fix unalign cacheline invalidate
Only invalidate may corrupt data in unalign start and end.
Use writeback and invalidate instead.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-24 22:48:13 -06:00
zhuyanlin
4db5016d83 arch:hostfs: add cache coherence config for semihosting option
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-24 22:48:13 -06:00
David Sidrane
ad7e36d83f stm32f7:sdmmc defer invalidate until after DMA completion
The FAT was not coherent. Resulting in a write failed
   with errno:28 No space left on device.

   It is unclear how the memory is acesses prior to the DMA
   completion. But this restructuring ensures the data
   is coherent.

   This issue was not detected on the stm32h7
2021-11-24 20:38:23 -06:00
chao.an
7cbb8da692 binfmt/elf: add bare metal coredump support
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-11-23 20:48:00 -06:00
chao.an
4c76c356ef arch/arm: add more arch elf define
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-11-23 20:34:56 +09:00
Xiang Xiao
a29ee19af4 driver/motor: Remove the unnecessary critical section operation
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-11-18 19:27:07 -06:00
Xiang Xiao
a799835ec6 arch/arm: Remove EXPERIMENTAL from ARCH_TRUSTZONE_XXX
since it work on the product device

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-17 08:59:14 -03:00
Andres Sanchez
064f6c8c55 add MTDIOCTL_PROGMEM_ERASESTATE support
Signed-off-by: Andres Sanchez <tito97_sp@hotmail.com>

solve style check errors.
2021-11-16 14:45:03 -03:00
Alin Jerpelea
6deaba896d arch: Haltian Ltd: update licenses to Apache
Gregory Nutt has submitted the SGA
Haltian Ltd has submitted the SGA
Uros Platise has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-11-15 06:49:32 -06:00
Xiang Xiao
2262ddfa6d arch: Remove fflush(stdout) from driver code
it's wrong to call stdio function inside driver

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-15 00:04:12 +01:00
zhuyanlin
012bd1494c arch:debug: add struct for task aware debug.
When enable DEBUG_TCBINFO config, a global struct will
provide, then debuggers can aware nuttx task infomation.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-10 14:31:10 -03:00
Juha Niskanen
201c67acbd stm32l4 dfumode: enable for STM32L4+ chips 2021-11-10 11:18:37 -06:00
Michal Lenc
e0cef411e1 arch/arm/src/samv7: add support for AFEC (ADC) driver
This commit adds microcontroller support for Analog Front End driver to
samv7 MCUs. Only software trigger via IOCTL is currently supported,
averaging can be set by configuration option CONFIG_SAMV7_AFECn_RES.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-11-07 21:04:56 -06:00
Yuichi Nakamura
3a0cd56623 rp2040: support I2C_RESET 2021-11-07 03:43:22 -08:00
Yuichi Nakamura
c109262a7f rp2040: add rp2040_gpio_get_function_pin() 2021-11-07 03:43:22 -08:00
raiden00pl
7b595ab73a arch/arm/stm32/stm32_qencoder: add support for Qenco index pin 2021-11-07 03:52:48 -06:00
David Sidrane
4b96c28ed4 stm32h7:Support SPI SPI_DELAY_CONTROL 2021-11-06 05:14:05 -05:00
David Sidrane
040a04241e drivers/spi:Define SPI_~CS~_DELAY_CONTROL to support other delays 2021-11-06 05:14:05 -05:00
David Sidrane
c077361a8a imxrt:usb Fix EP type allocation 2021-11-04 13:23:25 -05:00
David Sidrane
95f7f4b9e6 imxrt:usb DMA cache aligned Buffers for Endpoints 2021-11-04 13:23:25 -05:00
David Sidrane
bd2bc1e351 imxrt:usbdev Clean up cache maintainence 2021-11-04 13:23:25 -05:00
David Sidrane
c3d10ad0aa imxrt:usbdev formatting cleanup 2021-11-04 13:23:25 -05:00
David Sidrane
532635129c imxrt:usdhc add proper support for dcache (wb) 2021-11-04 13:23:25 -05:00
David Sidrane
5022244339 imxrt mpuinit:Set Data and Code Type to Normal
Strongly-Ordered requires aligned access unless
  caching is enabled.

  Normal memory
  Accesses to normal memory region are idempotent...
  - unaligned accesses can be supported
2021-11-04 13:23:25 -05:00
David Sidrane
34c3efcb91 imxrt mpuinit:Remove duplicate entry for ITCM (0x0) 2021-11-04 13:23:25 -05:00
David Sidrane
08d0434bad imxrt:mpu init handle dcache setting in MPU config
With CONFIG_ARMV7M_DCACHE the cache maintenance operation
   are not present. Or if CONFIG_ARMV7M_DCACHE_WRITETHROUGH
   is on then buffering operations are no-ops.

   This change enables MPU_RASR_C and MPU_RASR_B if
   CONFIG_ARMV7M_DCACHE is only set.

   if CONFIG_ARMV7M_DCACHE_WRITETHROUGH is set then only
   MPU_RASR_C is enabled.

   N.B When caching is disalbed unaligned access may cause hard faults
   so add -mno-unaligned-access

   It is always safe to enable Buffering in FLASH to achive unaligned
   access leniency, as it is not written to.
2021-11-04 13:23:25 -05:00
Alexander Lunev
60de445ab3 stm32h7 sdmmc: do not enable power saving configuration bit (in SD 4-bit mode) because
the SDIO clock is not enabled when the bus goes to the idle state, that, in turn, breaks
IRQ delivering mechanism over DAT[1]/IRQ SDIO line to the host.
2021-11-03 22:50:14 -05:00
ligd
2f4662c513 arch/arm: Remove -mcpu for fix warning
warning: switch '-mcpu=cortex-m55' conflicts with '-march=armv8-m.main' switch

Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-11-01 21:28:10 -05:00
ligd
8417b4726b Revert "arch/armv8-m: use -mfpu=auto based on -mcpu=cortex-m55"
This reverts commit d9a5b92c1a306a70df52d50a02a80dc8ef20bf0d.

Revert "arch/arm: Remove -march and -mtune"

This reverts commit b8e99cf12f3a287311a2d341f285c71a5da3e4d4.
2021-11-01 21:28:10 -05:00
Alexander Vasiljev
aeb1d3098d stm32h7/dmamux: correct bit fields 2021-11-01 14:40:33 -03:00
Alexander Lunev
33d236121f stm32h7 sdmmc: added missing sdio_set_sdio_card_isr() function to initialize SDIO in-band interrupt logic 2021-10-31 22:26:13 -05:00
Xiang Xiao
b58379b738 arch/arm: Add l suffix for INT32_C macro
since int32_t typedef to signed long

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-10-31 12:56:41 -03:00
Michal Lenc
a64903acc7 samv7: adds support for QSPI driver in SPI Mode
This commit adds new files that support functionality of QSPI driver in
SPI Master Mode. This functionality is included in new files sam_qspi_spi.x
to avoid too much mess in the source code. QSPI in SPI mode can be turn
on by config option SAMV7_QSPI_SPI_MODE.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-10-30 01:24:31 -05:00
raiden00pl
bb5e3fee44 arch/arm/src/stm32/stm32_foc.c: define missing FOC1_PWM_FZ_BIT for G4 2021-10-29 07:49:59 -05:00
raiden00pl
8e9e54cad3 arch/arm/src/stm32/hardware/stm32_dbgmcu.h: fix invalid STM32_DBGMCU_APB2_FZ offset for G4 2021-10-29 07:49:59 -05:00
Alexander Vasiljev
35e93644cf stm32h7: add low power timers 2021-10-27 10:37:05 -05:00
Jiuzhu Dong
1ed4118378 power/battery: add baterr, batinfo, batwarn for debug log
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-10-26 13:59:42 -03:00
David Sidrane
e1a0a1188e stm32h7:Support CONFIG_MPU_RESET and CONFIG_ARM_MPU_EARLY_RESET 2021-10-23 03:58:26 -05:00
David Sidrane
e66423229a stm32f7:Support CONFIG_MPU_RESET and CONFIG_ARM_MPU_EARLY_RESET 2021-10-23 03:58:26 -05:00
David Sidrane
fd2c1cb216 stm32:Support CONFIG_MPU_RESET and CONFIG_ARM_MPU_EARLY_RESET 2021-10-23 03:58:26 -05:00
David Sidrane
9d8f7126f6 armv7-m,armv7-r,armv8-m:MPU Add mpu_reset and ARM_MPU_EARLY_RESET
When NuttX is booted from a foreign (non NuttX)
   bootloader. There as a possibility that the
   bootloader configured the MPU, in an
   incompatible way for the NuttX memory usage.

   The option to reset the MPU before it is initialized
   may not succeed if the bss and data initialization
   code violated the previous MPU configurations.

   Added herein are ARM_MPU_RESET and
   ARM_MPU_EARLY_RESET. The former can be used
   If the system is capable of booting and running
   NuttX MPU configuration code without an MPU
   violation. The latter is used if the system can
   not run the bss and data initialization code.

   These are options so that a NuttX may be configured to
   not clobber a bootloader MPU configuration in a system
   that is architected to share the MPU configuration task.
2021-10-23 03:58:26 -05:00
David Sidrane
90cfa6f313 imxrt:syslog is dependant on arm_lowputc 2021-10-22 10:07:20 -05:00
oreh-a
3c1ac89557 Fixed line length 2021-10-22 09:03:14 -05:00
Alexander Oryshchenko
ed392abb83 Added ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG option to stm32f0/g0/l0 chip configiuration 2021-10-22 09:03:14 -05:00
Michal Lenc
3e1ce5f770 arch/arm/src/imxrt/hardware: add header file for ADC_ETC module
This commit adds header file imxrt_adc_etc.h for external ADC trigger
module. This contains only definitions of ADC_ETC registers and separate
bits, implementation of ADC_ETC driver is yet to be done.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-10-17 16:50:59 +02:00
Abdelatif Guettouche
7549de49b4 arch/*_cpupause:Allow a spin before taking the g_cpu_wait spinlock.
If we repeatedly call up_cpu_pause and up_cpu_resume, there would be
cases where the next call to up_cpu_pause happens while the other CPU is
still responding to the previous resume request. In this case the
DEBUGASSERT will trigger. We should allow the first CPU to wait until the
other CPU has finished responding to the resume request.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-17 21:10:23 +09:00
Alin Jerpelea
b9986ca016 arch: arm: update licenses to Apache
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-10-11 10:13:07 +02:00
Jari van Ewijk
e4752fbaee S32K1xx arch: Add (optional) support for SPI native/hardware chip select 2021-10-05 06:07:18 -07:00
Jari van Ewijk
cf6dcbc6fd S32K1XX arch: gpioread may also be used for output pins 2021-09-30 04:30:50 -07:00
Xiang Xiao
77bc1d1bdf power/battery: Move the enumurate to the common place
so the userspace program can handle the different battery driver equally

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-09-30 14:58:42 +09:00
P.Brier
b9d1fcb232 Use ethernet MAC programmed in imxrt OCOTP MAC0/MAC1 (teemsy board has this) 2021-09-29 20:45:14 -07:00
Alin Jerpelea
15a37c5a5a arch: Omni Hoverboards: update licenses to Apache
Gregory Nutt has submitted the SGA
Omni Hoverboards has submitted the SGA
David Sidrane has submitted the ICLA
Mateusz Szafoni has submitted the ICLA
Sebastien Lorquet has submitted the ICLA
Paul Alexander Patience has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-09-28 04:37:38 -07:00
Jari van Ewijk
62c41a723b s32k1xx_eeeprom.c - fix compiler warnings 2021-09-27 06:02:59 -07:00
Xiang Xiao
47c60b2de8 arch/arm: Remove -march and -mtune
since -mcpu is enough https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58869

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-09-23 11:48:11 +02:00
Jari van Ewijk
bbb2f1f8c7 S32K1XX: Add LPI2C slave support 2021-09-22 19:36:34 -07:00
David Sidrane
6d299ce802 stm32h7:DMA_TRBUFF is DMA_SCR_TRBUFF 2021-09-22 22:48:10 -03:00
Jari van Ewijk
e5f17f6604 S32K1XX: Add FlexIO registers 2021-09-22 03:15:42 -07:00
David Sidrane
a9ff808dd1 stm32xx:sdmmc/sdio remove redundant GPIO config
The stm32_gpiosetevent calls stm32_configgpio. So
   the pin is infact restored to the SDMMC/SDIO D0.

   The seconday init, dropped interrupts in a debug
   build with HW stack checking on after the GPIO glich
   fixes and that was how it was detected.
2021-09-21 18:25:16 -07:00
David Sidrane
a8d5f21f81 stm32H7:Etablish device before enabling outputs
This prevents gliches on changing to an output mode.
   If not the ALT mux can be selecting a IP block that
   is drving the line to say 0. Then the output is connected
   to that source, then swithced to the correct source.
2021-09-21 18:25:16 -07:00
David Sidrane
5e19ebb818 stm32F7:Etablish device before enabling outputs
This prevents gliches on changing to an output mode.
   If not the ALT mux can be selecting a IP block that
   is drving the line to say 0. Then the output is connected
   to that source, then swithced to the correct source.
2021-09-21 18:25:16 -07:00
David Sidrane
d5e306e6f3 stm32:Etablish device before enabling outputs
This prevents gliches on changing to an output mode.
   If not the ALT mux can be selecting a IP block that
   is drving the line to say 0. Then the output is connected
   to that source, then swithced to the correct source. This
   produced a 430 nS glich on a F4 @168 Mhz. It was a enough
   to corrupt an I2C device with a bus monitor.
2021-09-21 18:25:16 -07:00
P.Brier
35824b449a Added CONFIG_ETH0_PHY_DP83825I to imxrt_enet: make driver compile for teensy 4.1 (link detection needs more checks to see if it works as expected) 2021-09-21 10:27:33 -03:00
P.Brier
f9850cf433 Fixed imxrt flexcan driver compilation error due to incorrect scope of variable 2021-09-21 10:00:12 -03:00
Xiang Xiao
75a119ac1c arch: Compile up_puts in all Make.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-09-18 07:33:44 -03:00
Masayuki Ishikawa
204d88bcf3 arch: cxd56xx: Replace the critical section with spinlock in cxd56_serial.c
Summary:
- This commit replaces the critical section with spinlock in cxd56_serial.c

Impact:
- None

Testing:
- Tested with spresense:rndis_smp, spresense:rndis
  and spresense:rndis_wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-09-16 21:56:40 -05:00
Alin Jerpelea
48f92e6f1d author: Bill Gatliff : update licenses to Apache
Gregory Nutt has submitted the SGA
Bill Gatliff has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-09-16 21:56:08 -05:00
Cis van Mierlo
b316c679c1 S32K1xx: added PM support 2021-09-15 12:20:23 -03:00
SPRESENSE
74df4b70b3 drivers: video: Rearchitect video driver
Rearchitect video driver:
- Define two video I/F(struct imgsensor_ops_s and struct imgdata_ops_s),
  and support them.
- CISIF driver supports new video I/F struct imgdata_ops_s.
- ISX012 driver supports new video I/F struct imgsensor_ops_s.
- Move ISX012 driver to general driver directory.
2021-09-15 07:06:35 +02:00
Juha Niskanen
4487b352c0 arch/arm/src/stm32l4: fix baud rate setting for LPUART
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-09-14 08:57:25 -07:00
Harri Luhtala
7e3c813346 arch/arm/src/stm32l4: LPUART1 support
Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
2021-09-14 08:57:25 -07:00
Abdelatif Guettouche
198c30eaa6 stm32*7/stm32_serial.c: Don't fake an interrupt when interrupts are not
suppressed.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-14 22:50:43 +08:00
chao.an
ba9b829372 arch/arm: correct the function name from arm_getsp() to up_getsp()
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-09-14 22:48:47 +08:00
Cis van Mierlo
91c945a2e8 s32k1xx: added way to get the reset cause in proc fs 2021-09-14 08:35:41 +02:00
Alin Jerpelea
bb54ed4227 author: OffCode Ltd : update licenses to Apache
OffCode Ltd has submitted the SGA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-09-13 22:43:36 +08:00
Xiang Xiao
850367d5bb arch/arm: Add ARCH_CORTEXM55 Kconfig for cortex-m55
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-09-12 09:09:42 -03:00
Abdelatif Guettouche
31aa616bf2 stm32_serial.c: Don't fake a TX interrupt when interrupts are not
suppressed.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-09-10 15:15:44 -07:00
David Sidrane
41e1696b27 stm32f4:USB otgdev Ensure proper EP state
Repeated automated sercon, serdis on VBUS proved to fail
   for CDCACM DATA IN (device Serial TX). The root cause was
   that the EP was left active after disconnect. This resulted
   in the first serial write falling to kick-off the EP IN request.
   That should restart the EP ISR.
2021-09-09 14:27:41 -04:00
David Sidrane
e488f0047d stm32h7:USB otgdev Ensure proper EP state
Repeated automated sercon, serdis on VBUS proved to fail
   for CDCACM DATA IN (device Serial TX). The root cause was
   that the EP was left active after disconnect. This resulted
   in the first serial write falling to kick-off the EP IN request.
   That should restart the EP ISR.
2021-09-09 14:27:41 -04:00
David Sidrane
21f049b43a stm32f7:USB otgdev Ensure proper EP state
Repeated automated sercon, serdis on VBUS proved to fail
   for CDCACM DATA IN (device Serial TX). The root cause was
   that the EP was left active after disconnect. This resulted
   in the first serial write falling to kick-off the EP IN request.
   That should restart the EP ISR.
2021-09-09 14:27:41 -04:00
Harri Luhtala
d4e59b7e8d arch/arm/src/stm32l4: add control for Vddio2 independent I/Os supply valid
Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
2021-09-09 08:26:08 -03:00
YAMAMOTO Takashi
58bdcbab9b Revert "Make: use gcc as LD"
This reverts commit 45672c269d.

Because:

* It's very confusing to have cc as LD.
* I don't see what "-nostartfiles -nodefaultlibs" in LDFLAGS are
  supposed to do when we use LD directly. It would be simpler to
  remove them from our LDFLAGS.
2021-09-08 09:40:48 +08:00
Jari van Ewijk
5f63fa391f Fix error in s32k118_pinmux.h 2021-09-07 17:34:19 -07:00
YAMAMOTO Takashi
5ad1cba338 Revert "arch: Replace ar and nm with gcc-ar and gcc-nm"
This reverts commit b05737d78f.

Because it broke clang-based builds.
2021-09-07 10:54:15 +08:00
Fotis Panagiotopoulos
eb48a0dbe0 Fix in STM32_UART8 Kconfig. 2021-09-07 10:52:44 +08:00
Jukka Laitinen
1b75b5d5aa Fix compilation of arm protected build
Correct typos in include/nuttx/arch.h and suppress
"'noreturn' function does return" warning coming from arm_pthread_exit.c

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-09-07 00:31:47 +08:00
Juha Niskanen
b70ae9ae82 arch/arm/src/stm32l4/stm32l4_flash.c: fix FLASH_CONFIG_I to use dual-bank access
This is currently only used on STM32L4+ devices. Page erase in
flash_erase() function supports only dual-bank mode so it makes little
sense to configure this for unsupported single-bank mode.

Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-09-04 14:31:16 +08:00
Juha Niskanen
508215581f arch/arm/src/stm32l4: fix STM32L4+ option bytes memory address
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-09-03 09:55:54 -03:00
Alin Jerpelea
a20d4ac4ec author: Aleksandr Vyhovanec: update licenses to Apache
Aleksandr Vyhovanec has submitted the ICLA
as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-09-03 17:38:33 +08:00
Xiang Xiao
b05737d78f arch: Replace ar and nm with gcc-ar and gcc-nm
to make enable LTO easily

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-09-02 10:02:14 -03:00
Michal Lenc
1ec0258407 arch/arm/src/imxrt/imxrt_flexcan.c: use SW control to check free MBs
CAN_ESR2 register was having problems of havng the correct values when
the bus was busy (with 3 and more nods). The register bit fields were
incorrectly indicating that there is no free MB and would not updated
itself from this state which was causing the applications to freeze on
write. This change relies only on a software control which should avoid
the problems described above.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-08-31 14:47:41 -03:00
Oleg
e95f23ef8b arch/arm/stm32f7/stm32_irq: Fix format strings 2021-08-31 16:56:55 +08:00
Xiang Xiao
b0c782255c libxx: Change CXX_LIBSUPCXX to LIBSUPCXX
align with other Kconfig(e.g. LIBCXXABI, LIBCXX, UCLIBCXX)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-28 17:14:48 -03:00
Xiang Xiao
f0001574ed arch/armv8-m: Update per the latest architecture reference manual
https://developer.arm.com/documentation/ddi0553/latest

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-27 11:39:27 +02:00
chao.an
bcce3314e5 arch/arm/cortex-m: add up_backtrace support
add up_backtrace support based on push/branch instruction

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-26 18:31:51 +08:00
chao.an
d5d6297ca1 arch/arm/assert: enhance the assert dump
show the all tasks info including backtrace and registers

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-26 13:31:08 +08:00
chao.an
f14bd44001 arch/armv7: add up_backtrace support based on frame pointer
This feature depends on frame pointer, "-fno-omit-frame-pointer" is mandatory

This feature can not be used in THUMB2 mode if you are using GCC toolchain,
More details please refer:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92172

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-26 13:30:08 +08:00
ligd
f1aec38ffa arm: add ARM_HAVE_NEON to Kconfig
Change-Id: I112037aa15a6fae76cf4b7c2df10a42899c38a61
Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-08-26 13:25:43 +08:00
Abdelatif Guettouche
5ff703d5d0 arch/*_testset: Fix few typos.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-25 00:20:20 +08:00
Alin Jerpelea
07d528fd8d license: Ken Pettit: update licenses to Apache
Ken Pettit is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-08-23 11:41:41 +08:00
chao.an
6cfb132232 arch/cortex-m: replace arm_switchcontext to c-style
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-22 14:44:01 +08:00
Xiang Xiao
af72376773 fs: Remove magic field from partition_info_s
since it is wrong and impossible to return file
system magic number from the block or mtd layer.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-20 09:19:52 -03:00
Xiang Xiao
4b41579ccf arch/armv8-m: Add SAU support
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-20 10:22:43 +09:00