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Author SHA1 Message Date
Gregory Nutt
2eb526253b Rename ARMv7-A cache.h to cp15_cache.h. Things will be broken on this commit until I get the new cache.h in place. 2014-07-26 16:54:19 -06:00
Gregory Nutt
6d9ca195ee arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig: Add initiali support for the ARM L2CC-PL310 L2 cache. 2014-07-26 16:50:08 -06:00
Gregory Nutt
fcbf89c6f6 ARMv7-A: L2CC PL310 address filtering is an optional feature 2014-07-25 19:46:09 -06:00
Gregory Nutt
a007fa3f5e ARMv7-A: Add missing L2CC PL310 bit definitions 2014-07-25 19:41:35 -06:00
Gregory Nutt
e74f37445b rch/arm/armv7-a/l2cc_pl310.h: Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h. Adjust the two corresponding Kconfig files as well. 2014-07-25 17:25:17 -06:00
Gregory Nutt
2ec0ab3b5e 3rd time is a charm. Max is right, the initial priority setting should be NVIC_SYSH_PRIORITY_MIN 2014-07-24 16:51:07 -06:00
Gregory Nutt
1366ce0a02 Oops, should have been NVIC_SYSH_PRIORITY_DEFAULT 2014-07-24 16:42:15 -06:00
Gregory Nutt
a3d20b2fa1 LPC17 Ethernet: Added option to use the kernel worker thread to do most of the workload with CONFIG_NET_WORKER_THREAD option in Kconfig. Eliminated a problem with PHY DP83848C : it doesn't need a specific initialization on mbed. Critical bufix: From time to time (after some hours) the Ethernet receiver would lose one receive interrupt and the IP stack never recover because there is no receive watchdog as the transmit watchdog. From Max 2014-07-24 16:39:18 -06:00
Gregory Nutt
dd74e75d1e Added burstmode ADC conversion mode, with CONFIG_ADC_BURSTMODE option in Kconfig. From Max 2014-07-24 16:23:31 -06:00
Gregory Nutt
21d67c5b1b Mostly cosmetic changes from Max 2014-07-24 16:00:21 -06:00
Gregory Nutt
43a578d2d3 Eliminate warnings. From Max 2014-07-24 15:50:37 -06:00
Gregory Nutt
5e19807250 Correct the initial value of the BASEPRI register. This was apparently never being initialized. From Max 2014-07-24 15:37:13 -06:00
Gregory Nutt
949e002d76 Fix a recently introduced typo that was being masked by some bad conditional compilation 2014-07-22 11:45:14 -06:00
Gregory Nutt
d57c3b4e82 Update ChangeLog 2014-07-22 07:25:01 -06:00
Gregory Nutt
45c03e5a1a STM32 OTGFS device: Various changes to try to reduce that amount of time in interrupts handles and with interrupts disbled. Needs verification on other platforms. From Petteri Aimonen 2014-07-22 07:23:17 -06:00
Gregory Nutt
615b7d6c7a Fix typos in the STM32 DAC header file. From Petteri Aimonen 2014-07-22 07:13:33 -06:00
Gregory Nutt
af8f5f4bdc SAMA5D4 XDMAC: Never sets a channel as secure. Will probably have to revisit this 2014-07-21 17:46:35 -06:00
Gregory Nutt
4ce2e094ba SAMA5D4: Fix some HSMCI issues when XDMAC0 is enabled 2014-07-21 17:45:48 -06:00
Gregory Nutt
80c0b5628d SAMA5 HSMCI: Correct multi-block DMA setup; Fixes related to DMA timeout. Still problems with HSMCI DMA via XDMAC 2014-07-21 16:49:56 -06:00
Gregory Nutt
519c8f3e97 SAMA5 XDMAC: Missing some CUBC bits 2014-07-21 16:47:16 -06:00
Gregory Nutt
2d69c2f519 SAMA4D5 HSMCI: Set burst size to 1, sample DMA registers on timeout, and don't return from transfer until BOTH the HSMCI transfer and DMA complete 2014-07-21 13:24:55 -06:00
Gregory Nutt
c5b58b189c XDMAC register sampling missed CIM register; Should not set SWREQ bit in DMA setup 2014-07-21 13:23:36 -06:00
Gregory Nutt
35ea8f1542 Fix a commented out assertion 2014-07-20 17:06:55 -06:00
Gregory Nutt
b207138be9 Fix typos in comments 2014-07-20 13:09:47 -06:00
Gregory Nutt
7ba2d9ed36 SAMA5D4-EK: PIO Schmitt trigger logic backward 2014-07-20 13:04:30 -06:00
Gregory Nutt
9392953ea1 WM8904 w/NxPlayer: Fix some compile errors and warnings with debug enabled 2014-07-20 09:17:36 -06:00
Gregory Nutt
7c56185006 SAMA5D ADC: Fix some typos in conditional compilation 2014-07-19 13:56:48 -06:00
Gregory Nutt
3c29703c42 SAMA5 SCK: The SAMA5D3 does things a little differently 2014-07-19 13:55:53 -06:00
Gregory Nutt
e82143ac38 SAMA5 PCK: Add support for the slow clock as the PCK clock source 2014-07-19 13:55:08 -06:00
Gregory Nutt
8986bd3976 SAMA5: Update slow clock logic. Things work a little differently on the SAMA5D3 2014-07-19 13:25:59 -06:00
Gregory Nutt
813eade679 SAMA5: Add slow clock support 2014-07-19 13:07:55 -06:00
Gregory Nutt
c7055a4cb8 SAMA5D4-EK: Add WM8904 initialization logic 2014-07-19 11:58:53 -06:00
Gregory Nutt
8055a59d49 SAMA5 LCDC: Back out the delay kludge. Increase the LCDC input clock from MCK to 2*MCK was sufficient for all timing instbility problems 2014-07-12 11:24:14 -06:00
Gregory Nutt
424d47cfee SAMA5D4-EK LCDC: Change source clock to 2*Mck seems to solve stability issues 2014-07-12 09:45:05 -06:00
Gregory Nutt
30603b1021 SAMA5D4-EK LCDC: Adding a delay after enabling the LCD solves lots of start-up timing issues 2014-07-12 08:05:22 -06:00
Gregory Nutt
20493f1212 Lpc17xx Ethernet: Comment out an assertion that is reported to first inappropriately. From Max 2014-07-11 12:25:11 -06:00
Gregory Nutt
67468408ae SAMA5D4-EK LCD: Actual hardware with appears to be RGB888 2014-07-10 12:23:41 -06:00
Gregory Nutt
c7d53cb927 SAMA5D4-EK: LCDC works (with a few color problems) 2014-07-10 12:03:10 -06:00
Gregory Nutt
6563ae07c2 Don't have to set SDA high initially in I2C reset because that is done by the pin configuration 2014-07-09 17:17:32 -06:00
Gregory Nutt
fc973eb512 SAMA5 PIO: Fix a typo in Schmitt trigger configuration; Configure pin as a a vanilla input first so that final pin configuration is more read-able (i.e., easier to debug) 2014-07-09 17:16:43 -06:00
Gregory Nutt
0d4255257d SAMA5 I2C Reset: More changes... still does not work right 2014-07-09 15:09:06 -06:00
Gregory Nutt
c1ca11331d SAMA5 TWI: Some restructured needed by up_i2creset. Also timeout needs to vary with the size of the transfer and if debug is on or not 2014-07-09 13:39:10 -06:00
Gregory Nutt
ee351dc695 Use sam_pio_forceclk() so that we can read the current state of an open-drain output in the TWI reset logic. 2014-07-09 11:31:21 -06:00
Gregory Nutt
c4b9eaa01f Add a new interface sam_pio_forceclk() that can be used to force PIO clocking on. I am afraid I was too conservative with PIO clocking in the initial design; this is the price 2014-07-09 11:26:07 -06:00
Gregory Nutt
6c4f57b0dc SAMA5 TWI: Add support for up_i2creset 2014-07-09 09:51:28 -06:00
Gregory Nutt
446d9daa94 SAMA5D4 LCDC: Adapt the SAMA5D3 LCDC driver to work with the SAMA5D4 which has no hardware cursor 2014-07-08 12:45:16 -06:00
Gregory Nutt
8bc8a86b90 SAMA5D3/4 HEAP: Add a configuration option to reserve DRAM for a framebuffer when executing out of DRAM. 2014-07-08 12:43:38 -06:00
Gregory Nutt
3fe95f83de Fix some cloned errors in SAM GPIO interrupt setup 2014-07-07 15:54:37 -06:00
Gregory Nutt
14c90921b3 SAMA5D3/4: Fix two issues associated with PIO interrupts 2014-07-07 14:16:29 -06:00
Gregory Nutt
ae95f4e4d2 SAMA5D3/4 I2C: Test for read or write operation was reversed. How could this have worked before? 2014-07-07 09:54:43 -06:00