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d4963c2580
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9995 Commits

Author SHA1 Message Date
David Sidrane
d4963c2580 Merged in david_s5/nuttx/upstream_upstream_kinetis_usb (pull request #226) 
kinetis usb clean up

Approved-by: Gregory Nutt
 2017-02-28 00:54:04 +00:00
David Sidrane
0b637ddfb3 Kinetis:Define uart and lpuart versions of [early]serialinit 
Add serial init to centralize UART/LPUART management
   Use kinetis_ not up_ where arch specific
   Defined kinetis_[lp]uart_[early]serialinit to facilitate
    bring up both UARTs and LPUARTs as devices and a console

   Support ordering and merging of serial devices names.
 2017-02-27 14:27:31 -10:00
David Sidrane
d0c58fffb3 Kinetis:Refactor clocking in kinetis_usbdev 
1) Removed SIM_CLKDIV2[USBFRAC, USBDIV] setting as it is now
     done in kinetis_clockconfig
  2) Use BOARD_USB_CLKSRC to select the clock source to the
     USB block
  3) Removed warning
  4) Removed CONFIG_TEENSY_3X_OVERCLOCK from the driver as
     the board.h will now provide BOARD_SIM_CLKDIV2_USBDIV
     and BOARD_SIM_CLKDIV2_USBFRAC to the kinetis_clockconfig
 2017-02-27 13:13:24 -10:00
David Sidrane
1c518b223d Kinetis:Add the configuring SIM_CLKDIV2[USBFRAC, USBDIV] in kinetis_clockconfig 
If a board.h provides BOARD_SIM_CLKDIV2_FREQ it will configure the
  SIM_CLKDIV2 based on the additional provided
  BOARD_SIM_CLKDIV2_USBFRAC and BOARD_SIM_CLKDIV2_USBDIV

  The reason for doing this globaly is that the output the
  SIM_CLKDIV2 divisor may be also used for other IP blocks in
  future configurations (as is done for SIM_CLKDIV3)
 2017-02-27 13:06:01 -10:00
David Sidrane
b9dcedf289 Kinetis:Fixed unused warning 2017-02-27 11:22:49 -10:00
David Sidrane
4bdf732fc7 Kinetis:Fixed kinetis_uartreset call in kinetis_lpserial.c 2017-02-27 11:22:49 -10:00
David Sidrane
3ae4183971 Kinetis:Fixed C&P of stm32 on kinetis_fpuconfig 2017-02-27 09:12:39 -10:00
David Sidrane
ddb00217be Kinetis:Fixed up_rxint - did not disable the RX interuppts 
There was an OR where and AND NOT was needed.
 2017-02-27 07:19:19 -10:00
Gregory Nutt
433ed93aa0 Add some comments. 2017-02-27 06:25:31 -06:00
Gregory Nutt
1ed7bec85f Merge branch 'master' of bitbucket.org:nuttx/nuttx 2017-02-26 14:53:48 -06:00
Gregory Nutt
bca0adec2b Update comments in file headers. 2017-02-26 14:40:57 -06:00
Wolfgang Reißnegger
774346ccdd SAM3/4: GPIO bit numbering typo fixes. 2017-02-26 09:54:04 -08:00
Gregory Nutt
2e0ffc0ea3 Update some comments. 2017-02-26 09:15:57 -06:00
raiden00pl
3175b74428 Add basic support for the STM32F334 2017-02-26 12:39:44 +01:00
Gregory Nutt
2238912507 Fix some backward conditional compilation 2017-02-25 18:32:58 -06:00
Gregory Nutt
abfb070ee1 Kinetis: Try to make UART/LPUART definitions sane. 2017-02-25 17:48:05 -06:00
Gregory Nutt
27cac7f083 Fix error in last commit: defined, not define in conditional logic. 2017-02-25 16:44:27 -06:00
Gregory Nutt
1e1714b061 Kinetis: Resolve issue with duplicate definitions of up_putc. Addition conditional logic to pick just one. 2017-02-25 16:36:47 -06:00
Gregory Nutt
b6f5b77f2c Add C files that reference ANIOC_TRIGGER now need to include nuttx/analog/ioctl.h 2017-02-25 15:54:10 -06:00
Gregory Nutt
ee2f71ad3e Kinetis USBDEV: Eliminate compilation error introduced by last SIM changes. 2017-02-25 13:26:53 -06:00
Gregory Nutt
48bc77ee6b Update some comments. 2017-02-25 12:40:30 -06:00
Gregory Nutt
04ea69c32f Kinetis: Fix some comple errors and warnings that came in with the last PR 2017-02-25 11:52:31 -06:00
Gregory Nutt
90e63ba18e Purely cosmetic changes from review of last PR. 2017-02-25 11:43:05 -06:00
David Sidrane
38df949adc Merged in david_s5/nuttx/upstream_kinetis (pull request #221) 
Kinetis:Add LPUART

Approved-by: Gregory Nutt
 2017-02-25 17:23:04 +00:00
Gregory Nutt
d77d322a61 QEncoder: Add mechanism to assure that architecture-specific IOCTL commands do not overlap. 2017-02-25 11:15:59 -06:00
David Sidrane
df01e343a7 Kinetis:Add LPUART serail device driver 2017-02-25 07:06:04 -10:00
David Sidrane
0cbc03255c Kinetis:Add LPUART and Clock configuartaion to freedom-k66f board 
Pin out LPUART0 for testing
   Define BOARD_SOPT2_PLLFLLSEL ti select MCGPLLCLK
   Define BOARD_SIM_CLKDIV3_FREQ etal to provide BOARD_LPUART0_FREQ
 2017-02-25 07:05:34 -10:00
David Sidrane
b553d34a68 Kinetis:Added configurable 1|2 stop bits 
HAVE_SERIAL_CONSOLE -> HAVE_UART_CONSOLE to bew consistent with
  HAVE_LPUART_CONSOLE naming
 2017-02-25 07:02:56 -10:00
David Sidrane
dd218ffa8c Kinetis:Extend clockconfig to support SOPT2_PLLFLLSEL and SIM_CLKDIV3 
A board.h file can now specify the:
   1) BOARD_SOPT2_PLLFLLSEL to select the output of the SIM_SOPT2 MUX
     from:
       MCGFLLCLK
       MCGPLLCLK
       USB1PFD
       IRC48MHZ

    2) If it defines BOARD_SIM_CLKDIV3_FREQ then it must define
    BOARD_SIM_CLKDIV3_PLLFLLFRAC and BOARD_SIM_CLKDIV3_PLLFLLDIV
    which wil be used to cpnfigure SIM_CLKDIV3 [PLLFLLFRAC, PLLFLLDIV]
 2017-02-25 07:02:56 -10:00
David Sidrane
86c9f97f78 Kinetis: Add LPUART as lowlevel console 2017-02-25 07:02:56 -10:00
David Sidrane
29ab603a66 Kinetis:Add LPUART for use with K66 
Add LPUART made UART5 an uption as the K66 does not have UART5
 2017-02-25 07:02:56 -10:00
David Sidrane
61b10c5e58 Kinetis:Add LPUART to K66 chip 
Add KINETIS_NLPUART setting it to 1 and adjust KINETIS_NUART
  to removed UART5 as the K66 dioes not have UART5
 2017-02-25 07:02:56 -10:00
David Sidrane
f6fe9beeb3 Kinetis:Add LPUART to config 2017-02-25 07:02:56 -10:00
David Sidrane
b280aef9c0 Kinetis:Add LPUART register definitions 2017-02-25 07:02:38 -10:00
David Sidrane
9061a3fb64 Kinetis: UART add UART_BDH_SBNS definition 2017-02-25 07:02:38 -10:00
Gregory Nutt
de0e2ec261 STM32: Remove one residual use of the obsoleted STM32_TIM27_FREQUENCY definition which does not work for all STM32 family members. 2017-02-25 10:04:28 -06:00
Gregory Nutt
4c6b635298 Fix error in previous commit. 2017-02-25 09:39:33 -06:00
Gregory Nutt
c694ca0ebc Enable clocking to the timer on QE setup; disable clock on QE teardown. 2017-02-25 09:26:11 -06:00
Alan Carvalho de Assis
37298504e6 Fix QEncoder driver, based on STM32L4 driver 2017-02-24 16:10:28 -06:00
Gregory Nutt
8ee2e8d8b0 Most Ethernet drviers: Check if the poll timer is running before restarting it at the end of each TX. 2017-02-24 15:58:17 -06:00
Marc Rechte
579360e77d Merge branch 'master' of https://bitbucket.org/mrechte/nuttx-twrk64 2017-02-24 08:02:08 +01:00
Marc Rechte
c734a6283c kinetis_enet.c add #define for number of loops for auto negotiation to complete 2017-02-24 08:00:11 +01:00
David Sidrane
a43554decd Kinetis:SIM add paramiterized SIM_CLKDIVx_xxFRAC|DIV macros 
The makes for cleaner board definitions like:

   Divider output clock = Divider input clock * ((PLLFLLFRAC+1)/(PLLFLLDIV+1))
       SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ × [ (PLLFLLFRAC+1) / (PLLFLLDIV+1)]
                 90 Mhz = 180 Mhz X [(0 + 1) / (1 + 1)]
    #define BOARD_SIM_CLKDIV3_PLLFLLFRAC  1
    #define BOARD_SIM_CLKDIV3_PLLFLLDIV   2
    #define BOARD_SIM_CLKDIV3_FREQ        (BOARD_SOPT2_FREQ * (BOARD_SIM_CLKDIV3_PLLFLLFRAC / BOARD_SIM_CLKDIV3_PLLFLLDIV))
 2017-02-23 19:27:55 -10:00
David Sidrane
e1278c0cb9 Kinetis:Fix typo in comment 2017-02-23 19:25:53 -10:00
Gregory Nutt
207b4a3c68 Update README.txt 2017-02-23 11:02:06 -06:00
Gregory Nutt
d83422a00d Update README.txt 2017-02-23 10:57:21 -06:00
David Sidrane
41e3d9f174 Kinetis:Refactor you use SIM_SOPT2_PLLFLLSEL, added warning 
The warning has been added because: SIM_SOPT2_PLLFLLSEL
  is a clock selection that may feed many clock subsystem:
   USB, TPM, SDHCSRC, LPUARTSRC. Therefore, there needs to
  be a global board level setting to select  the source for
  SIM_SOPT2_PLLFLLSEL and then  derive all the  sub selections
  and proper fractions/divisors for each modules clock.
 2017-02-22 10:42:52 -10:00
David Sidrane
12c24f2644 Kinetis:kinetis_clockconfig uses the correct ACKISO 
ACKISO is located in the PMC_REGSC on the majority
   of the Kinetis SoCs. With the exception of the
   MK40DXxxxZVLQ10 where ACKISO is located in LLWU_CS
 2017-02-22 10:42:52 -10:00
David Sidrane
1324b8c00a Kinetis:Resolves issues where Freescale moved ACKISO 
ACKISO is located in the PMC_REGSC on the majority
  of the Kinetis SoCs. With the exception of the
  MK40DXxxxZVLQ10 where ACKISO is located in LLWU_CS
 2017-02-22 10:42:52 -10:00
David Sidrane
a4b985f865 Kinetis:PMC defines are based on PMC feature configuration 2017-02-22 10:42:52 -10:00