sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
42,628 Commits 1 Branch 0 Tags 291 MiB
d4e59b7e8d
Commit Graph

13642 Commits

Author SHA1 Message Date
Harri Luhtala
d4e59b7e8d arch/arm/src/stm32l4: add control for Vddio2 independent I/Os supply valid 
Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
 2021-09-09 08:26:08 -03:00
YAMAMOTO Takashi
58bdcbab9b Revert "Make: use gcc as LD" 
This reverts commit 45672c269d.

Because:

* It's very confusing to have cc as LD.
* I don't see what "-nostartfiles -nodefaultlibs" in LDFLAGS are
  supposed to do when we use LD directly. It would be simpler to
  remove them from our LDFLAGS.
 2021-09-08 09:40:48 +08:00
Jari van Ewijk
5f63fa391f Fix error in s32k118_pinmux.h 2021-09-07 17:34:19 -07:00
YAMAMOTO Takashi
5ad1cba338 Revert "arch: Replace ar and nm with gcc-ar and gcc-nm" 
This reverts commit b05737d78f.

Because it broke clang-based builds.
 2021-09-07 10:54:15 +08:00
Fotis Panagiotopoulos
eb48a0dbe0 Fix in STM32_UART8 Kconfig. 2021-09-07 10:52:44 +08:00
Jukka Laitinen
1b75b5d5aa Fix compilation of arm protected build 
Correct typos in include/nuttx/arch.h and suppress
"'noreturn' function does return" warning coming from arm_pthread_exit.c

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-09-07 00:31:47 +08:00
Juha Niskanen
b70ae9ae82 arch/arm/src/stm32l4/stm32l4_flash.c: fix FLASH_CONFIG_I to use dual-bank access 
This is currently only used on STM32L4+ devices. Page erase in
flash_erase() function supports only dual-bank mode so it makes little
sense to configure this for unsupported single-bank mode.

Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-09-04 14:31:16 +08:00
Juha Niskanen
508215581f arch/arm/src/stm32l4: fix STM32L4+ option bytes memory address 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-09-03 09:55:54 -03:00
Alin Jerpelea
a20d4ac4ec author: Aleksandr Vyhovanec: update licenses to Apache 
Aleksandr Vyhovanec has submitted the ICLA
as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-09-03 17:38:33 +08:00
Xiang Xiao
b05737d78f arch: Replace ar and nm with gcc-ar and gcc-nm 
to make enable LTO easily

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-02 10:02:14 -03:00
Michal Lenc
1ec0258407 arch/arm/src/imxrt/imxrt_flexcan.c: use SW control to check free MBs 
CAN_ESR2 register was having problems of havng the correct values when
the bus was busy (with 3 and more nods). The register bit fields were
incorrectly indicating that there is no free MB and would not updated
itself from this state which was causing the applications to freeze on
write. This change relies only on a software control which should avoid
the problems described above.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-08-31 14:47:41 -03:00
Oleg
e95f23ef8b arch/arm/stm32f7/stm32_irq: Fix format strings 2021-08-31 16:56:55 +08:00
Xiang Xiao
b0c782255c libxx: Change CXX_LIBSUPCXX to LIBSUPCXX 
align with other Kconfig(e.g. LIBCXXABI, LIBCXX, UCLIBCXX)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-28 17:14:48 -03:00
Xiang Xiao
f0001574ed arch/armv8-m: Update per the latest architecture reference manual 
https://developer.arm.com/documentation/ddi0553/latest

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-27 11:39:27 +02:00
chao.an
bcce3314e5 arch/arm/cortex-m: add up_backtrace support 
add up_backtrace support based on push/branch instruction

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-26 18:31:51 +08:00
chao.an
d5d6297ca1 arch/arm/assert: enhance the assert dump 
show the all tasks info including backtrace and registers

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-26 13:31:08 +08:00
chao.an
f14bd44001 arch/armv7: add up_backtrace support based on frame pointer 
This feature depends on frame pointer, "-fno-omit-frame-pointer" is mandatory

This feature can not be used in THUMB2 mode if you are using GCC toolchain,
More details please refer:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92172

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-26 13:30:08 +08:00
Abdelatif Guettouche
5ff703d5d0 arch/*_testset: Fix few typos. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-25 00:20:20 +08:00
Alin Jerpelea
07d528fd8d license: Ken Pettit: update licenses to Apache 
Ken Pettit is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-23 11:41:41 +08:00
chao.an
6cfb132232 arch/cortex-m: replace arm_switchcontext to c-style 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-22 14:44:01 +08:00
Xiang Xiao
af72376773 fs: Remove magic field from partition_info_s 
since it is wrong and impossible to return file
system magic number from the block or mtd layer.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-20 09:19:52 -03:00
Xiang Xiao
4b41579ccf arch/armv8-m: Add SAU support 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-20 10:22:43 +09:00
raiden00pl
78962165d8 arch/stm32: add 3-phase Hall effect sensor lower half 2021-08-19 08:19:38 -07:00
raiden00pl
532ec126e9 stm32/stm32_serial.c fix compile error when CONFIG_STM32_SERIALBRK_BSDCOMPAT=y. 
Fix for https://github.com/apache/incubator-nuttx/issues/4353
 2021-08-18 04:43:32 -07:00
Juha Niskanen
e02e1c25f6 arch/arm/src/stm32l4/Kconfig: add new STM32L4+ chip types 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Change-Id: I74050913643db23b4d03abaf516989ff3cdac142
 2021-08-17 06:27:18 -07:00
Alin Jerpelea
351091ed75 author: Pierre-noel Bouteville: update licenses to Apache 
Gregory Nutt has submitted the SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-16 07:11:32 -07:00
Xiang Xiao
71269811ca mtd: Implement BIOC_PARTINFO for all drivers 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-16 10:08:26 -03:00
Xiang Xiao
f63d1cfbbb arch/arm: Add NVIC_FPCCR_XXX macro to avoid the hard code value 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-15 10:50:52 +02:00
Xiang Xiao
fad0c3b38b arch/arm: Add NVIC_CPACR_CP_XXX(n) macro to avoid the hard code value 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-14 11:41:59 -07:00
Xiang Xiao
33666832c5 arch/arm: Add NVIC_AIRCR_VECTKEY macro to avoid the hard code value 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-14 11:41:59 -07:00
Abdelatif Guettouche
5b350f3a0f arch/*_reprioritizertr.c: Fix typos in comments. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-14 11:19:34 -07:00
Alexander Vasiljev
4229099944 arch/arm/stm32h7: dma and serial: add TRBUFF flag. It is obligatory for uart. 2021-08-12 08:07:18 -03:00
Xiang Xiao
6b6c11f0ad mtd: Replace MTDIOC_XIPBASE with BIOC_XIPBASE 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-12 08:01:29 -03:00
Xiang Xiao
d1687418db mtd: Remove the empty MTDIOC_XIPBASE implmentation 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-11 09:50:51 -03:00
Abdelatif Guettouche
054e284785 *_cpustart.c: Fix typos in function description. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-11 11:06:27 +09:00
Fotis Panagiotopoulos
5b7ff03f40 lpc17_40: Fixed I2C port sanity check. 2021-08-10 09:04:33 -07:00
raiden00pl
2b3106fb47 Qencoder implementations for imxrt, stm32f7, stm32h7, stm32l4 and tivia don't support QEIOC_SETPOSMAX 2021-08-10 11:19:05 -03:00
raiden00pl
51b24c4bad stm32/qenco: add support for QEIOC_SETPOSMAX 2021-08-10 11:19:05 -03:00
raiden00pl
092a0c8453 stm32/qenco: add an option to disable encoder timer extension from 16-bit to 32-bit 
Previous implementation has always expanded the width of the timer to 32-bit.
This feature is not always needed and should be configurable from Kconfig.
 2021-08-10 11:18:40 -03:00
raiden00pl
b0c9a6133e stm32/qenco: fix TIM2 width for STM32F3 which is 32-bit not 16-bit 
STM32F3 has timers of the same length as in STM32F4.
 2021-08-10 11:18:40 -03:00
raiden00pl
3dd385ac0c stm32/qenco: add support for STM32G4 
This required generalization of RCC definitions that are not compatible with previous chips
 2021-08-10 11:18:40 -03:00
raiden00pl
21f59c874f stm32/qenco: fix compilation for STM32F1. GTIM_CCER_CCxNP bits are not present in F1 2021-08-10 11:18:40 -03:00
Xiang Xiao
776458143c fs/hostfs: Support fchstat and chstat callback 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-09 17:55:44 -03:00
Xiang Xiao
7e0db977cc arch/arm: Add CONTROL register bit field definition 
and replace all hardcode value

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-07 09:20:10 -03:00
Daniel P. Carvalho
a7be1c9a2e stm32_pmw: fix pwm_stop() function to enable multiple PWM start and stop. 2021-08-05 14:48:44 -03:00
Michal Lenc
a3986eeba3 arch/arm/src/imxrt/imxrt_flexpwm.c: Set LDOK bits after all channels are set 
This commit changes the FLexPWM driver for iMXRT MCU so that LDOK bits in
Master Control Register are set at once after all channels are configured.
Setting LDOK bit enables the driver to load prescaler, modulus and PWM
values of corresponging submodule and start PWM output. Setting all bits
at once instead of doing it separately can help avoiding the channels to
be out of sync with each other.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-08-05 09:57:49 -07:00
Daniel P. Carvalho
2593089f84 stm32_dac: add support for DAC3 2021-08-04 20:22:58 +02:00
Xiang Xiao
6a396eb224 Fix the printf warning after off_t change 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Id46daa2ee690a73d3187b479f0e7ab0e2e361764
 2021-08-04 06:48:30 -07:00
licheng
431df45e97 EXC_SECURE and SECURE_STACK just can clear at TRUSTZONE_NONSECURE 2021-08-02 23:20:34 -07:00
Xiang Xiao
5d1a444812 Replace __attribute__ ((unused)) with unused_code 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00