To avoid build break:
ld: riscv-none-elf/lib/rv64imafdc_zicsr/lp64d/crt0.o: in function `.L0 ':
(.text+0x8): undefined reference to `__bss_start'
ld: (.text+0x10): undefined reference to `_end'
ld: (.text+0x36): undefined reference to `main'
collect2: error: ld returned 1 exit status
Signed-off-by: chao an <anchao@lixiang.com>
Newly added logging in `sched/task_exit.c` obsoletes the existing
ones in `arch/up_exit()`, thus remove the latter to reduce duplications.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Previously k230 kernel build needs OpenSBI wrapping for use on
target, thus leading to larger program and memory overheads.
This patch adds alternative small overhead kernel build support.
Changes:
- in arch/risc-v/src/k230:
- k230_head.S entrance renamed for sake of NUTTSBI
- k230_irq.c add M-mode handling for NUTTSBI case
- k230_mm_init.c add L3 table for smaller RAM case
- hardware/k230_plic.h add PLIC_CTRL definition
- Make.defs use CHIP_ASRCS to fix entrance selection
- in boards/risc-v/canmv230/scripts:
- Make.defs add support for NUTTSBI case
Additions:
- in boards/riscv/canmv230/:
- scripts/ld-nuttsbi.script link script for NUTTSBI case
- configs/nsbi/defconfig config for NUTTSBI case
The artifact nuttx.bin from this configuration can be used directly
on target as OpenSBI wrapping is not needed.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
fix typo
new options to enable toolchain support for quadruple precision
(128 bits or 16 bytes) floating point if both the toolchain and
the hardware support it.
Signed-off-by: chao an <anchao@lixiang.com>
Some devices have special preparations before entering S-mode, thus
a hook is needed from NUTTSBI to give them the chance.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Chips like K230 has ARCH_RV64 but only supports 32-bit MMIO. So using
ARCH_RV_MMIO_BITS is more proper here.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This is not the right place to modify DMA memory protection values.
Why not? These are designed to protect other AMP mode instances. Opening
the entire SoC's memory for the USB DMA kind of defeats this purpose.
Also, the driver cannot know how to configure these registers correctly,
only opening up the whole SoC "works".
armv8-r/arm_gicv3.c: In function 'gic_validate_dist_version':
armv8-r/arm_gicv3.c:730:9: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=]
730 | sinfo("GICD_TYPER = 0x%x\n", typer);
| ^~~~~~~~~~~~~~~~~~~~~ ~~~~~
| |
| uint32_t {aka long unsigned int}
armv8-r/arm_gicv3.c:730:26: note: format string is defined here
730 | sinfo("GICD_TYPER = 0x%x\n", typer);
| ~^
| |
| unsigned int
| %lx
Signed-off-by: chao an <anchao@lixiang.com>
Fully linked apps take less storage and are efficient to load. This
is to enable them for rv-vrit configurations in KERNEL build.
Changes:
- arch/risc-v/Kconfig select BINFMT_ELF_EXECUTABLE for QEMU-RV
- boards/risc-v/qemu-rv/rv-virt/configs
- knsh32/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
- knsh64/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
- ksmp64/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
- knetnsh64/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
- knetnsh64_smp/defconfig enable ELF_EXECUTABLE, LIBM, OSTEST
Additions:
- boards/risc-v/qemu-rv/rv-virt/scripts/
- gnu-elf.ld apps linker script
The ARCH_TEXT_VBASE of knsh32 is set to same as that of 64bit to reuse
the apps linker script.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Previously apps in kernel build are partially linked, thus are
big and inefficient. This enables full link for kernel mode apps
to reduce size and speed up loading.
Changes:
- arch/risc-v/Kconfig select HAVE_ELF_EXECUTABLE for K230
- boards/../scripts/Make.defs adjust LDELFLAGS
- boards/../knsh/defconfig enable BINFMT_ELF_EXECUTABLE
Additions:
- boards/../scripts/gnu-elf.ld apps linker script
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The RT-Timer thread may call the `start_rt_timer` function. This
function gets the spinlock with interrupts disabled to ensure
exclusive access. However, this was already being performed in the
RT-Timer thread, causing a deadlock.
Following up the 'Espressif HAL fullly integration for ESP32s2/s3'
changes in https://github.com/apache/nuttx/pull/11428
There are few missing interrupt type constants need update. So
update them to avoid the build error.
Usually the startup script is placed under /etc. The contents of the etc directory
are compiled and linked with Nuttx binary in the form of romfs. After startup,
it will be mounted by Nsh.
etc is generated by the different boards, that use genromfs and xxd tools to generate
and compile it into the Nuttx, for example: boards/arm/at32/at32f437-mini/tool/mkromfs.sh
The more common method is etc image generated from the content in the corresponding
board/arch/board/board/src/etc directory, and added by Makefile for example:
boards/sim/sim/sim/src/etc.
But in kernel/protected mode, Nuttx kernel and apps are run in different privileged/
non-privileged mode or the isolated binarys, so as that nsh should use syscall to
access Nuttx kernel by exported API. In this scenario, nsh can not mount the etc image
content, because that is generated in board and as a part of Nuttx kernel.
changes:
- move etc romfs mount from nsh to Nuttx, but keep the script to parse and execute.
- move and rename the related CONFIG, move customized nsh_romfsimg.h to etc_romfs.c
in boards, and no need declaration for romfs_img/romfs_img_len.
This commit changes and updates all configurations in Nuttx arch/board as much as possible,
but if any missing, please refer to the following simple guide:
- rename CONFIG_NSH_ROMFSETC to CONFIG_ETC_ROMFS, and delete CONFIG_NSH_ARCHROMFS in defconfig
- rename the etc romfs mount configs, for example CONFIG_NSH_FATDEVNO to CONFIG_ETC_FATDEVNO
- move customized nsh_romfsimg.h to etc_romfs.c in board/arch/board/board/src and no need
declaration for romfs_img/romfs_img_len.
- delete default nsh_romfsimg.h, if ROMFSETC is enabled, should generate and compile etc_romfs.c
in board/arch/board/board/src.
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
Note: This implementation is a bit more relaxed than what we do for
non-cmake builds. Mainly because I'm not familiar enough with cmake
to mirror what the non-cmake version does.
Current LITEX_LAST_IRQ looks like a typo that blocks compilation of
`arty_a7/knsh` configuration.
This fixes the build but I have no such device for test.
Found it was LITEX_IRQ_LAST before commit #ee84ea3 so likely typo was
introduced by then.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Add ARCH_CHIP_QEMU_TRUSTZONE to enable/disable the TrustZone
support beacause qemu also support enable/disable Arm Security
Extensions: https://qemu-project.gitlab.io/qemu/system/arm/virt.html
when launch.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
The implementation of the RISC-V Timer for BL808 SoC is incomplete. This PR implements the BL808 RISC-V Timer by calling OpenSBI. The code is derived from NuttX for RISC-V QEMU.
The implementation of `up_timer_initialize` with OpenSBI is explained in this article: https://lupyuen.github.io/articles/nim#appendix-opensbi-timer-for-nuttx
Changes:
- Documentation/platforms/risc-v/k230 revised for both modes
- arch/risc-v/include/k230/irq.h add S-mode IRQs
- under arch/risc-v/src/k230 folder:
- Make.defs drop use of k230_exception_m.S
- hardware/k230_clint.h add S-mode defs, revised freq
- k230_head.S unified flat/kernel mode support
- k230_irq.c add S-mode support with debug dump
- k230_mm_init.c revised for K230 S-mode
- k230_start.c revised for flat/s-mode,
- arch/risc-v/src/k230/k230_timerisr.c unified flat/s-mode support.
- under boards/risc-v/k230/canmv230 folder:
- configs/nsh/defconfig fix RAM size
- include/board_memorymap.h cleanup for S-mode
- src/.gitignore ignore romfs_boot.c
- src/Makefile add romfs support
Renames:
- under boards/risc-v/k230/canmv230/src/ folder:
- canmv_init.c from k230_appinit.c making room for more k230 devices
Dropped:
- under arch/risc-v/src/k230/
- k230_exception_m.S as hybrid mode not ready yet.
New files in boards/riscv/k230/canmv230:
- configs/knsh/defconfig S-mode config
- scripts/ld-kernel.script S-mode linker script
- src/romfs.h User space ROMFS defs needed in S-mode
- src/romfs_stub.c Stub ROMFS image
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
hostfs has its copies of some of nuttx definitions with different
names to avoid conflicting with the host OS definitions.
sometimes people only modifies one of them and forgets updating
another. eg. https://github.com/apache/nuttx/pull/11445
this commit introduces some assertions to detect that kind of
mistakes.
This is to align with ARCH_KMAP_VBASE by source codes.
It also fixes fake warnings from `tools/refresh.sh`.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
By integrating the Espressif`s HAL repository into the current
ESP32-S2 implementation on NuttX, it is possible to call functions
that makes it easier to setup the registers of the ESP32-S2,
enabling the usage of common Espressif drivers.
By integrating the Espressif`s HAL repository into the current
ESP32-S3 implementation on NuttX, it is possible to call functions
that make it easier to set up the registers of the ESP32-S3 and
enables the usage of common Espressif drivers. Please note that
Espressif's HAL repository was already being used for the Wi-Fi
driver. Then, this commit includes other source files to be used
by other drivers other than Wi-Fi and reorganize the build process.
This lower-half WS2812 LED driver uses the RMT peripheral of the
Espressif's SoCs to drive the RGB addressable LEDs. Compared to
the SPI-based implementation, it is faster!
The lower-half implementation of the RMT character driver based on
Espressif HAL enables using the RMT peripheral of ESP32, ESP32-S2
and ESP32-S3 as a common xtensa-based Espressif driver.
The RMT packages on Espressif SoCs are 4-byte long and are known as
"items". Please check the Techinal Reference Manual of the chip to
obtain more details.
Summary:
- I noticed that qemu-armv8a:netnsh_smp_hv does not detect
GICv2 on Raspi4B (ubuntu 22.04 server + qemu-8.1.2)
- According to the GIC-400 TRM, it says that the architecture
version can be obtained from GICC_IIDR (See Table 3-7)
- This commit fixes this issue.
Impact:
- Should be none
Testing:
- Tested with qemu-armv8a:netnsh_smp_hv on
- Raspi3B+ (ubuntu 22.04 server + qemu-8.1.2)
- Raspi4B (ubuntu 22.04 server + qemu-8.1.2)
- M1/MacBook Pro 2021 (macOS 13.6 + qemu-8.1.2)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
1. Solve wifi may not work bug for bbpll not lock or not stable when enable RF.
2. Improved timing tuning stability on ESP32-S3.
The root cause of the issue:
The application won't re-calibrate the BBPLL clock if it's already enabled.
We add a force-recalib function in the app startup code to make sure even if
the patch is applied by OTA, the clock is still re-calibrated.
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
since gcc report the false alarm if the pointer offset from zero address:
inlined from 'up_vectormapping' at chip/dm320_boot.c:162:7,
inlined from 'arm_boot' at chip/dm320_boot.c:211:3:
Error: chip/dm320_boot.c:117:17: error: array subscript 0 is outside array bounds of 'uint32_t[0]' {aka 'long unsigned int[]'} [-Werror=array-bounds=]
117 | ctable[index] = (paddr | mmuflags);
| ~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
The opening and closing of the window has been associated with the opening and closing of fb, but the LCD has not yet been optimized. The window will only open when sim_x11openwindow is called, and similarly, the window will only close when sim_x11closewindow is called.
Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
The code is mainly derived from the NuttX qemu-rv/rv-virt codebase.
Major changes:
- boards/Kconfig: add new BOARD_K230_CANMV
- arch/risc-v/Kconfig: add new CHIP_K230 chip and ARCH_RV_MMIO_BITS
- arch/risc-v/src/common/riscv_mtimer.c: use ARCH_RV_MMIO_BITS to
select MMIO access width
New additions:
- arch/risc-v/include/k230/: k230 SoC definitions
- arch/risc-v/src/k230/: k230 SoC sources
- boards/risc-v/k230/canmv230/: CanMV-K230 board sources and configs
- Documentation/platforms/risc-v/k230/: simple doc
Note that only FLAT build works for canmv230 now.
This PR has changes in RiscV common layer thus may affect other RiscV ports
It changes the mtime/mtimecmp access control from using config ARCH_RV64 to
newly intorduced config ARCH_RV_MMIO_BITS.
Original design uses ARCH_RV64 to select 64bit MMIO in riscv_mtimer.c, this
can't cope with the situation with K230 --- it has ARCH_RV64 but only can do
32bit MMIO. So a new ARCH_RV_MMIO_BITS config has been introduced. Its value
depicts the MMIO width in bits. The MMIO_BITS defaults to 32/64 for RV32/
RV64 respectively. This allows the macro to replace current use of ARCH_RV64
in riscv_mtimer.c.
The new MMIO_BITS config is a derived one, and for RiscV chips with
equal CPU and MMIO widths there is no need to explicitly set it as the
default rule will do that. Only chips with different CPU and MMIO widths
need set it in Kconfig.
So by design this change should be safe but RiscV ports should be checked.
"ostest" verification has been done for:
- canmv230/nsh
- rv-vivt/nsh
- rv-virt/nsh64
configuration generation and manual check of derived RV_MMIO_BITS has been
done for:
- star64/nsh
- arty_a7/nsh
- bl602evb/nsh
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The `xxx_ipv6multicast` function in each driver is not adapted to
multiple IPv6 addresses yet, and they're redundant, so try to take them
into common code.
Change:
1. Add MAC `g_ipv6_ethallnodes` and `g_ipv6_ethallrouters` in
`icmpv6_devinit` and call them in `netdev_register`
2. Add multicast MAC for Neighbor Solicitation when adding any IPv6
address, and remove them when IPv6 address is removed
3. Select `NET_MCASTGROUP` when `NET_ICMPv6` because now we need
`d_addmac` when we have ICMPv6
Note:
We want modules outside net stack to call functions like
`netdev_ipv6_add` and never touch the related MAC address, so these MAC
functions are added as internal functions to `net/netdev/netdev.h`
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
DMA directly to user (virtual) memory won't work, as the DMA engine(s)
don't do address translations, i.e. they require a physical address.
Using kernel heap is fine as it is mapped vaddr=paddr. Also, the USB DMA
engine does not have any alignment requirements.
The hack just opens the entire SoC memory unconditionally, which is not
a good idea.
Test features can be used ad-hoc, they don't need to be supported by the
build.
There is a problem with the current elf loader for risc-v: when a pair of
PCREL_HI20 / LO12 relocations are encountered, it is assumed that these
will follow each other immediately, as follows:
label:
auipc a0, %pcrel_hi(symbol) // R_RISCV_PCREL_HI20
load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S
With this assumption, the hi/lo relocations are both done when a hi20
relocation entry is encountered, first to the current instruction (addr)
and to the next instruction (addr + 4).
However, this assumption is wrong. There is nothing in the elf relocation
specification[1] that mandates this. Thus, the hi/lo relocation always
needs to first fixup the hi-part, and when the lo-part is encountered, it
needs to find the corresponding hi relocation entry, via the given "label".
This necessitates (re-)visiting the relocation entries for the current
section as well as looking for "label" in the symbol table.
The NuttX elf loader does not allow such operations to be done in the
machine specific part, so this patch fixes the relocation issue by
introducing an architecture specific cache for the hi20 relocation and
symbol table entries. When a lo12 relocation is encountered, the cache
can be consulted to find the hi20 part.
[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
The macro LOG2_CEIL is intended to be used in the pre-processor phase. If
used run-time it will generate a massive amount of extra code (~3.5K) which
is a problem, as the PMP configuration is quite often executed from a first
stage bootloader with a limited amount of code memory.
Code size differences pre- and post:
Memory region Used Size Region Size %age Used
envm: 112064 B 112384 B 99.72%
Memory region Used Size Region Size %age Used
envm: 108952 B 112384 B 96.95%
This PR adds support for the Bouffalo Lab BL808 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for PINE64 Ox64 SBC.
Most of the code was derived from NuttX for Star64 JH7110. The UART Driver was derived from BL602 NuttX. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64
`Kconfig`: Added ARCH_CHIP_BL808 for BL808 SoC
`include/bl808/chip.h`: BL808 Definitions
`include/bl808/irq.h`: External Interrupts
`src/bl808/chip.h`: Interrupt Stack Macro
`src/bl808/bl808_allocateheap.c`: Kernel Heap
`src/bl808/bl808_head.S`: Linux Header and Boot Code
`src/bl808/bl808_irq.c`: Configure Interrupts
`src/bl808/bl808_irq_dispatch.c`: Dispatch Interrupts
`src/bl808/bl808_memorymap.h`: Memory Map
`src/bl808/bl808_mm_init.c`, `bl808_mm_init.h`: Memory Mgmt
`src/bl808/bl808_pgalloc.c`: Page Allocator
`src/bl808/bl808_serial.c`, `bl808_serial.h`: UART Driver
`src/bl808/bl808_start.c`: Startup Code
`src/bl808/bl808_timerisr.c`: Timer Interrupt
`src/bl808/hardware/bl808_memorymap.h`: PLIC and UART Base Address
`src/bl808/hardware/bl808_plic.h`: PLIC Register Addresses
`src/bl808/hardware/bl808_uart.h`: UART Register Addresses
`src/bl808/Kconfig`: BL808 Config
`src/bl808/Make.defs`: Makefile
Currently RISC-V NuttX supports 32-bit MMU Flags inside a Page Table Entry. This PR extends the MMU Flags to 64-bit, to support T-Head C906 Core and the new RISC-V Svpbmt Extension.
T-Head C906 uses Bits 59 to 63 in a Leaf Page Table Entry to configure the Memory Type: Cacheable / Bufferable / Strongly-Ordered. For the upcoming port of NuttX to PINE64 Ox64 BL808 SBC, we need to set the Memory Type to Strongly-Ordered for I/O Memory, which requires 64-bit MMU Flags.
Details of C906 MMU: https://lupyuen.github.io/articles/plic3#t-head-errata
Newer RISC-V Cores will use the Svpbmt Extension to configure the Memory Type (Cacheable / Strongly-Ordered). Svpbmt uses Bits 61 to 62 in a Leaf Page Table Entry to define the Memory Type. This also requires 64-bit MMU Flags.
Details of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc#svpbmt
Usage:
1. CONFIG_FS_PROCFS_MAX_STACK_RECORD > 0, such as 32,
2. add '-finstrument-functions' to CFLAGS for What you want to check
stack.
3. mount porcfs
4. cat /proc/<pid>/stack will print backtace & size
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.
We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.
Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.
use instrument_register to register entry function and exit function.
They will be called by the instrumented function
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
The ADC peripheral can only support up to
50MHz on rev V silicon and 36MHz on Y silicon.
The existing driver always used no prescaler
and kept boost setting at 0.
The 1170 usage of the GPR registers is to select the
between GPIO{2|3} or CM7_GPIO{2|3} where as the 1060
it selected ports between 1-6,2-7..4-9 and uses
different GPR registers.
For the 1170 we are defaulting to GPIO{2|3} and not
supporting the swtich to CM7_GPIO{2|3}.
Co-authored-by: Jari van Ewijk <jari.vanewijk@nxp.com>
Co-authored-by: David Sidrane <david.sidrane@nscdg.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
imxrt:Kconfig fix formatting
imxrt:usbphy move IMXRT_USBPHY{1|[2]}_BASE to memory map
imxrt:lpspi Fix build breakage from adding 1170
imxrt:Finish 1170 iomux and clockconfig versioning
imxrt:Remove duplicate imxrt_clock{off|all}_lpi2c4
imxrt:pmu remove duplicate dcd non 117x header
imxrt:lpspi Fix unused var warnings
imxrt:lpi2c Fix unused var warnings
imxrt:lowputs Fix unused var warnings
imxrt:imxrt117x_dmamux fix duplicate entries
imxtr:serial Use IOMUX_PULL_{UP|DOWN} and map IOMUX V1 to them
imxrt:MPU Support the 1170
imxrt:dmamux Alias IMXRT_DMAMUX0_BASE as IMXRT_DMAMUX_BASE
imx1170:ccm Alias CCM_CCGR_DMA & CCM_CCGR_SNVS_LP for compatiblity
Author: Peter van der Perk <peter.vanderperk@nxp.com>
IMXRT7 Add LPUART 9/10/11/12 support
Author: David Sidrane <david.sidrane@nscdg.com>
imxrt:1170pinmux Add QTIMER pins
imxrt:1170pinmux Add GPT pins
imxrt:1170pinmux Add FLEXPWM pins
imxrt1170:pinmap Add GPIO_ENET_1G pinning
imxrt:enet Support ENET_1G
imxrt:periphclks rt1170 does not have canX_serial clock
imxrt:flexcan:Layer imxrt_ioctl
imxrt117x:memorymap added CAN3
imxrt:ADC support ver1 and ver2 for imxrt117x
imxrt:imxrt117x_ccm Align timer naming with other imxrt QTIMERn->TIMERn
imxrt:imxrt117x_ccm align CCM names with rt106x
imxrt:XBAR support larger number of selects needed on imxrt1170
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
FlexSPI AHB Region support, PIT rename for compatiblity
imxrt:USB Analog add VBUS_VALID_3V
FlexSPI expand prefetch registers for IMXRT117X
imxrt:Support Initialization of FlexRam without Running from OCRAM
imxrt: ocotp add UNIQUE_ID register definition
imxrt: enet use ocotp unique_id
imxrt: enet fixes for imxrt117x
imxrt: ethernet pinmux sion enable
imxrt:imxrt_periphclk_configure add memory sync
Flush the pipeline to prevent bus faults, by insuring a
peripheral is clocked before being accessed on return from
this function.
imxrt:Restructure gpioN to padmux mapping
imxrt:Add imxrt1170 daisy
imxrt: correct power modes for imxrt117x fixing hang on WFI
imxrt: imxrt117x TCM MPU config
imxrt: FlexRAM clocking DIV0 setup
imxrt: 117x periphclocks wait for status bit
imxrt: iomucx set pad settings correctly and allow reconfiguration
imxrt: enet align buffers 64-byte for optimal performance
Add DSC barriers for write-through cache support
imxrt: imxrt1170 use FlexCAN FD/ECC features
imxrt:iomuxc_ver2 (117x) SD_B1 and DISP_B1 use PULL feild not PUE/PUS
imxrt:Fix 1170 SNVS addressing
imxrt: enet set mii clock after ifdown so that phy keep working
nxstyle fixes
imxrt: preprocessor and include fixes
Fix configs
imxrt1170-evk clean defconfig
Fixes is stuttering output.
The use of the semaphore was causing blocking
on non blocking callers. This ensured that
the TX DAM would be restated, but when it
was switched to trywait in 660ac6, it left
data in the xmit queue unsent.
This solution removes the semaphore and restart
the DMA on completion if there is more data in
the xmit queue to be sent.
chip/sam_emac.c:3754:11: error: 'struct sam_emac_s' has no member
named 'phytype'
3754 | if (priv->phytype == SAMV7_PHY_KSZ8061)
| ^~
make[3]: *** [Makefile:167: sam_emac.o] Error 1
Member phytype is available only if CONFIG_NETDEV_PHY_IOCTL and
CONFIG_ARCH_PHY_INTERRUPT is set.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Fixes stuttering output.
The use of the semaphore was causing blocking
on non blocking callers. This ensured that
the TX DAM would be restated, but when it
was switched to trywait in 8362e314, it left
data in the xmit queue unsent.
This solution removes the semaphore and restart
the DMA on completion if there is more data in
the xmit queue to be sent.
This prevents dma stop operations called of a completion
call back from rentering, the callback and ensures that
the call back will see the idle state.
1. Configurable mapping of virtual address to psram physical address
2. Access SPIRAM memory at high physical address through bank switching
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
Since picolibc used by clang-17 does not provide an implementation of libm,
if you want to use clang, please must specify a libm as an option.
Signed-off-by: chao an <anchao@xiaomi.com>
armv6-m/arm_dumpnvic.c: In function 'arm_dumpnvic':
armv6-m/arm_dumpnvic.c:67:13: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=]
67 | _info(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
armv6-m/arm_dumpnvic.c:67:27: note: format string is defined here
67 | _info(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
| ~~~^
| |
| unsigned int
| %08lx
Signed-off-by: chao an <anchao@xiaomi.com>
chip/stm32_ethernet.c:2014:7: warning: variable 'i' set but not used [-Wunused-but-set-variable]
2014 | int i;
| ^
1 warning generated.
Signed-off-by: chao an <anchao@xiaomi.com>
To avoid losing the first frame, the set_buf needs to excute first. At the same time, imgdata->start_capture should excuted before the imgsensor->start_capture.
Signed-off-by: yaojingwei <yaojingwei@xiaomi.com>
The divider should be rounded to the next full integer to ensure that
the resulting SPI frequency is <= target frequency, i.e. the SPI is
not overclocked.
After this, RISC-V fully supports the kmap interface.
Due to the current design limitations of having only a single L2 table
per process, the kernel kmap area cannot be mapped via any user page
directory, as they do not contain the page tables to address that range.
So a "kernel address environment" is added, which can do the mapping. The
mapping is reflected to every process as only the root page directory (L1)
is copied to users, which means every change to L2 / L3 tables will be
seen by every user.
Replace DEBUGASSERTs with sanity checks. DEBUGASSERT()s are
not necessarily enabled at all, thus risking the functionality
especially in that case. Remove PANICs as well.
Don't enable the ihc irq too early. If enabled, and the master
is already up, the irq is being issued so that the system gets
stuck or is severely slowed down. Master may be already up if
this NuttX hart only is rebooted, for example.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
When setting the essid that contains the special characters (\"'),
we need to add an escape (\) for them.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
Version 1.3.1 is the latest tagged version as of November
the 21st, 2023. This patch prepares the required changes
to make v1.3.1 work.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Adds support for hardware timestamping of received Ethernet packets.
The timestamp is available to applications using socket option SO_TIMESTAMP.
Optionally, the Ethernet PTP timer can be used as system high-resolution RTC.
In this mode it supports fine resolution rate adjustment.
Alternatively other time source for CLOCK_REALTIME can be used, and the
PTP timestamps are converted by sampling the clocks and computing the
difference. This results in a few microseconds of uncertainty.
The halt operation may be causes the raw epread data segment lost, and
usb ep_queue can handle when the usb buffer is full. so remove the
relevant operations.
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
Summary:
- Temporarily disables ARCH_HAVE_FORK for arm64 to address a crash issue,
as detailed in https://github.com/apache/nuttx/pull/9755.
- This is a precautionary measure until a more permanent solution is implemented.
Impact:
- Temporarily limits certain functionalities on arm64,
but necessary to ensure system stability.
Testing:
- Successfully tested on QEMU-8.1.2.
- Note: please apply the changes from https://github.com/apache/nuttx-apps/pull/1962.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
1. If CONFIG_ESP32S3_PHY_INIT_DATA_IN_PARTITION and CONFIG_ESP32S3_SUPPORT_MULTIPLE_PHY_INIT_DATA are enabled,
PHY initialization data (PHY initialization data is used for RF calibration) will be loaded from a partition.
2. The corresponding PHY init data type can be automatically switched according to the country code,
China's PHY init data bin is used by default, country code can be modified through the wapi command: wapi country <ifname> <country code>.
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
If using flow control with a high CTS the thread may be
blocked forever on the second transmit attempt due to waiting
on the txdma semaphore. The calling thread can then never
make progress and release any resources it has taken, thus
may cause a deadlock in other parts of the system.
The implementation differs in behavior from interrupt-driven
TX. It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to
do next.
If using flow control with a high CTS the thread may be
blocked forever on the second transmit attempt due to waiting
on the txdma semaphore. The calling thread can then never
make progress and release any resources it has taken, thus
may cause a deadlock in other parts of the system.
The implementation differs in behavior from interrupt-driven
TX. It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to
do next.
If using flow control with a high CTS the thread may be
blocked forever on the second transmit attempt due to waiting
on the txdma semaphore. The calling thread can then never
make progress and release any resources it has taken, thus
may cause a deadlock in other parts of the system.
The implementation differs in behavior from interrupt-driven
TX. It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to
do next.
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
It also makes the code look more similar to the ESP32-S3 SPI flash
implementation by creating a common `esp32_spiflash_init` that is
responsible to create the SPI flash operation tasks. The function
intended to initialize the SPI flash partions was, then, renamed to
`board_spiflash_init`.
Whenever we enter/leave a critical section, the interrupt status is
saved and, then, restored. However, for the ESP32's BLE adapter,
entering/leaving a critical section is done on separate functions
that need to be registered as a callback.
The status flag was being saved as a global variable. However,
calling nested enter_critical_section would overwrite this global
variable that was storing the previous flag and, when leaving the
last critical section, the restored status would be different from
the one expected. The proposed solution for this issue is to create
a global array to store the interrupt status flags for nested calls.
If using flow control with a high CTS the thread may be blocked forever
on the second transmit attempt due to waiting on the txdma semaphore.
The calling thread can then never make progress and release any
resources it has taken, thus may cause a deadlock in other parts of the
system.
The implementation differs in behavior from interrupt-driven TX and the
STM32F7 TXDMA . It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to do next.
Some APIs are implemented both in common code and CHIP-specific code,
and the link needs to be based on the implementation in CHIP, so move
NUTTX_CHIP_ABS_DIR before common src.
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
Because there is no pre-encoding length of the ssid, the ssid including
the Chinese characters whose length is less than 32 after encoding
cann't be translated.
For example, the ssid name is `word人`. After encoding it is `world\xe4\xba\xba` and will not be decoded.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
These flags are not used in the code.
SERIAL_HAVE_RXDMA and SERIAL_HAVE_TXDMA flags are used instead.
STM32_UART_TXDMA flag is not even defined in Kconfig
Connecting the static page tables to each other was done with the page
table virtual address (riscv_pgvaddr) when the page table physical address
is needed.
I can never remember whether the static page table list contains the
table's physical or kernel virtual address.. Add the fact as a comment
there.
Also add the limitations that come from this static page table approach
for Sv32.
The SSID can be configured with special symbols suach as single
quotations, double quotations and backslashes, which need to be escaped.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
This adds option to do PMP configuration via mpfs_board_pmp_setup instead
of just opening up everything. In this case, it is up to the specific
board to implement the PMP configuration in whichever way it sees fit.
With TCD set to loop, there is a window where the
DMA has raised Done, but not reloaded the TCD, resetting
count and clearing Done.
In this window imxrt_dmach_getcount could then return 0.
Resulting in imxrt_dma_nextrx returning RXDMA_BUFFER_SIZE.
Which is not a valid index in the FIFO.
Since the count will be set to RXDMA_BUFFER_SIZE. When the DMA
engine completes the TCD reload. The imxrt_dma_nextrx would
return 0. Therefore:
(RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE
accomplishes this.
With TCD set to loop, there is a window where the
DMA has raised Done, but not reloaded the TCD, resetting
count and clearing Done.
In this window imxrt_dmach_getcount could then return 0.
Resulting in imxrt_dma_nextrx returning RXDMA_BUFFER_SIZE.
Which is not a valid index in the FIFO.
Since the count will be set to RXDMA_BUFFER_SIZE. When the DMA
engine completes the TCD reload. The imxrt_dma_nextrx would
return 0. Therefore:
(RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE
accomplishes this.
With TCD set to loop, there is a window where the
DMA has raised Done, but not reloaded the TCD, resetting
count and clearing Done.
In this window imxrt_dmach_getcount could then return 0.
Resulting in imxrt_dma_nextrx returning RXDMA_BUFFER_SIZE.
Which is not a valid index in the FIFO.
Since the count will be set to RXDMA_BUFFER_SIZE. When the DMA
engine completes the TCD reload. The imxrt_dma_nextrx would
return 0. Therefore:
(RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE
accomplishes this.
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
The DMA can bring in more rx data, than the number of
DMA completions call backs. The call back happen on
idle, 1/2 and full events. But in between these events
the DMA can write more data to the buffers memory that
need to be brought in to the cache. (invalidate)
We do the invalidate on the reads from the fifo memory
if the the DMA as commited since the last read.
Previously, GPIO interrupts were not correctly mapped to the peripheral base register responsible for the interrupt.
Change the IRQ number calculation so the interrupts work correctly on all GPIO peripheral bases.
When ESP32's BLE is enabled, select the option to pin the HCI TX
thread to a specific core. This is necessary to avoid problems
with the BLE task that runs pinned to the PRO CPU (core 0) while
running with SMP enabled.
