Commit Graph

20622 Commits

Author SHA1 Message Date
Karel Kočí
62661600b2 treewide: add DOWNLOAD variable as unification of curl call
This is a followup to the commit
03b164f59c.
2023-03-08 17:05:05 +08:00
chao an
815f40c8f1 armv8-m/cortex-m85: add support of PACBTI(Authentication and Branch Target Identification Extension)
Reference:
https://developer.arm.com/documentation/100748/0617/Security-features-supported-in-Arm-Compiler-for-Embedded/PACBTI-M-extension-mitigations-against-ROP-and-JOP-style-attacks
https://developer.arm.com/documentation/101754/0619/armclang-Reference/armclang-Command-line-Options/-mbranch-protection

Signed-off-by: chao an <anchao@xiaomi.com>
2023-03-07 07:34:05 +02:00
Michal Lenc
f97d93903c samv7: add support for dead time delay to PWM driver
This commit adds support for dead time delay to SAMv7 PWM driver. The
dead time can be used to delay an active PWM output at the begining
of the period. This can be used for H bridge control for example.

The values are to be set from the application level. It is required
to allow config option PWM_DEADTIME in order to support dead time delay.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-03-07 01:30:01 +08:00
chao an
b48f9d9b96 arch/arm: correct ARCH_HAVE_DSP to ARM_HAVE_DSP
Signed-off-by: chao an <anchao@xiaomi.com>
2023-03-07 01:27:28 +08:00
Karel Kočí
eab9e688d8 samv7: switch from printing numbers as signed to unsigned in QSPI
This switches from PRId32 to PRIu32. Those variables have unsigned type
and thus we should print them as such.
2023-03-06 18:51:50 +02:00
chao an
34a032b486 arm/armv8-m: add missing zig flags
Signed-off-by: chao an <anchao@xiaomi.com>
2023-03-06 10:54:08 -03:00
Huang Qi
bcf5700e8a tools/arm: Add missing -mcpu param for zig
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-03-06 11:27:53 +01:00
raiden00pl
9dc8f27dda arch/nrf53: add SoftDevice support 2023-03-05 19:31:07 -03:00
raiden00pl
5fd321e54d arch/nrf53: add systimer configuration 2023-03-05 19:31:07 -03:00
raiden00pl
3b92819792 arch/nrf53: initial clock configuration 2023-03-05 19:31:07 -03:00
raiden00pl
15a932f8e1 arch/nrf53: add more registers definitions 2023-03-05 19:31:07 -03:00
raiden00pl
242606a7d9 arch/nrf52/nrf52_sdc: fix memory configuration for MULTIROLE 2023-03-05 21:32:11 +02:00
raiden00pl
238b606057 arch/nrf52: fix configuration for SoftDevice, LFCLK is required but it doesn't have to be XTAL 2023-03-05 21:32:11 +02:00
raiden00pl
cf5cd222d6 Revert "arch/nrf52/Kconfig: update comment about SoftDevice used PPI channels"
This reverts commit 688d2bb820.

It's not clear how many PPI channels is required.
Let's assume the worst case scenario, which is the previous version.
2023-03-05 21:32:11 +02:00
Bernd Walter
5ca9adbe61 Copy I2C_M_NOSTART support from sam7v/sam_twihs.c driver 2023-03-06 01:39:21 +08:00
Huang Qi
e7bf464c7a arch/imx6: Fix a compilation error with UBSan
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-03-05 11:06:48 +02:00
qinwei1
e3f0f86514 arm64: add arm64_serialinit/arm64_earlyserialinit
Summary:

   add arm64_serialinit/arm64_earlyserialinit function prototype
to arm64_internal.h as common function for arm64 based chip.
   Testing with ostest in SP and SMP

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-05 09:44:51 +08:00
raiden00pl
99b0bad94e arch/armv8-m: DSP extension is optional 2023-03-05 09:43:52 +08:00
Michal Lenc
1d88bceb79 samv7: raise input flow control warning only for serial drivers
Hardware flow control for serial requires the usage of DMAC channels
which is not yet supported for SAMv7 MCU. However the same config option
CONFIG_SERIAL_IFLOWCONTROL is also used for USB CDC/ACM flow control which
works well. Therefore the warning message should be raised only if
flow control is configured for USART driver and not for USB CDC/ACM.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-03-04 23:22:00 +08:00
raiden00pl
84d8b821e0 armv8-m/arm_ramvec_initialize.c: fix printf warning 2023-03-04 22:33:53 +08:00
raiden00pl
342fb22c3f arch/nrf52/.gitignore: clean up after SoftDevice update 2023-03-04 22:33:53 +08:00
raiden00pl
688d2bb820 arch/nrf52/Kconfig: update comment about SoftDevice used PPI channels 2023-03-04 22:33:53 +08:00
raiden00pl
bac798af07 arch/nrf52/sdc: remove no more needed core_cm4.h 2023-03-04 22:33:53 +08:00
Xiang Xiao
454921eac7 arch/boards: Rename up_lowputc to [arm64|renesas]_lowputc
follow other arch coding style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-04 11:08:00 +02:00
Gustavo Henrique Nihei
312d6223d3 xtensa: Remove non-supported options from CPUs' specs
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-04 12:56:58 +08:00
Gustavo Henrique Nihei
bf9951f939 xtensa/esp32: Move attribution to CMN_ASRCS to common makefile
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-04 12:56:58 +08:00
raiden00pl
49446c8e76 arch/nrf53: support for APPROTECT, and disable it at default for now 2023-03-04 12:35:14 +09:00
raiden00pl
ad4af9b9c9 arch/nrf53: boot the net core 2023-03-04 12:35:14 +09:00
raiden00pl
150b3622a8 arch/nrf53_gpio: add interface to assign GPIO to the net core 2023-03-04 12:35:14 +09:00
raiden00pl
e3008e13f3 arch/nrf53_gpio: MCUSEL is available only for the app core 2023-03-04 12:35:14 +09:00
raiden00pl
7cbaa98d88 nrf52/nrf53_serial: remove redundant include 2023-03-04 12:35:14 +09:00
raiden00pl
d58753725e arch/nrf53: add initial register definitions for CTRL-AP, RESET and UICR 2023-03-04 12:35:14 +09:00
zhangyuan21
0af63cfc48 sim/usb: add sim usb host
signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-03-03 14:31:30 -03:00
zhangyuan21
c61c694a77 sim/usb: add sim usb device
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-03-03 14:31:30 -03:00
zhangyuan21
392eebf5e2 arch/armv7-a: fixed scu cpu tagram mask define issue
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-03-03 11:41:33 +08:00
raiden00pl
eda99e35bb arch/nrf52: use the lates SoftDevice release (v2.3.0)
A list of breaking changes:
- SoftDevice libraries was renamed and libaries are now cmpatible with all platfroms with a given faimily.
- The random number generator was decoupled from the controller and must now be provided by the user.
  We use arc4random_buf NuttX API for this.
- sdc_support_ API must be called before sdc_cfg_set()
- update public API terms to Bluetooth Core Specification v5.3 (mainly change slave/master to central/peripheral)
  NuttX NRF52 configuration options properly updated.
- BLE features are supported only if the proper BLE role is selected
- sdc_hci_evt_get() and sdc_hci_data_get() have been replaced by sdc_hci_get()
2023-03-03 09:41:17 +08:00
jturnsek
081b04f05e iMXRT MCUboot support 2023-03-02 22:40:44 +08:00
Jari Nippula
aeddec2ec5 clear i2c ints before the transfer starts
If transfer is restarted in irq handler the interrupts shall be
cleared before the start bit is set in control register. This is
to avoid ints being accidentally cleared before they are handled leading
to timeout error.
2023-03-02 22:25:56 +08:00
Jari Nippula
6ba906691a clear spi int before the transfer starts
In spi_irq handler the data is written into txfifo and transfer
is started before the TXDONE interrupt is cleared. If the bus/memory
access is in some cases delayed, the spi transfer may have been
finished already before the interrupt register is cleaned for the
transfer. This leads the early arrived interrupt to be just removed
and never handled, which would cause a timeout error.
This patch moves the clearing of the interrupt to the place before
the tx is started, so the interrupt is not missed in above cases.
2023-03-02 22:05:25 +08:00
Jari Nippula
ab5d6d759a arch/arm/src/stm32f7/stm32_i2c.c: Driver cleanup
Remove unnecessary heap allocation by relocating ops inside priv data
2023-03-02 21:46:44 +08:00
qinwei1
d2d954f691 arm64: ARMv8-r(Cortex-R82) support( add FVP platform )
Summary:
   Adding virtual evaluate platform FVP. This FVP board configuration
will be used to emulate generic ARM64v8-R (Cotex-R82)series hardware
platform and provide support for these devices:

 - GICv3 interrupt controllers for ARMv8-r
 - PL011 UART controller(FVP)

Note:
1. ostest is PASSED at fvp ( single core and SMP)
2. the FVP tools can be download from ARM site, please check FVP
  board readme.txt

TODO: merge PL011 UART driver to common place

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-02 13:33:15 +08:00
Michal Lenc
93097be705 samv7: add support for PWM fault protection
This commit adds configurable fault protection to SAMv7 PWM driver.
The fault input can be used from peripherals as ADC or GPIO inputs.
Inputs from GPIO have configurable polarity (high or low). The PWM output
is automatically set to zero if fault input is active and restored
if fault input is not actived.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-03-02 11:08:25 +08:00
huxiandong
266455f01c mtd: Extend isbad and markbad func for mtd_dev_s
Signed-off-by: huxiandong <huxiandong@xiaomi.com>
2023-03-01 10:06:56 -03:00
qinwei2004
fa359e355c Update arm64_head.S 2023-03-01 13:23:48 +08:00
qinwei1
518eb4076e arm64: ARMv8-r(Cortex-R82) support(mpid fix)
Summary
  Different ARM64 Core will use different Affn define, the mpidr_el1
value is not CPU number, So we need to change CPU number to mpid
and vice versa, the patch change the mpid define into platform

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
d5c6b8a94b arm64: add 64-bit time for all arm64 platform
Summary
  For ARM64 architecture, the arch timer is 64-bit,
the CONFIG_SYSTEM_TIME64 need to be enabled just like
x86_64 and risc-v 64

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
4cb5ff3353 arm64: ARMv8-r(Cortex-R82) support(add ARCH_SET_VMPIDR_EL2 option)
Summary

   VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID.
From architecture manual of AArch64, the behave is:
  -reading register MPIDR_EL1 in EL2, it's return real MPIDR_EL1
  -reading register MPIDR_EL1 in EL1, it's return VMPIDR_EL2
  So since NuttX for SMP is running at EL1 to read MPIDR_EL1 for
  identify CPU id, it's need to set VMPIDR_EL2 to MPIDR_EL1 for
  every CPU at boot EL2 stage.
  For some platform, the bootloader or hypervisor will do that at
  the EL2 stage, but not all.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
0841f4dbaa arm64: ARMv8-r(Cortex-R82) support
Summary:

  Adding armv8-r(Cortex-R82) support and modify some common code to
fit the change, the change including:

1. ARM Single Security State Support, ARMv8-R support only single
   security state, and some GIC configure need to change and fit
2. For ARMv8-R, only have EL0 ~ EL2, the code at EL3 is not necessary
   and system register for EL3 is not accessible(gcc will failed when
   access these registers)
3. add base MPU configure for the platform.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
4240723b78 arm64: add ARCH_EARLY_PRINT support
Summary:
  The aarch64 have EL0~El3 execute level and NS/S (security state),
the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
state. but booting NuttX have different ELs and state while with
different platform, if NuttX runing at wrong ELs or state it will
be not normal anymore. So we need to print something in arm64_head.S
to debug this situation.
Enabling this option will need to implement up_earlyserialinit and
up_lowputc functions just you see in qemu, if you not sure,
keeping the option disable.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
qinwei1
e5564a9872 arm64: PSCI config support
Summory
   This Power State Coordination Interface (PSCI) defines a standard
interface for power management. the PCSI need to implement handling
firmware at EL2 or EL3 for ARM64. the PSCI maybe not applicable
for arm core without PCSI firmware interface implement.
  Add configure option for it.

Note:
1. ostest is PASSED at qemu and fvp ( single core and SMP)

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-01 13:23:48 +08:00
SPRESENSE
b576a26d51 arch: cxd56xx: Fix emmc pin control on initialization error
Fix emmc pin control on initialization error.
2023-03-01 12:29:23 +08:00
SPRESENSE
57ca5c0401 arch: cxd56xx: Disable SubCore to use DMA
Disable SubCore to use SPI transfer with DMA because it may be used
by MainCore.
2023-03-01 12:29:23 +08:00
SPRESENSE
134424da18 arch: cxd56xx: Fix a warning in cxd56_serial.c
Fix a warning by -Wunused-function when CONFIG_UART2_SERIAL_CONSOLE=y.
2023-03-01 12:29:23 +08:00
SPRESENSE
700610e625 arch: cxd56xx: Fix eMMC uninitialize function
- Fix prototype function with prefix of cxd56.
- Add logic to unregister blockdriver.
- Minor fix nxstyle.
2023-03-01 12:29:23 +08:00
SPRESENSE
d643fb8511 arch: cxd56xx: Fix gnss poll when an event has already occurred
Fix an issue that poll with timeout=0 cannot detect events that have
already occurred.
2023-03-01 12:26:06 +08:00
SPRESENSE
1877be8ce9 arch: cxd56xx: Fix a freezing issue caused by power control
- Add retry timeout to prevent inifinite loop
- Change the register operation of power control
- Add exclusive control by semaphore into some functions
- Add short delay until power control is reflected
2023-03-01 12:17:29 +08:00
Gustavo Henrique Nihei
e4d219ca06 risc-v/esp32c3: Remove erroneous interrupt disable
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-02-28 22:14:54 +02:00
Dong Heng
f47cb67da6 xtensa/common: Fix Xtensa interrupt stack context restore issue 2023-02-28 16:36:55 -03:00
Alan Carvalho de Assis
49a5f02fb1 esp32c3: Fix missing irq timer 2023-03-01 01:22:24 +08:00
Huang Qi
8a389a06e1 Don't download tarball if a local git repo found
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-02-27 23:55:23 +08:00
Xiang Xiao
2c5f653bfd Remove the tail spaces from all files except Documentation
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-26 13:24:24 -08:00
Michal Lenc
49ce1c5df7 samv7: add support for ADC conversion triggering with PWM
This commit enhances ADC and PWM drivers with option to trigger ADC
conversion with events generated by PWM comparison units.

The generation of PWM events is handled by comparison units set up from
Kconfig option SAMV7_PWMx_TRIGn. ADC triggering from PWM can be selected
by AFECn_PWMTRIG option.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-02-26 10:47:12 +08:00
lilei19
38f64f559d change strcpy to strlcpy
Signed-off-by: lilei19 <lilei19@xiaomi.com>
2023-02-24 12:15:40 +08:00
Tiago Medicci Serrano
173212ebc9 esp32s3: Define syscall table to enable using ROM functions 2023-02-24 04:06:50 +08:00
Alan Carvalho de Assis
119dabaf73 esp32c3: Fix WDT incorrect interrupt enable/disable 2023-02-23 21:57:15 +02:00
Xiang Xiao
8b4ecac6c2 libc: Move math library from libs/libc/math to libs/libm/libm
to prepare the support of other implementation e.g.:
https://github.com/JuliaMath/openlibm
https://gitlab.com/gtd-gmbh/libmcs

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-23 10:40:07 +02:00
chao an
0e873b51c6 arm/backtrace/unwind: skip unaligned instruction
Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-23 14:06:52 +08:00
Michal Lenc
db6919648b samv7: add support for complementary PWM output
SAMv7 PWM driver supports complementary PWM output if both pins (H and L)
are defined and configured. This commit adds a configuration option to
configure the complementary L pin.

The pin definition has to be provided by board level support.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-02-22 02:22:10 +08:00
Karel Kočí
60bd4ac13d samv7: fix printf warnings in QSPI 2023-02-22 01:42:49 +08:00
Masayuki Ishikawa
69e6e17407 arch: imxrt: Enable IMXRT_ENET_ENHANCEDBD if !ARMV7M_DCACHE_WRITETHROUGH
Summary:
- I noticed that there are two kinds of descriptors for imxrt_enet.c
- The first one is the legacy descriptor and its size is 8bytes.
- The second one is the enhanced descriptor and its size is 32bytes.
- In both cases, we can not use a descriptor chain like stm32.
- Considering cache line alignment, the second one is perfect because
  one descriptor fits the Cortex-M7 cache line which would fix networking
  stability issues in d-cache write-back mode.

Impact:
- imxrt ethernet in d-cache write-back mode

Testing:
- Tested with ixmrt1060-evk:netnsh_dcache_wb (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-02-22 01:27:54 +08:00
Masayuki Ishikawa
3a4542f3c4 arch: imxrt: Fix CONFIG_IMXRT_ENET_ENHANCEDBD
Summary:
- I noticed that CONFIG_IMXRT_ENET_ENHANCEDBD is not correctly
  used though it is defined in Kconfig.
- This commit fixes this issue.

Impact:
- None

Testing:
- Tested with imxrt1060-evk:netnsh_dcache_wb (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-02-22 01:27:54 +08:00
chao an
60a0c2ed87 tools/ci: skip -Warray-bounds check due to bug of GCC-12.2
Wrong warning array subscript [0] is outside array bounds:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105523

Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-21 09:28:57 +08:00
Xiang Xiao
7d3a9b1cbc Revert "STM32 Nucleo: warning: #warning "Default Flash Configuration Used""
This reverts commit 62c15c03d3.

Fix warning: the choice symbol STM32_FLASH_CONFIG_G (defined at arch/arm/src/stm32/Kconfig:1275) is selected by the following symbols, but select/imply has no effect on choice symbols
 - ARCH_CHIP_STM32F412ZG (defined at arch/arm/src/stm32/Kconfig:1014)
2023-02-20 00:02:36 +02:00
Michal Lenc
333707e101 pwm: add PWM overwrite under CONFIG_PWM_OVERWRITE option
Generic drivers shoud not use architecture related config options like
CONFIG_SAMV7_PWM. This commit adds PWM pin overwrite under generic
configuration option CONFIG_PWM_OVERWRITE.

Now the overwrite can be used on other architectures as well or can be
completely disabled for SAMv7.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-02-19 00:16:41 +08:00
dirksavage88
02fc698e75 Add UART4 & UART5 to high density stm32f103 chips
Signed-off-by: dirksavage88 <dirksavage88@gmail.com>
2023-02-18 13:32:52 +08:00
Fotis Panagiotopoulos
9bfa9a0b49 stm32_eth: Enabled store-end-forward. 2023-02-18 11:08:46 +08:00
Fotis Panagiotopoulos
87a23f8e38 stm32_eth: Fixed alignment of Ethernet descriptors & buffers. 2023-02-18 11:06:59 +08:00
Michal Lenc
d52e875a99 samv7: fix build error in sam_mcan.c file
Commit d07792a caused a build error in sam_mcan.c file. This commit fixes
the build. The file now succesfully compiles and CAN works.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-02-17 14:58:37 -03:00
Jackson R
62c15c03d3 STM32 Nucleo: warning: #warning "Default Flash Configuration Used"
https://cwiki.apache.org/confluence/display/NUTTX/Configuration+Variables
Fixed the Warning F412ZG has 1028 KB Flash.
2023-02-17 23:22:32 +08:00
Fotis Panagiotopoulos
85ceb7920e Typo fixes. 2023-02-17 11:17:11 -03:00
David Sidrane
c6d3e7e087 stm32:dma v2 Remove CPU lock on HW fail 2023-02-17 14:23:27 +08:00
David Sidrane
d2ea49109a stm32h7:dma Remove CPU lock on HW fail 2023-02-17 14:23:27 +08:00
David Sidrane
8064f60a9e stm32f7:dma Remove CPU lock on HW fail 2023-02-17 14:23:27 +08:00
Nathan Hartman
b881948b27 arch/pic32mz: Fix compiler warnings in pic32mz_ethernet.c
* arch/mips/src/pic32mz/pic32mz_ethernet.c
  (): Fix warnings related to printf-style format specifiers.
2023-02-17 09:58:02 +08:00
Fotis Panagiotopoulos
f78bdd3978 stm32_eth: Busy bit is cleared before accessing the MACMIIAR register. 2023-02-17 09:56:35 +08:00
Nathan Hartman
1d5c8380b1 arch/pic32mz: Serial TIOCxBRK BSD-compatible BREAK support
In the lower half UART driver for PIC32MZ architecture, adding the
TIOCxBRK ioctl calls, which allow an application to transmit a UART
line BREAK signal.

This architecture does not support BSD-style BREAK in hardware so our
implementation follows the precedent set in STM32, GD32, and Kinetis
architectures: By default, if only PIC32MZ_UART_BREAKS is configured,
we produce the hardware-native BREAK, which lasts for 12 bit lengths;
if, in addition, PIC32MZ_SERIALBRK_BSDCOMPAT is configured, we
generate a BSD-style BREAK by putting the TX pin in GPIO mode and
driving it low "manually" until told to stop.

* arch/mips/src/pic32mz/Kconfig
  (config PIC32MZ_UART_BREAKS): New. Appears as
   CONFIG_PIC32MZ_UART_BREAKS in code.
  (config PIC32MZ_SERIALBRK_BSDCOMPAT): New. Appears as
   CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT in code.

* arch/mips/src/pic32mz/hardware/pic32mz_pps.h
  (__PPS_OUTPUT_REGADDR_TO_GPIO, PPS_OUTPUT_REGADDR_TO_GPIO): New
   macros to automatically determine the GPIO port and pin from the
   corresponding PPS (Peripheral Pin Select) define. Since there is a
   one-to-one correspondence between PPS output mappings and a single
   port and pin, these macros avoid writing redundant pin mappings. We
   use this when switching the TX pin from UART to GPIO to generate
   the BREAK and we could use it in other peripheral drivers in the
   future to override hardware behavior.

* arch/mips/src/pic32mz/pic32mz_serial.c
  (struct up_dev_s): Add new field 'brk' to indicate line break in
   progress when built with PIC32MZ_UART_BREAKS. If generating BSD-
   compatible BREAKs, also add tx_gpio, tx_pps_reg, and tx_pps_val, to
   let us toggle the pin between UART and GPIO modes.
  (up_ioctl): Add cases for TIOCSBRK and TIOCCBRK to turn BREAK on and
   off, with both hardware-native and BSD-compatible implementations.
   This is similar to the STM32F7 implementation.
  (up_txint): Block enabling TX interrupt if line break in progress.
   This is similar to the STM32F7 implementation.
2023-02-17 09:55:29 +08:00
Jackson R
37db965cff This simulator was tested on ARM MacBook.
Updating Simulator for macOS

macOS requires genromfs and X11 Libraries to run Simulators.
* Added instructions to install genromfs
* Added instructions to install X11
Adding Xorg Server

The linker was unable to identify the location of X11 libraries.

removed -L/opt/X11/lib from ln 145

Updating Changes to streamline with other Hosts
2023-02-16 09:27:54 +08:00
Nathan Hartman
212ef18803 arch/pic32mz: Fix typos in PPS register mapping defines
The PIC32MZ architecture provides a Peripheral Pin Select (PPS) which
allows mapping peripherals to different GPIO pins. To map a peripheral
output, a value is programmed to a register called RPnxR, where n is
the GPIO port (A thru K) and x is the GPIO pin (0 thru 15). The names
of these registers in code are PIC32MZ_RPnxR. However, in various
definitions, these were mistakenly written as PI32MZ_RPnxR (missing C
in PIC32). This prevents using any of the affected mappings. This
issue is fixed by repairing the define names.

* arch/mips/src/pic32mz/hardware/pic32mzec_pps.h,
  arch/mips/src/pic32mz/hardware/pic32mzef_pps.h:
  (): s/PI32MZ/PIC32MZ/g
2023-02-16 09:27:33 +08:00
Nathan Hartman
7c90fbd7c2 arch/pic32mz: Fix PPS mappings for RPE5R register
The defines for Peripheral Pin Select (PPS) register RPE5R were called
RPE4R inadvertently; however, mappings elsewhere in the file used the
correct name of RPE5R, so the build would break if anyone attempted to
map those peripherals to GPIO pin E5. This issue is now fixed.

* arch/mips/src/pic32mz/hardware/pic32mzec_pps.h,
  arch/mips/src/pic32mz/hardware/pic32mzef_pps.h:
  (PIC32MZ_RPE4R_OFFSET): Rename to PIC32MZ_RPE5R_OFFSET.
  (PIC32MZ_RPE4R): Rename to PIC32MZ_RPE5R.
2023-02-16 09:26:30 +08:00
Nathan Hartman
6fb08b8b03 Fix typos: s/UARt/UART/ 2023-02-16 09:25:35 +08:00
Julian Oes
4f30c298bf stm32h7: reduce the extended filter size to 64
When I checked how this register was set I discovered that 128 was not
accepted by the H7 but 64 was ok. Looking at the STM32Cube's HAL it
seems to be only 64 words long, however, the reference manual claims
otherwise.

I have opened a discussion on the ST community forum
https://community.st.com/s/question/0D73W000001nzqFSAQ
but unfortunately not received an answer yet.

In the meantime, I think, we should update this to what I found to be
working though.

Signed-off-by: Julian Oes <julian@oes.ch>
2023-02-15 19:06:54 +08:00
Julian Oes
a59e65db3f stm32h7: fix comment
This was likely just a copy-paste error.

Signed-off-by: Julian Oes <julian@oes.ch>
2023-02-15 19:06:54 +08:00
Eero Nurkkala
b9ba262fb7 risc-v/mpfs: add athena irq defines
Add the Athena cryptographic microprocessor irq defines.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-02-15 00:21:03 +08:00
chao an
1e7014262c sim/windows: fix build break on visual studio
1. fix build break on visual studio
2. enable more net config

Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-13 20:37:25 +08:00
ligd
87a92d995f sim: fix nuttx consumes much CPU time
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-02-13 18:41:43 +09:00
ligd
758668d11a sim: remove sim_saveusercontext() return value
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-02-13 18:41:43 +09:00
ligd
7e3e99c940 sim: fix vfork report error
user_main: vfork() test
=================================================================
==3754757==ERROR: AddressSanitizer: stack-buffer-underflow on address 0xae9126f0 at pc 0x56845661 bp 0xae912570 sp 0xae912560
READ of size 1 at 0xae9126f0 thread T0
    #0 0x56845660 in memcpy string/lib_memcpy.c:44
    #1 0x56b70f61 in up_vfork sim/sim_vfork.c:133
    #2 0x567c0b85 in vfork (/home/ligd/platform/sim/nuttx/nuttx+0x26bb85)

0xae9126f0 is located 73456 bytes inside of 73728-byte region [0xae900800,0xae912800)
allocated by thread T0 here:
    #0 0xf7ab1c2f in __interceptor_posix_memalign ../../../../../src/libsanitizer/asan/asan_malloc_linux.cpp:226

SUMMARY: AddressSanitizer: stack-buffer-underflow string/lib_memcpy.c:44 in memcpy

Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-02-12 02:37:25 +08:00
Fotis Panagiotopoulos
1b372a55cc stm32_sdio: Fix in SDIO clocking configuration. 2023-02-11 23:29:11 +08:00
Michal Lenc
00e87962fd imxrt: add option to select PWM trigger source value from configuration
Current implementation supports the trigger generation only from timer
capture on period value. This is sufficient for PWM synchronization but
may not be enough for other purposes as ADC triggering for example.

This change adds an option to generate the trigger based on a duty
cycle value.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-02-11 20:07:28 +08:00
chenwen@espressif.com
cfc9029c5d risc-v/esp32c6: Add ESP32-C6 basic support
1. Bring up OS kernel.
  2. Add interrupt support.
  3. Add system timer support.
  4. Add the ESP32-C6 devkit board.
  5. Add basic UART support for console.
  6. Add clock configuration.
  7. Add board reset support.
2023-02-10 17:38:41 -03:00
Masayuki Ishikawa
777c6c4aad arch: imxrt: Fix imxrt for CONFIG_BUILD_PROTECTED=y
Summary:
- Fix imxrt_allocateheap.c for CONFIG_BUILD_PROTECTED=y
- Call mpu_reset() in imxrt_mpuinit.c

Impact:
- CONFIG_BUILD_PROTECTED=y only

Testing:
- Tested with imxrt1060-evk:knsh (will be updated later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-02-09 23:30:50 -08:00
ligd
1cc6e4b1fa sim: add uart dma mode & use work instead of loop.
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-02-10 13:54:42 +08:00
Janne Rosberg
739688f6c6 sama5/twi: add support for flexcom twi 2023-02-10 10:56:56 +08:00
Michal Lenc
725dfd5db9 samv7: fix compilation error when only DAC1 is configured
The function call dac_txdone(&g_dac1dev) was not contained in ifdef
section. This was cousing compilation error if only DAC1 was configured
as the structure g_dac1dev is defined only if DAC0 is used.

This commit fixes the error and ensures the function is called only if
corresponding DAC is configured.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-02-10 02:33:30 +08:00
TimJTi
becaf3bf9d Correct SAMA5_USBA_DRP to be SAMA5_USB_DRP 2023-02-10 01:01:03 +08:00
TimJTi
b3365858ee Fix sam_udphs to allow RNDIS to work
Update sam_udphs.c
2023-02-10 00:55:59 +08:00
Peter Bee
2ebccd82b6 drivers/video: add timestamp support
Add support for timestamp and change in related drivers

Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
2023-02-09 23:27:15 +08:00
chao an
74ce3b81d3 build/Kconfig: add BINDIR/APPSBINDIR to support out of tree build
First decoupling changes related to CMAKE

BINDIR/APPSBINDIR:
Output path of Kconfig which dynamically generated by NuttX Kernel/Apps
This option is consistent with the TOPDIR/APPSDIR by default, and will
be changed when out-of-tree compilation is supported

Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-09 20:13:04 +08:00
chao an
e942a7c55e build/Kconfig: fix warnings detected by kconfiglib
Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-09 20:07:46 +08:00
chao an
3a0fdb019d nuttx: replace all ARRAY_SIZE()/ARRAYSIZE() to nitems()
Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-09 20:05:44 +08:00
ligd
9b35a2e1a1 sim: fix compile warning
sim/sim_doirq.c: In function 'sim_doirq':
Error: sim/sim_doirq.c:79:10: error: function may return address of local variable [-Werror=return-local-addr]
   79 |   return regs;
      |          ^~~~
sim/sim_doirq.c:44:14: note: declared here
   44 |   xcpt_reg_t tmp[XCPTCONTEXT_REGS];
      |              ^~~

Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-02-09 14:22:38 +08:00
ligd
16367aa084 sim: correct save irq flags error when use sim 64bits
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-02-09 14:22:38 +08:00
ligd
8aecad287c sim: set loop task duration to 10ms
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-02-09 14:19:09 +08:00
ligd
f102837fe1 sim: realize sim timer tickless
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-02-09 14:19:09 +08:00
Zhihong Chen
d082af34f7 add hpmicro chip: hpm6750
Signed-off-by: Zhihong Chen <zhihong.chen@hpmicro.com>
2023-02-09 14:17:49 +08:00
TimJTi
4aada75249 Changes to allow board-specific DRP/OTG support
Update sam_udphs.c
2023-02-09 03:42:55 +08:00
Lucas Saavedra Vaz
1fb6dcec3b arch/xtensa/esp32s2: Fix function header 2023-02-09 02:39:54 +08:00
Lucas Saavedra Vaz
b29198a62a arch/xtensa/esp32s3: Add support for touch pad interrupts 2023-02-09 02:39:54 +08:00
Ville Juven
9ac3e841da group_addrenv: Fix call to group_addrenv for targets that don't need it 2023-02-09 00:14:52 +08:00
Nathan Hartman
375cb09ff0 arch/pic32mz: Serial support for termios
Previously, it was impossible to build for PIC32MZ architecture with
CONFIG_SERIAL_TERMIOS because it introduced compiler errors in the
lower half driver.

Fixing the compiler errors and adding an implementation of the
TIOCSERGSTRUCT, TCGETS, and TCSETS ioctl calls.

* arch/mips/src/pic32mz/pic32mz_serial.c
  (): Include nuttx/fs/ioctl.h, needed for the TIOCSERGSTRUCT, TCGETS,
   and TCSETS defines.
  (up_ioctl): Fix compile breakage. Implement TIOCSERGSTRUCT. Make
   TCGETS return data bits, parity, and stop bits. Make TCSETS apply
   changes to data bits, parity, and stop bits.
2023-02-08 23:55:37 +08:00
Nathan Hartman
8b2c8c73e8 arch/tiva: Serial TIOCxBRK BSD-compatible BREAK support
In the lower half UART driver for Tiva architecture (TM4C12x), adding
the TIOCxBRK ioctl calls, which allow an application to transmit a BSD
compatible line BREAK. TIOCSBRK starts the BREAK and TIOCCBRK ends it.

This architecture supports BSD-style BREAK in hardware. We write to
the BRK bit (bit 0) of the UART Line Control register (UARTLCRH) to
start the BREAK, which begins after the UART finishes shifting out the
current character in progress, if any, including its stop bit(s), and
continues indefinitely until we write to the BRK bit again to stop the
BREAK.

* arch/arm/src/tiva/Kconfig
  (config TIVA_UART_BREAKS): New. Appears as CONFIG_TIVA_UART_BREAKS
   in code.

* arch/arm/src/tiva/common/tiva_serial.c
  (struct up_dev_s): Add new field 'brk' to indicate line break in
   progress when built with CONFIG_TIVA_UART_BREAKS.
  (up_ioctl): Add cases for TIOCSBRK to turn BSD-compatible break on
   unconditionally and TIOCCBRK to turn break off unconditionally.
  (up_txint): Block enabling TX interrupt if line break in progress.
   This is similar to the STM32F7 implementation.
2023-02-08 23:55:28 +08:00
ligd
24cdcd9a6e sim: fix kasan report memalign crash when alignment is 1
(0)Allocating 3 bytes aligned to 0x00000001
=================================================================
==1461685==ERROR: AddressSanitizer: invalid alignment requested in posix_memalign: 1, alignment must be a power of two and a multiple of sizeof(void*) == 4 (thread T0)
    #0 0xf7ab1c2f in __interceptor_posix_memalign ../../../../../src/libsanitizer/asan/asan_malloc_linux.cpp:226

Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-02-08 20:37:43 +08:00
ligd
8d0094f6c9 sim: fix color running stack crash when use -Os
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-02-08 20:37:43 +08:00
qiaohaijiao1
b6472b8b15 sim/sim_alsa: add audio offload capture support.
use host liblame as encoder.

Signed-off-by: qiaohaijiao1 <qiaohaijiao1@xiaomi.com>
2023-02-08 13:55:17 +08:00
Alan Carvalho de Assis
63a847ebca esp32s3-devkit: Add support LED PWM initialization 2023-02-08 11:02:19 +08:00
Alan Carvalho de Assis
453d9688c7 esp32s3: Add support to PWM using LEDC 2023-02-08 11:02:19 +08:00
Alan Carvalho de Assis
94970f32d7 esp32s2-saola-1: Add initialization to LEDC PWM 2023-02-08 10:56:32 +08:00
Alan Carvalho de Assis
39729bb635 esp32s2: Add support to LEDC PWM 2023-02-08 10:56:32 +08:00
Lucas Saavedra Vaz
d7b66adbeb arch/xtensa/esp32s3: Add support for RTC IRQs 2023-02-08 10:56:15 +08:00
Lucas Saavedra Vaz
14d95eb131 arch/risc-v/esp32c3: Add RTC interrupt support 2023-02-08 10:42:19 +08:00
Nathan Hartman
5d2e1d40dc arch/tiva: Fix inability to control serial CTS/RTS via termios
* arch/arm/src/tiva/common/tiva_serial.c:
  (up_ioctl): PR #8406 (commit 1edec0aaa1) added support for
   configuring the serial port's CTS/RTS flow control at runtime using
   termios when built with CONFIG_SERIAL_TERMIOS and either or both of
   CONFIG_SERIAL_OFLOWCONTROL and CONFIG_SERIAL_IFLOWCONTROL. However,
   a runtime sanity check left over from before prevented this from
   working: When processing ioctl TCSETS, we would return -EINVAL if
   one or both of CCTS_OFLOW and CRTS_IFLOW were requested, which was
   not deserved if the requested features were in fact supported.
   Fixing the sanity check so it depends on features actually
   configured.
2023-02-08 10:31:11 +08:00
Nathan Hartman
1b3cac19a0 serial: Fix typo in comments (s/besued/because/) 2023-02-08 10:05:27 +08:00
Ville Juven
f4b82b6405 sched/addrenv: Remove up_addrenv_restore
The function is not relevant any longer, remove it. Also remove
save_addrenv_t, the parameter taken by up_addrenv_restore.

Implement addrenv_select() / addrenv_restore() to handle the temporary
instantiation of address environments, e.g. when a process is being
created.
2023-02-08 02:51:23 +08:00
Ville Juven
09e7987121 sched/addrenv: Fix system crash when process group has been deleted
There is currently a big problem in the address environment handling which
is that the address environment is released too soon when the process is
exiting. The current MMU mappings will always be the exiting process's, which means
the system needs them AT LEAST until the next context switch happens. If
the next thread is a kernel thread, the address environment is needed for
longer.

Kernel threads "lend" the address environment of the previous user process.
This is beneficial in two ways:
- The kernel processes do not need an allocated address environment
- When a context switch happens from user -> kernel or kernel -> kernel,
  the TLB does not need to be flushed. This must be done only when
  changing to a different user address environment.

Another issue is when a new process is created; the address environment
of the new process must be temporarily instantiated by up_addrenv_select().
However, the system scheduler does not know that the process has a different
address environment to its own and when / if a context restore happens, the
wrong MMU page directory is restored and the process will either crash or
do something horribly wrong.

The following changes are needed to fix the issues:
- Add mm_curr which is the current address environment of the process
- Add a reference counter to safeguard the address environment
- Whenever an address environment is mapped to MMU, its reference counter
  is incremented
- Whenever and address environment is unmapped from MMU, its reference
  counter is decremented, and tested. If no more references -> drop the
  address environment and release the memory as well
- To limit the context switch delay, the address environment is freed in
  a separate low priority clean-up thread (LPWORK)
- When a process temporarily instantiates another process's address
  environment, the scheduler will now know of this and will restore the
  correct mappings to MMU

Why is this not causing more noticeable issues ? The problem only happens
under the aforementioned special conditions, and if a context switch or
IRQ occurs during this time.
2023-02-08 02:51:23 +08:00
Ville Juven
5713d85df0 group/group_addrenv: Move address environment from group -> tcb
Detach the address environment handling from the group structure to the
tcb. This is preparation to fix rare cases where the system (MMU) is left
without a valid page directory, e.g. when a process exits.
2023-02-08 02:51:23 +08:00
Lucas Saavedra Vaz
21d9163aae arch/xtensa/esp32s2: Add support for touch pad interrupts 2023-02-07 12:19:41 +08:00
Lucas Saavedra Vaz
247aad82f2 arch/xtensa/esp32s2: Fix touch function typo 2023-02-07 12:19:41 +08:00
Nathan Hartman
5f9cb6faf4 drivers/serial: Fix docstrings on UART interrupt handlers 2023-02-07 04:41:36 +08:00
chao an
1b245664ad arm/rp2040: fix compile warning on boot2 build
ld: warning: boards/arm/rp2040/raspberrypi-pico-w/scripts/raspberrypi-pico-flash.ld contains output sections; did you forget -T?
Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-07 04:40:38 +08:00
chao an
5ac638944b arm/backtrace: fix compile warning
common/arm_backtrace_unwind.c: In function 'up_backtrace':
common/arm_backtrace_unwind.c:626:27:
warning: assignment to 'long unsigned int' from 'uint8_t (*)[]'\
{aka 'unsigned char (*)[]'} makes integer from pointer without a cast [-Wint-conversion]

  626 |           frame.stack_top = &g_intstacktop;
      |
2023-02-07 04:40:38 +08:00
Lucas Saavedra Vaz
1e3af48fff arch/xtensa/esp32s2: Add support for RTC IRQs 2023-02-04 18:28:10 -03:00
wangbowen6
a11cb59af6 tc32/Make.defs: fix build break after merge unblock/block_task
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2023-02-04 18:25:58 -03:00
wangbowen6
f925e17f18 tlsr82/backtrace: tc32 backtrace bug fix
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2023-02-04 18:25:58 -03:00
chao an
edfae1fe21 sim/hcisocket: correct teardown device index
Parameter of HCIDEVDOWN should be the corresponding device id, not 0

Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-03 23:22:54 +08:00
chao an
7625126c91 Remove the remain MIN/MAX like macro
Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-03 23:22:41 +08:00
Xiang Xiao
09841300b0 Remove the remain MIN/MAX like macro
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-03 20:42:57 +08:00
Alan Carvalho de Assis
e710ae5daf esp32c3: reserve CPUINTs 5 and 8 for BLE 2023-02-03 12:24:11 +08:00
Alan Carvalho de Assis
c12a60cb5a esp32c3: Fix WiFi adapter to use WMAC instead of MAC_NMI 2023-02-03 12:24:11 +08:00
Alan Carvalho de Assis
e950e53df2 esp32c3: Always reserve CPU INT 0 and fix cpu init order
Co-author: Tiago Medicci <tiago.medicci@espressif.com>
Co-author: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-02-03 12:24:11 +08:00
chao an
eca4951021 nuttx: Use MIN/MAX definitions from "sys/param.h"
Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-02 22:16:04 +08:00
Xiang Xiao
df102d1f06 Remove OK macro from the code base
let's use OK from sys/types.h instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-02 13:58:16 +01:00
ligd
3ae4a6b8c3 sim/uart: do uart_xmitchars() when tty_txint enabled
to speed up the logout speed

Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-02-02 18:27:39 +08:00
chao an
03b164f59c tools/makefile: silent all compile output
In order to make compilation warnings and errors easier to be found out,
this commit will disable the printing of the compilation process as much
as possible, and also if you want to restore the log information of the
compilation process, please enable verbose build on command line:

$ make V=0
OR
$ make V=1

| V=0:   Exit silent mode
| V=1,2: Enable echo of commands
| V=2:   Enable bug/verbose options in tools and scripts

Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-02 17:40:19 +08:00
chao an
4c8d244fae sched/getpid: replace syscall getpid/tid/ppid() to kernel version
NuttX kernel should not use the syscall functions, especially after
enabling CONFIG_SCHED_INSTRUMENTATION_SYSCALL, all system functions
will be traced to backend, which will impact system performance.

Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-02 10:33:01 +08:00
Nathan Hartman
5651940d02 tiva/serial: Allow changing CTS/RTS with termios
This is a follow-up to PR #6548, which added UART CTS/RTS support for
Tiva (TI TM4C12x) microcontrollers. This follow-up makes it possible,
when termios support is enabled with CONFIG_SERIAL_TERMIOS and CTS/RTS
support is enabled with CONFIG_SERIAL_OFLOWCONTROL and/or
CONFIG_SERIAL_IFLOWCONTROL, to query whether CTS/RTS are on/off at
runtime by utilizing ioctl TCGETS and to turn CTS/RTS on/off at runtime
by utilizing ioctl TCSETS.

* arch/arm/src/tiva/common/tiva_serial.c
  (up_set_format): Because this function is called from ioctl TCSETS to
   modify UART settings, and that IOCTL now respects CCTS_OFLOW and
   CRTS_IFLOW, move setting/clearing of Tiva UART's CTL register's RTSEN
   and CTSEN bits here...
  (up_setup): ...from here.
  (up_ioctl): For TCGETS, populate CCTS_OFLOW and CRTS_IFLOW bits as
   appropriate. For TCSETS, populate priv's oflow and iflow from
   supplied CCTS_OFLOW and CRTS_IFLOW bits.

Thanks to Petro Karashchenko for review and suggested fixes.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-02-02 09:44:07 +08:00
Nathan Hartman
f2e15b431c Support termios for Tiva
The lower-half serial driver for Tiva (TI TM4C12x) microcontrollers supports
termios, but Kconfig never enabled this support because we were missing the
ARCH_HAVE_SERIAL_TERMIOS configs. This is now enabled, allowing termios support
to be enabled with CONFIG_SERIAL_TERMIOS.

* arch/arm/src/tiva/Kconfig
  (config TIVA_UART0 thru TIVA_UART7): Select ARCH_HAVE_SERIAL_TERMIOS.
2023-02-02 09:43:09 +08:00
Nathan Hartman
78154f12ff Serial: Fix wrong identifier name in comments 2023-02-02 09:42:34 +08:00
Gustavo Henrique Nihei
e6b204f438 nuttx: Use MIN/MAX definitions from "sys/param.h"
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-02-01 23:47:44 +08:00
Stuart Ianna
05c6d7c7b9 litex: Add PWM driver.
PWM driver for multiple peripherals supplied in gateware.

Only single channel frequency and duty cycle control is implemented. Pulse counting and multichannel features are not currently feasible.

Additions also include a new board configuration for arty-a7 which enables the PWM driver and example application.
2023-02-01 09:34:57 -03:00
zhuyanlin
96a70b908f arch:xtena: modify timer interrupt level large to XCHAL_IRQ_LEVEL level.
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-02-01 14:04:44 +08:00
Huang Qi
8b27d60bcd tools: Make zig available for arm/riscv/sim
Add essential compile flags to make zig available out of box.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-02-01 11:12:44 +08:00
qiaohaijiao1
38039df16a sim/sim_alsa.c: support streaming data when offload playback.
Audio offload playback, change data organization from fragmented to
streaming.

Signed-off-by: qiaohaijiao1 <qiaohaijiao1@xiaomi.com>
2023-02-01 11:03:36 +08:00
Stuart Ianna
26ac5335e5 litex: Add GPIO driver.
GPIO driver with optional ISR support. Allows for multiple GPIO peripherals to be specified at an arbitrary addresses.
2023-02-01 11:02:03 +08:00
Nathan Hartman
fdb149ddb0 Kconfig: Improve help text related to *_SERIALBRK_BSDCOMPAT
* arch/arm/src/gd32f4/Kconfig
  (GD32F4_SERIALBRK_BSDCOMPAT): Improve help text.

* arch/arm/src/stm32/Kconfig
  (STM32_SERIALBRK_BSDCOMPAT): Improve help text.

* arch/arm/src/stm32f7/Kconfig
  (STM32F7_SERIALBRK_BSDCOMPAT): Improve help text.

* arch/arm/src/stm32h7/Kconfig
  (STM32H7_SERIALBRK_BSDCOMPAT): Improve help text.

* arch/arm/src/stm32l4/Kconfig
  (STM32L4_SERIALBRK_BSDCOMPAT): Improve help text.

* arch/arm/src/stm32l5/Kconfig
  (STM32L5_SERIALBRK_BSDCOMPAT): Improve help text.

* arch/arm/src/stm32u5/Kconfig
  (STM32U5_SERIALBRK_BSDCOMPAT): Improve help text.

* arch/arm/src/stm32wb/Kconfig
  (STM32WB_SERIALBRK_BSDCOMPAT): Improve help text.
2023-02-01 10:58:34 +08:00
Lucas Saavedra Vaz
f07885541c arch/xtensa/esp32: Propagate RTC IRQ status register to lower levels 2023-02-01 00:45:52 +08:00
Xiang Xiao
9f027208d4 fs: Add model field to geometry and mtd_geometry_s
the model is very useful to track the device info

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-31 11:50:28 -03:00
Jukka Laitinen
4f957f8031 arch/arm/src/lc823450/lc823450_i2c.c: Remove extra rounding after MSEC2TIC change to round up
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-01-31 22:42:29 +08:00
Jukka Laitinen
05eb8541d1 Revert "arch/arm/src/stm32f7/stm32_i2c.c: Round up stm32_i2c_toticks return value"
This reverts commit fe6f6870dcc431cecf0fa94187cff05ec040cf47.
2023-01-31 22:42:29 +08:00
Xiang Xiao
55679aec5f drivers/camera: Support the private data for imgsensor and imgdata
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-31 08:04:39 +01:00
David Vosahlik
372fee9412 Added SocketCAN driver implementation to the tiva chip, modified the EK-TC1294XL launchpad board to use the new SocketCAN API 2023-01-31 14:07:23 +08:00
yinshengkai
3f97a87162 tools: add separate flags parameter for COMPILE/COMPILEXX
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-01-31 13:42:33 +08:00
Huang Qi
570c7587c7 risc-v/Toolchain.defs: Correct indent 2023-01-31 11:19:47 +08:00
Zhe Weng
d3dd349649 net: Implement shutdown() for usrsock
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
2023-01-31 11:15:01 +08:00
lilei19
1d8af7e105 add holder for mutex
Signed-off-by: lilei19 <lilei19@xiaomi.com>
2023-01-31 12:08:05 +09:00
Nathan Hartman
6b89b6f945 Remove executable permissions from source files
* arch/arm/src/sama5/sam_flexcom_spi.h,
  arch/risc-v/src/mpfs/mpfs_ihc_sbi.c,
  drivers/usbdev/adb.c,
  libs/libc/math/lib_scalbn.c,
  libs/libc/math/lib_scalbnf.c,
  net/ipfrag/Make.defs,
  net/ipfrag/ipfrag.c,
  net/ipfrag/ipfrag.h,
  net/ipfrag/ipv4_frag.c,
  net/ipfrag/ipv6_frag.c: Remove executable permission.
2023-01-30 20:34:51 -03:00
Nathan Hartman
f63754c4c0 arch/tiva: Remove dead store
* arch/arm/src/tiva/common/tiva_can.c:
  (tiva_can_initialize): Remove the local variable 'canmod', which was
   assigned but never used.
2023-01-31 01:36:09 +08:00
chao an
0f35ad29a8 arm/unwinder: set default unwinder type to arm exidx/extab
Signed-off-by: chao an <anchao@xiaomi.com>
2023-01-31 00:38:42 +08:00
Jiuzhu Dong
17f410e647 arch/sim: add toolchain library libm
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2023-01-30 20:32:14 +08:00
rajvinder kaur
2b30f17607 stm32h7: socket CAN error handling. 2023-01-30 11:22:49 +08:00
pengyiqiang
0443889124 sim_framebuffer: fix fb_pollnotify not called
Signed-off-by: pengyiqiang <pengyiqiang@xiaomi.com>
2023-01-29 17:34:36 -03:00
ligd
9e39600c83 arch: fix sim_x11events calls but sim_x11initialize() hasn't ready
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-01-29 17:34:36 -03:00
chao an
82520c0006 arm/itm_syslog: remove invaild select config
1. CONFIG_SYSLOG has been removed by Nutt on below commit:

| commit c5ac473bc0
| Author: Gregory Nutt <gnutt@nuttx.org>
| Date:   Tue Jun 21 07:58:42 2016 -0600
|
|     SYSLOG: Remove an obsolete, unused configuration item from Kconfig file

2. Fix comile warning

| armv7-m/arm_itm_syslog.c: In function 'itm_syslog_initialize':
| armv7-m/arm_itm_syslog.c:183:18: warning: passing argument 1 of 'syslog_channel' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
|   183 |   syslog_channel(&g_itm_channel);
|       |                  ^~~~~~~~~~~~~~
| In file included from armv7-m/arm_itm_syslog.c:29:
| nuttx/syslog/syslog.h:155:49: note: expected 'struct syslog_channel_s *' but argument is of type 'const struct syslog_channel_s *'
|   155 | int syslog_channel(FAR struct syslog_channel_s *channel);
|       |

Signed-off-by: chao an <anchao@xiaomi.com>
2023-01-29 19:54:55 +08:00
zhangyuan21
e6d2f0623a backtrace: use CURRENT_REGS when in interrupt context
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-01-29 02:48:00 -08:00
qinwei1
b989e4f3a6 arch:arm64: add support for nuttx arm64 Toolchain Selection
Summary:
1. to enable Toolchain select Kconfig option, making something depend on
   the opton to be configured with menuconfig

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-01-29 14:37:16 +08:00
zhanghongyu
4ea43f2df2 sim: init events field when send ack/dack
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2023-01-29 14:34:09 +08:00
chao an
cc7dc89c64 arch/sim: fix undefined reference to `usrsock_event_callback'
/usr/bin/ld: sim_hostusrsock.o: in function `host_usrsock_loop':
arch/sim/src/sim/posix/sim_hostusrsock.c:514: undefined reference to `usrsock_event_callback'

Signed-off-by: chao an <anchao@xiaomi.com>
2023-01-29 14:33:37 +08:00
Xiang Xiao
7d66a16c53 Minor style clean up
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-28 19:53:20 +02:00
Jukka Laitinen
7d54d04613 arch/arm/src/stm32f7/stm32_i2c.c: Round up stm32_i2c_toticks return value
When sending small number of bytes with larger CONFIG_USEC_PER_TICK
this function should return at least 1. Solve this by rounding
up the result.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-01-28 12:11:33 -03:00
Xiang Xiao
964a41283c arm/tlsr82: Fix warning: "IC_TAG_CACHE_ADDR_EQU_EN" is not defined
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-28 11:30:33 -03:00
Xiang Xiao
ac3a667860 Fix chip/intel64_handlers.c:136: error: "SIGFPE" redefined [-Werror]
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-27 13:21:49 -03:00
Ville Juven
42d0e356c2 arch/addrenv: Change group_addrenv_t to arch_addrenv_t
This is preparation for moving address environments out of the group
structure into the tcb.

Why move ? Because the group is destroyed very early in the exit phase,
but the MMU mappings are needed until the context switch to the next
process is complete. Otherwise the MMU will lose its mappings and the
system will crash.
2023-01-27 23:17:01 +08:00
Max Kriegleder
8c465a64b9 stm32h7: add lower half timer driver 2023-01-27 13:29:10 +08:00
Alan Carvalho de Assis
e0cb643545 Update arch/xtensa/src/esp32s3/esp32s3_rng.c
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-01-27 13:16:35 +08:00
Alan Carvalho de Assis
2d635be05f Update arch/xtensa/src/esp32s3/esp32s3_rng.c
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-01-27 13:16:35 +08:00
Alan Carvalho de Assis
b27351828a esp32s3: Add RNG driver
Fix multiplier noticed by Tiago

Co-author: Tiago Medicci <tiago.medicci@espressif.com>
2023-01-27 13:16:35 +08:00
Gustavo Henrique Nihei
80bbb0f24c esp32c3: Fix IRQ initialization, it was crashing on DEBUG_ASSERTIONS
Co-author: Alan C. Assis <alan.carvalho@espressif.com>
2023-01-27 13:15:39 +08:00
qiaohaijiao1
adba1e5e19 arch/sim: ignore return value of snd_pcm_pause/resume
snd_pcm_pause, snd_pcm_resume failed with -5, -38 errno.

Signed-off-by: qiaohaijiao1 <qiaohaijiao1@xiaomi.com>
2023-01-27 01:10:15 +02:00
qiaohaijiao1
05a12ba69e sim/sim_alsa: register pcm1p/pcm1c audio device.
use pcm1p/pcm1c to simulate offload playback/capture.

Signed-off-by: qiaohaijiao1 <qiaohaijiao1@xiaomi.com>
2023-01-27 01:10:15 +02:00
ligd
d17b6fa58b sim/alsa: don't let siwtch out when open alsa
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-01-27 01:10:15 +02:00
chao an
931a4f6969 arch/EXTRA_LIBS: link all staging library
Signed-off-by: chao an <anchao@xiaomi.com>
2023-01-27 01:08:26 +02:00
chao an
d031989e0e arch/arm: make DSP arch extension configurable
Signed-off-by: chao an <anchao@xiaomi.com>
2023-01-26 22:39:30 +02:00
Lucas Saavedra Vaz
eee4396b06 arch/xtensa/esp32: Add support for touch pad interruptions 2023-01-26 14:33:08 -03:00
Lucas Saavedra Vaz
c4aa37ee2f arch/xtensa: Fix 'interruption' typos 2023-01-26 14:33:08 -03:00
Lucas Saavedra Vaz
07fd4b564d arch/xtensa/esp32: Fix SENS_TOUCH_XPD_WAIT definition 2023-01-26 14:33:08 -03:00
zhuyanlin
3c6b844fcd arch:xtensa:toolchain: add -Wno-atmoic-alignment flags for xcc
see a bug here:
https://bugs.llvm.org/show_bug.cgi?id=43603

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2023-01-26 17:11:54 +02:00
Ville Juven
686b990a85 arch/ARCH_KERNEL_STACK: Fix signal handling with kernel stack
There were two issues with signal handling:
- With a kernel stack the "info" parameter was passed from kernel memory.
  This is fixed by making a stack frame to the user stack and copying it
  there.
- If the signal handler uses a system call, the kernel stack was completely
  and unconditionally destroyed, resulting in a crash in the user application

There is also no need to check ustkptr, it is always NULL. Why ? Because
signal delivery is deferred when a system call is being executed.
2023-01-26 20:41:42 +08:00
Petro Karashchenko
a58e73add8 arch/arm/tiva: simplify TIVA_CAN option usage
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-01-26 10:26:09 +08:00
Petro Karashchenko
bd7cb522a1 nuttx: use TABs instead of spaces in Kconfig files
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-01-26 10:26:09 +08:00
Petro Karashchenko
c4cf1eeb2b arch/xtensa/esp32s2: switch from semaphore to mutex for exclusive access
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-01-26 10:24:05 +08:00
Petro Karashchenko
c415ce518f arch/xtensa/esp32: style fixes in SPI driver
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-01-26 10:24:05 +08:00
Petro Karashchenko
f952b8456c assert: switch from ASSERT(0/false) to PANIC
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-01-26 10:15:34 +08:00
Michael Jung
eaea60a575 armv8-m: Fix pthread_start syscall
The 'arg' parameter is in R3, not in R2.

Signed-off-by: Michael Jung <michael.jung@secore.ly>
2023-01-26 04:02:19 +08:00
Petro Karashchenko
be10056702 arch/arm/samv7: fix issue when AFEC1 driver failed to open second time
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-01-26 01:26:41 +08:00
Xiang Xiao
d7ee492fc4 board/arch: Remove FAR decorator
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-25 13:05:07 +02:00
Stuart Ianna
34fdc3da0d litex: Allow custom peripheral memory mapping and IRQ. 2023-01-25 14:11:06 +08:00
Xiang Xiao
43e7b13697 assert: Log the assertion expression in case of fail
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-24 15:00:19 -03:00
Ville Juven
9b88f8ea5c riscv/riscv_exception.c: Print the EPC value always
The value printed by assert() cannot always be trusted to be correct,
as it relies on the stack / stack pointer not being corrupt.

The CPU register always points to the faulting instruction so print it
out in the exception handler.
2023-01-25 00:55:07 +08:00
Stuart Ianna
f49c20d28f litex: System clock frequency selectable from Kconfig. 2023-01-24 08:20:16 +01:00
Gustavo Henrique Nihei
e77e12e145 espressif: Stabilize MCUboot support on Espressif chips
MCUboot support is no longer behind EXPERIMENTAL for the following
chips:
- ESP32
- ESP32-S2
- ESP32-S3
- ESP32-C3

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-01-24 08:44:22 +09:00
David Sidrane
15462f3e7a s32k1xx:serial Do not use TC use TDRE & TIE 2023-01-24 06:47:21 +08:00
raiden00pl
aa7d4b40c1 stm32/foc: move the warning in the right place - should be in stm32f7 2023-01-24 00:44:41 +08:00
raiden00pl
bfdb7f8909 stm32f7,stm32/foc: support for BEMF sensing
stm32 version tested with b-g431b-esc1
stm32f7 version not tested on HW
2023-01-22 12:58:04 -03:00
raiden00pl
01d84408e6 stm32,stm32f7/adc: add interface to configure multi mode ADC 2023-01-22 12:58:04 -03:00
raiden00pl
f3fde0e9a8 stm32,stm32f7/foc: improve pwm_off 2023-01-22 12:58:04 -03:00
raiden00pl
bd6a0b08db stm32,stm32f7/foc: support for pwm_off() 2023-01-21 12:28:16 +08:00
Lucas Saavedra Vaz
39162ebafb arch/xtensa/esp32: Add support for RTC IRQs 2023-01-21 12:27:35 +08:00
raiden00pl
91d43edffd drivers/foc: support for BEMF sensing 2023-01-20 21:26:27 +02:00
Alan Carvalho de Assis
2bdb7c0e8d esp32s2: Add support to EFUSE 2023-01-20 15:41:13 +08:00
Alan Carvalho de Assis
adc5f52fcf esp32s3: Add support to EFUSE 2023-01-20 15:40:46 +08:00
Max Kriegleder
57034f483d esp32: fix lower half oneshot for usage with nxsched_oneshot_start 2023-01-20 15:39:47 +08:00
Jukka Laitinen
e2a7cee5ed arch/mpfs: Make selection of SBI boot or direct boot run-time configurable
Allow bootloader to select run-time whether the payload binary is booted with
SBI or directly by jumping to entrypoint address.

- Use just one bitmask to select sbi or direct boot for each hart
- Add mpfs_set_use_sbi function to allow selecting how to boot
- Initialize the bitmask by default according to the configuration flags
- Add a header file for including the function prototypes in bootloader code

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-01-20 00:08:51 +08:00
Xiang Xiao
fd64e38072 build: Add STACK_USAGE(-fstack-usage) to assist the stack analysis
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-19 10:35:20 -03:00
Masayuki Ishikawa
dc454765fb Revert "add holder for mutex"
This reverts commit fc176addeb.
2023-01-19 06:04:48 +09:00
Ville Juven
0922121bc0 riscv/addrenv: Do not free physical memory for SHM area
SHM area is just mapped memory, the physical backup is not owned by the
process, so the process must not free it.

In ARM this is already handled as the regions are destroyed one by one,
while this implementation does a page directory walk instead.
2023-01-18 21:59:55 +08:00
David
5dbd082fad Bugfix of typo in tiva_can.c 2023-01-18 12:15:53 +01:00
Gustavo Henrique Nihei
a4c9da9280 xtensa/esp32: Fix ESP32_SPIRAM_USER_HEAP under Protected mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-01-18 17:41:09 +08:00
Gustavo Henrique Nihei
e451b43798 xtensa/esp32: Improve Wi-Fi driver to support MM_KERNEL_HEAP
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-01-18 17:41:09 +08:00
Gustavo Henrique Nihei
705e29fb27 xtensa/esp32: Support allocation of userspace heap into External RAM
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-01-18 17:41:09 +08:00
lilei19
fc176addeb add holder for mutex
Signed-off-by: lilei19 <lilei19@xiaomi.com>
2023-01-18 17:40:58 +08:00
Zhe Weng
1cf3147626 net/netdev: Avoid hardcoded guardsize when using d_iob
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
2023-01-18 14:41:07 +08:00
Dong Heng
f35f32d4ee xtensa/esp32: Fix SPI bugs
1. Fix SPI master/slave clock init/deinit error
2. Fix SPI slave RX process error
2023-01-18 12:23:08 +08:00
Ville Juven
201a55c7cb arm/addrenv_utils: Don't touch L1 mappings in addrenv_destroy()
This is unnecessary, the address environment is getting wiped anyway,
there is no need to remove the L1 references because they will get
wiped when the page directory is changed
2023-01-18 11:02:19 +08:00
Ville Juven
58b5a0412e riscv/addrenv_shm: Add missing sanity check to up_shmdt()
A missing sanity check, make sure the last level page table actually exists
before trying to clear entries from it.
2023-01-18 02:45:04 +08:00
anjiahao
bc30b294aa mm:add heap args to mm_malloc_size
use malloc_size inside of where used mm_malloc_size

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-01-17 21:57:37 +08:00
dongjiuzhu1
8101978765 arch/sim: fix compile break when using mallinfo_task with custom mm manager
/usr/bin/ld: nuttx.rel: in function `mallinfo_task':
nuttx/mm/umm_heap/umm_mallinfo.c:67: undefined reference to `mm_mallinfo_task'

Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-01-17 16:48:30 +08:00
luoyong1
a32124879d arch/arm/src/armv7-a/r: fix kconfig error of l2 cache latency
fix the error of the config name and set latency config param bool to int

Signed-off-by: luoyong1 <luoyong1@xiaomi.com>
2023-01-17 12:45:42 +09:00
Xiang Xiao
62c5afe655 Fix warning in file included from chip/sam_clockconfig.c:34:
chip/sam_clockconfig.c: In function 'sam_usbclockconfig':
Error: /github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:51: error: 'regval' is used uninitialized [-Werror=uninitialized]
  135 | #define putreg32(v,a)  (*(volatile uint32_t *)(a) = (v))
      |                                                   ^
chip/sam_clockconfig.c:422:12: note: 'regval' was declared here
  422 |   uint32_t regval;
      |            ^~~~~~

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-16 18:59:44 -03:00
ligd
fedad91b0d sim/mem: don't let siwtch out when operated the host mem
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-01-17 01:18:03 +08:00
ligd
c08cc01c9d sim/oneshot: don't need sleep_until when open CONFIG_SIM_WALLTIME_SIGNAL
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-01-17 01:18:03 +08:00
Xiang Xiao
f64da13e9b libxx: Add CXX_STANDARD to select -std=c++??
and default to "c++17"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-16 15:41:57 +02:00
TimJTi
6b4da4ad6e Ensure SFR CKTRIM register correctly set, SAMA5D2/D3 only 2023-01-16 21:40:00 +08:00
Dong Heng
118222ba46 xtensa/esp32: Partition device supports encryption mode 2023-01-16 09:55:44 -03:00
dongjiuzhu1
7cd325f3be mm/mm_heap: remove kasan in MM_ADD_BACKTRACE
do simple copy to instead of memset and memcpy operation because
they have been instrumented, if you access the posion area,
the system will crash.

Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-01-16 20:32:17 +08:00
chao an
415a09115d boards/sim/windows: enable custom options
1. boards/sim: enable child status
2. boards/sim/windows: enable custom options
3. sim/windows: enable hostfs

Signed-off-by: chao an <anchao@xiaomi.com>
2023-01-16 20:30:39 +08:00
zhangyuan21
806a2a8b8d arch/armv7-ar: flush dcache when addr is not aligned with cache line
When invalidate address is not aligned with cache line,
must align address and flush the cache line.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-01-16 16:14:32 +08:00
zhangyuan21
4bb155db64 arch/arm: add barrier instruction for cache ops
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-01-16 16:14:32 +08:00
Xiang Xiao
f783f5c384 arch/arm: Fix typo error in cp15_cacheops.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-16 16:14:32 +08:00
Xiang Xiao
1ea9db4ebe Fix error: implicit declaration of function 'cp15_invalidate_icache'; did you mean 'cp15_invalidate_dcache'?
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-16 16:14:32 +08:00
chenrun1
c61195bcc9 arch/armv7-a & armv7-r:Add invalidate icache behavior
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2023-01-16 16:14:32 +08:00
ligd
7e4c5d3daa armv7a/r: cache function should depends on CONFIG_ARCH_XCACHE
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-01-16 16:14:32 +08:00
Julian Oes
22fa59074f stm32h7: add SMPS PWR option for STM32H7X7
The dual core STM32H747 / STM32H757 there is an additional option to
select SMPS rather than LDO as the power selection.

This commit adds this option to the STM32H747 config and the
stm32h7x7xx source.

Signed-off-by: Julian Oes <julian@oes.ch>
2023-01-16 13:31:23 +08:00
zhangyuan21
fc623949a3 arch/arm: move hard code macro to kconfig
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-01-16 13:31:04 +08:00
luoyong1
6975bbb38d arch/arm/src: add pl310 l2cache's kconfig for latency
Signed-off-by: luoyong1 <luoyong1@xiaomi.com>
2023-01-16 13:31:04 +08:00
Alan Carvalho de Assis
97402f9121 esp32: Fix QEnconder reset position and small typo
The PCNT RST bit needs to be set to zeroing the counter and then
this same bit needs to be cleared to returning counting.
2023-01-16 09:41:46 +08:00
Jukka Laitinen
f9c8b4015f Revert "arch: Don't free the context if the reference doesn't equal zero"
struct stm32_i2c_inst_s instance is allocated on every call to
stm32_i2cbus_initialize, and that instance is supposed to be deleted on every
call to stm32_i2cbus_uninitialize.

The "refs" counter just keeps track on when the last one is deleted, and
everything is unregisterd/disabled.

This reverts commit 8098c80338.
2023-01-15 19:52:05 +08:00
ssssenai
077ad5b45f arch: xtensa/esp32: Add esp32_himem_chardev.c
Summary:
- It is applicable to esp32 products and uses the himem part
  of 8M psram by creating character devices.

Impact:
- None

Testing:
- Use esp32-wrover series products for more than 1000 functional verifications.
2023-01-14 14:07:46 +08:00
Janne Rosberg
246a677045 sama5/sam_flexcom_spi: enable DMA support 2023-01-14 13:40:14 +08:00
Janne Rosberg
f6d164bf9d sama5/dmac: add defines for ATSAMA5D2
This allows xdma to be used on SAMA5D2x chips
2023-01-14 13:40:14 +08:00
ptr_b
890f9ad2ed arch/sim: add arch/math.h
To avoid introducing __GLIBC__ symbol which may affect others

Signed-off-by: ptr_b <bijunda1@xiaomi.com>
2023-01-13 23:09:47 +08:00
W-Mai
bcb0abc05d sim/posix/sim_linuxspi.c: fix select not work and incorrect behaviour
Fixed missing `SPI_SELECT` method and incorrect sending behavior in sim_linuxspi

Signed-off-by: xinbingnan <xinbingnan@xiaomi.com>
2023-01-13 15:32:13 +08:00
Petro Karashchenko
45ed6f657c arch/arm/cxd56xx: do not clear enabled callback event on card insertion
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-01-13 12:18:36 +08:00
dongjiuzhu1
cf987238c0 sim/hci: add depends on config for SIM_HCISOCKET to fix compile break
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-01-13 02:21:34 +08:00
Jukka Laitinen
70de321de3 arch/Kconfig: remove virtual memory allocator dependency from MM_SHM
The dependency should be vice versa; the MM_SHM should depend on the
existence of the virtual memory range allocator.

Create a new CONFIG flag CONFIG_ARCH_VMA_MAPPING, which will define that
there is a virtual memory range allocator. Make MM_SHM select that flag

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-01-13 02:20:13 +08:00
Lucas Saavedra Vaz
674b480198 arch/xtensa/esp32s2: Add initial support for touch pad polling 2023-01-12 22:23:42 +08:00
Lucas Saavedra Vaz
749d0dfe84 arch/xtensa/esp32s2: Add RTC GPIOs configuration functions 2023-01-12 22:23:42 +08:00
Lucas Saavedra Vaz
cdd0787b54 arch/xtensa/esp32: Fix typo and check PU/PD registers 2023-01-12 22:23:42 +08:00
Lucas Saavedra Vaz
3dad6b273e arch/xtensa/esp32s2: Add missing SENS and RTCCNTL registers 2023-01-12 22:23:42 +08:00
xinbingnan
383458c64e sim/Kconfig: move some i2c,spi configs from board to arch
Move `SIM_I2CBUS_ID` and `SIM_SPIDEV_NAME` from board to arch.
This allows you not to rely on board configuration.

Signed-off-by: xinbingnan <xinbingnan@xiaomi.com>
2023-01-11 17:28:43 +08:00
Lucas Saavedra Vaz
2b7d8981e2 arch/xtensa/esp32s3: Add initial support for touch pad polling 2023-01-11 02:00:41 +08:00
Lucas Saavedra Vaz
24995f6918 arch/xtensa/esp32s3: Add RTC GPIOs configuration functions 2023-01-11 02:00:41 +08:00
Lucas Saavedra Vaz
c8dd4b068d arch/xtensa/esp32s3: Add missing registers and definitions 2023-01-11 02:00:41 +08:00
Dong Heng
07342f7957 xtensa/esp32: SPI support to configure as R/W/RW mode 2023-01-11 01:54:36 +08:00
raiden00pl
88dd705d27 stm32/stm32f7 CANv1: protect TX buffer during CAN error frame generation
Follow up to eb240e0 (PR #8060)
2023-01-11 01:53:49 +08:00
chao an
eef818e51f risc-v/esp32c3: correct receive buffer size
1. correct receive buffer size, d_len should keep the l2 header size
2. fix race condition issue of de/enqueue rx queue

Signed-off-by: chao an <anchao@xiaomi.com>
2023-01-10 11:28:06 -03:00
Carlos Sanchez
eb240e014c stm32: protect TX buffer during CAN error frame generation. 2023-01-10 13:33:35 +08:00
Petro Karashchenko
5f92c62874 boards/cxd56xx/spresense: add fs automount driver for SD Card
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-01-10 10:39:23 +09:00
Carlos Sanchez
78248183aa s32k1xx: reserve MSG_DATA extra space only when needed by config. 2023-01-09 21:06:56 +02:00
Carlos Sanchez
3c6d45fa99 s32k1xx: avoid buffer overflow when CAN time is used for non-FD CAN.
s32k1xx: fix initialization of MAXMB field in MCR.
2023-01-09 21:06:56 +02:00
Dong Heng
67ccee2c4f xtensa/esp32: ESP32 SPI Flash encryption supports 16-bytes align writing 2023-01-10 01:10:10 +08:00
Sergey Nikitenko
e0f99d93ac stm32wb: add i2c driver 2023-01-09 09:27:17 +08:00
chenwen@espressif.com
eed2cce3f2 xtensa/esp32: Optimize WLAN device buffer 2023-01-07 13:46:37 +08:00
chenwen@espressif.com
933d1a0a80 xtensa/esp32: Add Wi-Fi softap event 2023-01-06 12:25:36 -03:00
Dong Heng
f137a7b552 xtensa/esp32: Fix macro "CONFIG_NETDEV_IOCTL" control range error 2023-01-06 20:40:53 +08:00
Dong Heng
7097cfd000 xtensa/esp32: Add option to enable ETH PHY reset pin 2023-01-06 20:40:53 +08:00
Lee Lup Yuen
6d70b91a55 arm64/a64: Fix PIO Interrupt
The current implementation of PIO Interrupt for Allwinner A64 is incomplete. This PR fixes the implementation of PIO Interrupt for all supported PIO Ports (PB, PG and PH).

### Modified Files

`arch/arm64/src/a64/a64_pio.c`, `a64_pio.h`: Add implementation of PIO Interrupt

`arch/arm64/include/a64/irq.h`: Add IRQ for PIO Port PH

`arch/arm64/src/a64/hardware/a64_pio.h`: Fix addresses of PIO Interrupt Registers
2023-01-06 13:43:44 +08:00
yinshengkai
4752dcd12a arch/stm32: Initialize up_perf after system boot
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-01-06 13:32:12 +08:00
anjiahao
172d467c26 arch:add faultmask register operation to armv7-m & armv8-m
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-01-05 23:17:43 +02:00
anjiahao
c02fea36d8 arch:change tcbinfo regs num
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-01-05 23:36:12 +08:00
gaojiawei
1486600d7d sim: Fix make tool doesn't rebuild dependencies of the libboard target
Signed-off-by: gaojiawei <gaojiawei@xiaomi.com>
2023-01-05 22:27:00 +08:00
Xiang Xiao
b0a0ba3ad7 fs: Move mmap callback before truncate in [file|mountpt]_operations
since mmap may exist in block_operations, but truncate may not,
moving mmap beforee truncate could make three struct more compatible

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-04 17:43:59 +02:00