- Add retry timeout to prevent inifinite loop
- Change the register operation of power control
- Add exclusive control by semaphore into some functions
- Add short delay until power control is reflected
This commit enhances ADC and PWM drivers with option to trigger ADC
conversion with events generated by PWM comparison units.
The generation of PWM events is handled by comparison units set up from
Kconfig option SAMV7_PWMx_TRIGn. ADC triggering from PWM can be selected
by AFECn_PWMTRIG option.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
SAMv7 PWM driver supports complementary PWM output if both pins (H and L)
are defined and configured. This commit adds a configuration option to
configure the complementary L pin.
The pin definition has to be provided by board level support.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Summary:
- I noticed that there are two kinds of descriptors for imxrt_enet.c
- The first one is the legacy descriptor and its size is 8bytes.
- The second one is the enhanced descriptor and its size is 32bytes.
- In both cases, we can not use a descriptor chain like stm32.
- Considering cache line alignment, the second one is perfect because
one descriptor fits the Cortex-M7 cache line which would fix networking
stability issues in d-cache write-back mode.
Impact:
- imxrt ethernet in d-cache write-back mode
Testing:
- Tested with ixmrt1060-evk:netnsh_dcache_wb (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that CONFIG_IMXRT_ENET_ENHANCEDBD is not correctly
used though it is defined in Kconfig.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with imxrt1060-evk:netnsh_dcache_wb (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This reverts commit 62c15c03d3.
Fix warning: the choice symbol STM32_FLASH_CONFIG_G (defined at arch/arm/src/stm32/Kconfig:1275) is selected by the following symbols, but select/imply has no effect on choice symbols
- ARCH_CHIP_STM32F412ZG (defined at arch/arm/src/stm32/Kconfig:1014)
Generic drivers shoud not use architecture related config options like
CONFIG_SAMV7_PWM. This commit adds PWM pin overwrite under generic
configuration option CONFIG_PWM_OVERWRITE.
Now the overwrite can be used on other architectures as well or can be
completely disabled for SAMv7.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Commit d07792a caused a build error in sam_mcan.c file. This commit fixes
the build. The file now succesfully compiles and CAN works.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
In the lower half UART driver for PIC32MZ architecture, adding the
TIOCxBRK ioctl calls, which allow an application to transmit a UART
line BREAK signal.
This architecture does not support BSD-style BREAK in hardware so our
implementation follows the precedent set in STM32, GD32, and Kinetis
architectures: By default, if only PIC32MZ_UART_BREAKS is configured,
we produce the hardware-native BREAK, which lasts for 12 bit lengths;
if, in addition, PIC32MZ_SERIALBRK_BSDCOMPAT is configured, we
generate a BSD-style BREAK by putting the TX pin in GPIO mode and
driving it low "manually" until told to stop.
* arch/mips/src/pic32mz/Kconfig
(config PIC32MZ_UART_BREAKS): New. Appears as
CONFIG_PIC32MZ_UART_BREAKS in code.
(config PIC32MZ_SERIALBRK_BSDCOMPAT): New. Appears as
CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT in code.
* arch/mips/src/pic32mz/hardware/pic32mz_pps.h
(__PPS_OUTPUT_REGADDR_TO_GPIO, PPS_OUTPUT_REGADDR_TO_GPIO): New
macros to automatically determine the GPIO port and pin from the
corresponding PPS (Peripheral Pin Select) define. Since there is a
one-to-one correspondence between PPS output mappings and a single
port and pin, these macros avoid writing redundant pin mappings. We
use this when switching the TX pin from UART to GPIO to generate
the BREAK and we could use it in other peripheral drivers in the
future to override hardware behavior.
* arch/mips/src/pic32mz/pic32mz_serial.c
(struct up_dev_s): Add new field 'brk' to indicate line break in
progress when built with PIC32MZ_UART_BREAKS. If generating BSD-
compatible BREAKs, also add tx_gpio, tx_pps_reg, and tx_pps_val, to
let us toggle the pin between UART and GPIO modes.
(up_ioctl): Add cases for TIOCSBRK and TIOCCBRK to turn BREAK on and
off, with both hardware-native and BSD-compatible implementations.
This is similar to the STM32F7 implementation.
(up_txint): Block enabling TX interrupt if line break in progress.
This is similar to the STM32F7 implementation.
Updating Simulator for macOS
macOS requires genromfs and X11 Libraries to run Simulators.
* Added instructions to install genromfs
* Added instructions to install X11
Adding Xorg Server
The linker was unable to identify the location of X11 libraries.
removed -L/opt/X11/lib from ln 145
Updating Changes to streamline with other Hosts
The PIC32MZ architecture provides a Peripheral Pin Select (PPS) which
allows mapping peripherals to different GPIO pins. To map a peripheral
output, a value is programmed to a register called RPnxR, where n is
the GPIO port (A thru K) and x is the GPIO pin (0 thru 15). The names
of these registers in code are PIC32MZ_RPnxR. However, in various
definitions, these were mistakenly written as PI32MZ_RPnxR (missing C
in PIC32). This prevents using any of the affected mappings. This
issue is fixed by repairing the define names.
* arch/mips/src/pic32mz/hardware/pic32mzec_pps.h,
arch/mips/src/pic32mz/hardware/pic32mzef_pps.h:
(): s/PI32MZ/PIC32MZ/g
The defines for Peripheral Pin Select (PPS) register RPE5R were called
RPE4R inadvertently; however, mappings elsewhere in the file used the
correct name of RPE5R, so the build would break if anyone attempted to
map those peripherals to GPIO pin E5. This issue is now fixed.
* arch/mips/src/pic32mz/hardware/pic32mzec_pps.h,
arch/mips/src/pic32mz/hardware/pic32mzef_pps.h:
(PIC32MZ_RPE4R_OFFSET): Rename to PIC32MZ_RPE5R_OFFSET.
(PIC32MZ_RPE4R): Rename to PIC32MZ_RPE5R.
When I checked how this register was set I discovered that 128 was not
accepted by the H7 but 64 was ok. Looking at the STM32Cube's HAL it
seems to be only 64 words long, however, the reference manual claims
otherwise.
I have opened a discussion on the ST community forum
https://community.st.com/s/question/0D73W000001nzqFSAQ
but unfortunately not received an answer yet.
In the meantime, I think, we should update this to what I found to be
working though.
Signed-off-by: Julian Oes <julian@oes.ch>
user_main: vfork() test
=================================================================
==3754757==ERROR: AddressSanitizer: stack-buffer-underflow on address 0xae9126f0 at pc 0x56845661 bp 0xae912570 sp 0xae912560
READ of size 1 at 0xae9126f0 thread T0
#0 0x56845660 in memcpy string/lib_memcpy.c:44
#1 0x56b70f61 in up_vfork sim/sim_vfork.c:133
#2 0x567c0b85 in vfork (/home/ligd/platform/sim/nuttx/nuttx+0x26bb85)
0xae9126f0 is located 73456 bytes inside of 73728-byte region [0xae900800,0xae912800)
allocated by thread T0 here:
#0 0xf7ab1c2f in __interceptor_posix_memalign ../../../../../src/libsanitizer/asan/asan_malloc_linux.cpp:226
SUMMARY: AddressSanitizer: stack-buffer-underflow string/lib_memcpy.c:44 in memcpy
Signed-off-by: ligd <liguiding1@xiaomi.com>
Current implementation supports the trigger generation only from timer
capture on period value. This is sufficient for PWM synchronization but
may not be enough for other purposes as ADC triggering for example.
This change adds an option to generate the trigger based on a duty
cycle value.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
The function call dac_txdone(&g_dac1dev) was not contained in ifdef
section. This was cousing compilation error if only DAC1 was configured
as the structure g_dac1dev is defined only if DAC0 is used.
This commit fixes the error and ensures the function is called only if
corresponding DAC is configured.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
First decoupling changes related to CMAKE
BINDIR/APPSBINDIR:
Output path of Kconfig which dynamically generated by NuttX Kernel/Apps
This option is consistent with the TOPDIR/APPSDIR by default, and will
be changed when out-of-tree compilation is supported
Signed-off-by: chao an <anchao@xiaomi.com>
sim/sim_doirq.c: In function 'sim_doirq':
Error: sim/sim_doirq.c:79:10: error: function may return address of local variable [-Werror=return-local-addr]
79 | return regs;
| ^~~~
sim/sim_doirq.c:44:14: note: declared here
44 | xcpt_reg_t tmp[XCPTCONTEXT_REGS];
| ^~~
Signed-off-by: ligd <liguiding1@xiaomi.com>
Previously, it was impossible to build for PIC32MZ architecture with
CONFIG_SERIAL_TERMIOS because it introduced compiler errors in the
lower half driver.
Fixing the compiler errors and adding an implementation of the
TIOCSERGSTRUCT, TCGETS, and TCSETS ioctl calls.
* arch/mips/src/pic32mz/pic32mz_serial.c
(): Include nuttx/fs/ioctl.h, needed for the TIOCSERGSTRUCT, TCGETS,
and TCSETS defines.
(up_ioctl): Fix compile breakage. Implement TIOCSERGSTRUCT. Make
TCGETS return data bits, parity, and stop bits. Make TCSETS apply
changes to data bits, parity, and stop bits.
In the lower half UART driver for Tiva architecture (TM4C12x), adding
the TIOCxBRK ioctl calls, which allow an application to transmit a BSD
compatible line BREAK. TIOCSBRK starts the BREAK and TIOCCBRK ends it.
This architecture supports BSD-style BREAK in hardware. We write to
the BRK bit (bit 0) of the UART Line Control register (UARTLCRH) to
start the BREAK, which begins after the UART finishes shifting out the
current character in progress, if any, including its stop bit(s), and
continues indefinitely until we write to the BRK bit again to stop the
BREAK.
* arch/arm/src/tiva/Kconfig
(config TIVA_UART_BREAKS): New. Appears as CONFIG_TIVA_UART_BREAKS
in code.
* arch/arm/src/tiva/common/tiva_serial.c
(struct up_dev_s): Add new field 'brk' to indicate line break in
progress when built with CONFIG_TIVA_UART_BREAKS.
(up_ioctl): Add cases for TIOCSBRK to turn BSD-compatible break on
unconditionally and TIOCCBRK to turn break off unconditionally.
(up_txint): Block enabling TX interrupt if line break in progress.
This is similar to the STM32F7 implementation.
(0)Allocating 3 bytes aligned to 0x00000001
=================================================================
==1461685==ERROR: AddressSanitizer: invalid alignment requested in posix_memalign: 1, alignment must be a power of two and a multiple of sizeof(void*) == 4 (thread T0)
#0 0xf7ab1c2f in __interceptor_posix_memalign ../../../../../src/libsanitizer/asan/asan_malloc_linux.cpp:226
Signed-off-by: ligd <liguiding1@xiaomi.com>
* arch/arm/src/tiva/common/tiva_serial.c:
(up_ioctl): PR #8406 (commit 1edec0aaa1) added support for
configuring the serial port's CTS/RTS flow control at runtime using
termios when built with CONFIG_SERIAL_TERMIOS and either or both of
CONFIG_SERIAL_OFLOWCONTROL and CONFIG_SERIAL_IFLOWCONTROL. However,
a runtime sanity check left over from before prevented this from
working: When processing ioctl TCSETS, we would return -EINVAL if
one or both of CCTS_OFLOW and CRTS_IFLOW were requested, which was
not deserved if the requested features were in fact supported.
Fixing the sanity check so it depends on features actually
configured.
The function is not relevant any longer, remove it. Also remove
save_addrenv_t, the parameter taken by up_addrenv_restore.
Implement addrenv_select() / addrenv_restore() to handle the temporary
instantiation of address environments, e.g. when a process is being
created.
There is currently a big problem in the address environment handling which
is that the address environment is released too soon when the process is
exiting. The current MMU mappings will always be the exiting process's, which means
the system needs them AT LEAST until the next context switch happens. If
the next thread is a kernel thread, the address environment is needed for
longer.
Kernel threads "lend" the address environment of the previous user process.
This is beneficial in two ways:
- The kernel processes do not need an allocated address environment
- When a context switch happens from user -> kernel or kernel -> kernel,
the TLB does not need to be flushed. This must be done only when
changing to a different user address environment.
Another issue is when a new process is created; the address environment
of the new process must be temporarily instantiated by up_addrenv_select().
However, the system scheduler does not know that the process has a different
address environment to its own and when / if a context restore happens, the
wrong MMU page directory is restored and the process will either crash or
do something horribly wrong.
The following changes are needed to fix the issues:
- Add mm_curr which is the current address environment of the process
- Add a reference counter to safeguard the address environment
- Whenever an address environment is mapped to MMU, its reference counter
is incremented
- Whenever and address environment is unmapped from MMU, its reference
counter is decremented, and tested. If no more references -> drop the
address environment and release the memory as well
- To limit the context switch delay, the address environment is freed in
a separate low priority clean-up thread (LPWORK)
- When a process temporarily instantiates another process's address
environment, the scheduler will now know of this and will restore the
correct mappings to MMU
Why is this not causing more noticeable issues ? The problem only happens
under the aforementioned special conditions, and if a context switch or
IRQ occurs during this time.
Detach the address environment handling from the group structure to the
tcb. This is preparation to fix rare cases where the system (MMU) is left
without a valid page directory, e.g. when a process exits.
ld: warning: boards/arm/rp2040/raspberrypi-pico-w/scripts/raspberrypi-pico-flash.ld contains output sections; did you forget -T?
Signed-off-by: chao an <anchao@xiaomi.com>
common/arm_backtrace_unwind.c: In function 'up_backtrace':
common/arm_backtrace_unwind.c:626:27:
warning: assignment to 'long unsigned int' from 'uint8_t (*)[]'\
{aka 'unsigned char (*)[]'} makes integer from pointer without a cast [-Wint-conversion]
626 | frame.stack_top = &g_intstacktop;
|
In order to make compilation warnings and errors easier to be found out,
this commit will disable the printing of the compilation process as much
as possible, and also if you want to restore the log information of the
compilation process, please enable verbose build on command line:
$ make V=0
OR
$ make V=1
| V=0: Exit silent mode
| V=1,2: Enable echo of commands
| V=2: Enable bug/verbose options in tools and scripts
Signed-off-by: chao an <anchao@xiaomi.com>
NuttX kernel should not use the syscall functions, especially after
enabling CONFIG_SCHED_INSTRUMENTATION_SYSCALL, all system functions
will be traced to backend, which will impact system performance.
Signed-off-by: chao an <anchao@xiaomi.com>
This is a follow-up to PR #6548, which added UART CTS/RTS support for
Tiva (TI TM4C12x) microcontrollers. This follow-up makes it possible,
when termios support is enabled with CONFIG_SERIAL_TERMIOS and CTS/RTS
support is enabled with CONFIG_SERIAL_OFLOWCONTROL and/or
CONFIG_SERIAL_IFLOWCONTROL, to query whether CTS/RTS are on/off at
runtime by utilizing ioctl TCGETS and to turn CTS/RTS on/off at runtime
by utilizing ioctl TCSETS.
* arch/arm/src/tiva/common/tiva_serial.c
(up_set_format): Because this function is called from ioctl TCSETS to
modify UART settings, and that IOCTL now respects CCTS_OFLOW and
CRTS_IFLOW, move setting/clearing of Tiva UART's CTL register's RTSEN
and CTSEN bits here...
(up_setup): ...from here.
(up_ioctl): For TCGETS, populate CCTS_OFLOW and CRTS_IFLOW bits as
appropriate. For TCSETS, populate priv's oflow and iflow from
supplied CCTS_OFLOW and CRTS_IFLOW bits.
Thanks to Petro Karashchenko for review and suggested fixes.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
The lower-half serial driver for Tiva (TI TM4C12x) microcontrollers supports
termios, but Kconfig never enabled this support because we were missing the
ARCH_HAVE_SERIAL_TERMIOS configs. This is now enabled, allowing termios support
to be enabled with CONFIG_SERIAL_TERMIOS.
* arch/arm/src/tiva/Kconfig
(config TIVA_UART0 thru TIVA_UART7): Select ARCH_HAVE_SERIAL_TERMIOS.
PWM driver for multiple peripherals supplied in gateware.
Only single channel frequency and duty cycle control is implemented. Pulse counting and multichannel features are not currently feasible.
Additions also include a new board configuration for arty-a7 which enables the PWM driver and example application.
Summary:
1. to enable Toolchain select Kconfig option, making something depend on
the opton to be configured with menuconfig
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
/usr/bin/ld: sim_hostusrsock.o: in function `host_usrsock_loop':
arch/sim/src/sim/posix/sim_hostusrsock.c:514: undefined reference to `usrsock_event_callback'
Signed-off-by: chao an <anchao@xiaomi.com>
When sending small number of bytes with larger CONFIG_USEC_PER_TICK
this function should return at least 1. Solve this by rounding
up the result.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This is preparation for moving address environments out of the group
structure into the tcb.
Why move ? Because the group is destroyed very early in the exit phase,
but the MMU mappings are needed until the context switch to the next
process is complete. Otherwise the MMU will lose its mappings and the
system will crash.
There were two issues with signal handling:
- With a kernel stack the "info" parameter was passed from kernel memory.
This is fixed by making a stack frame to the user stack and copying it
there.
- If the signal handler uses a system call, the kernel stack was completely
and unconditionally destroyed, resulting in a crash in the user application
There is also no need to check ustkptr, it is always NULL. Why ? Because
signal delivery is deferred when a system call is being executed.
The value printed by assert() cannot always be trusted to be correct,
as it relies on the stack / stack pointer not being corrupt.
The CPU register always points to the faulting instruction so print it
out in the exception handler.
MCUboot support is no longer behind EXPERIMENTAL for the following
chips:
- ESP32
- ESP32-S2
- ESP32-S3
- ESP32-C3
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Allow bootloader to select run-time whether the payload binary is booted with
SBI or directly by jumping to entrypoint address.
- Use just one bitmask to select sbi or direct boot for each hart
- Add mpfs_set_use_sbi function to allow selecting how to boot
- Initialize the bitmask by default according to the configuration flags
- Add a header file for including the function prototypes in bootloader code
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
SHM area is just mapped memory, the physical backup is not owned by the
process, so the process must not free it.
In ARM this is already handled as the regions are destroyed one by one,
while this implementation does a page directory walk instead.
This is unnecessary, the address environment is getting wiped anyway,
there is no need to remove the L1 references because they will get
wiped when the page directory is changed
/usr/bin/ld: nuttx.rel: in function `mallinfo_task':
nuttx/mm/umm_heap/umm_mallinfo.c:67: undefined reference to `mm_mallinfo_task'
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
do simple copy to instead of memset and memcpy operation because
they have been instrumented, if you access the posion area,
the system will crash.
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
When invalidate address is not aligned with cache line,
must align address and flush the cache line.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
The dual core STM32H747 / STM32H757 there is an additional option to
select SMPS rather than LDO as the power selection.
This commit adds this option to the STM32H747 config and the
stm32h7x7xx source.
Signed-off-by: Julian Oes <julian@oes.ch>
struct stm32_i2c_inst_s instance is allocated on every call to
stm32_i2cbus_initialize, and that instance is supposed to be deleted on every
call to stm32_i2cbus_uninitialize.
The "refs" counter just keeps track on when the last one is deleted, and
everything is unregisterd/disabled.
This reverts commit 8098c80338.
Summary:
- It is applicable to esp32 products and uses the himem part
of 8M psram by creating character devices.
Impact:
- None
Testing:
- Use esp32-wrover series products for more than 1000 functional verifications.
The dependency should be vice versa; the MM_SHM should depend on the
existence of the virtual memory range allocator.
Create a new CONFIG flag CONFIG_ARCH_VMA_MAPPING, which will define that
there is a virtual memory range allocator. Make MM_SHM select that flag
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Move `SIM_I2CBUS_ID` and `SIM_SPIDEV_NAME` from board to arch.
This allows you not to rely on board configuration.
Signed-off-by: xinbingnan <xinbingnan@xiaomi.com>
The current implementation of PIO Interrupt for Allwinner A64 is incomplete. This PR fixes the implementation of PIO Interrupt for all supported PIO Ports (PB, PG and PH).
### Modified Files
`arch/arm64/src/a64/a64_pio.c`, `a64_pio.h`: Add implementation of PIO Interrupt
`arch/arm64/include/a64/irq.h`: Add IRQ for PIO Port PH
`arch/arm64/src/a64/hardware/a64_pio.h`: Fix addresses of PIO Interrupt Registers
since mmap may exist in block_operations, but truncate may not,
moving mmap beforee truncate could make three struct more compatible
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
- Add mmap into file_operations and remove it from ioctl definitions.
- Add mm_map structure definitions to support future unmapping
- Modify all drivers to initialize the operations struct accordingly
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
- Add truncate into file_operations
- Move truncate to be common for mountpt_operations and file_operations
- Modify all drivers to initialize the operations struct accordingly
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
which is made by:
commit 87a1f69a3c
Author: Alan Carvalho de Assis <acassis@gmail.com>
Date: Fri Dec 16 15:23:39 2022 -0300
Modify the IRQ APIs to be compatible with ESP32/S2/S3
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This PR adds the driver for Xingbangda XBD599 LCD Panel (based on Sitronix ST7703 LCD Controller) on PINE64 PinePhone. This PR also includes:
- The driver for X-Powers AXP803 Power Mgmt IC, which calls our driver for Allwinner A64's Reduced Serial Bus. The PMIC Driver is needed to power on the MIPI DSI Interface for the LCD Panel.
- A simple Display Driver that renders a Test Pattern on the LCD Display at startup. It calls our Allwinner A64 drivers for Display Engine, Timing Controller TCON0 and MIPI Display Serial Interface.
The NuttX Frame Buffer Driver will be implemented in the next PR.
`arch/arm64/src/a64/a64_de.c`, `a64_de.h`: Changed the Frame Buffer pointer to `const` for Allwinner A64 Display Engine
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for PWM, for controlling the PWM Backlight
`boards/arm64/a64/pinephone/src/pinephone_bringup.c`: Call `fb_register()` to start the Display Driver at startup
`boards/arm64/a64/pinephone/src/Makefile`: Added LCD Driver, PMIC Driver and Display Driver to Makefile
`boards/arm64/a64/pinephone/Kconfig`: Added the Kconfig option for "PINE64 PinePhone > LCD Display" (`CONFIG_PINEPHONE_LCD`) which enables the LCD Driver, PMIC Driver and Display Driver
`boards/arm64/a64/pinephone/src/pinephone_lcd.c`, `pinephone_lcd.h`: Driver for Xingbangda XBD599 LCD Panel
`boards/arm64/a64/pinephone/src/pinephone_pmic.c`, `pinephone_pmic.h`: Driver for X-Powers AXP803 Power Mgmt IC
`boards/arm64/a64/pinephone/src/pinephone_display.c`: Simple Display Driver that renders a Test Pattern in `up_fbinitialize()`
`boards/arm64/a64/pinephone/configs/lcd/defconfig`: New PinePhone Board Configuration `pinephone:lcd` that enables the LCD Driver (`CONFIG_PINEPHONE_LCD`)
`platforms/arm/a64/boards/pinephone/index.rst`: Added PinePhone Board Configuration `pinephone:lcd` that enables the LCD Driver
Summary:
- I noticed that rv-virt:ksmp64 sometimes stops during boot.
- Finally, I found that it posts the Supervisor Software Interrupt
before the OS finishes hardware initialization.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This PR adds the driver for Reduced Serial Bus (RSB) on Allwinner A64 SoC. The RSB Driver will be called by the upcoming Power Mgmt IC Driver for PINE64 PinePhone, to power on the LCD Display.
`arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > RSB" (`CONFIG_A64_RSB`), which enables the RSB Driver
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for RSB
`arch/arm64/src/a64/Make.defs`: Added the RSB Driver to the Makefile
`arch/arm64/src/a64/a64_de.c`: Increase PLL Timeout for Allwinner A64 Display Engine
`boards/arm64/a64/pinephone/configs/nsh/defconfig`: Set PinePhone Board Config `CONFIG_BOARD_LOOPSPERMSEC` to the value computed by `calib_udelay`
`arch/arm64/src/a64/a64_rsb.c`, `a64_rsb.h`: RSB Driver for Allwinner A64
`platforms/arm/a64/boards/pinephone/index.rst`: Added RSB as supported peripheral for PinePhone
This PR adds the driver for Display Engine 2.0 on Allwinner A64 SoC. The Display Engine Driver will be called by the upcoming LCD Driver for PINE64 PinePhone.
`arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > DE" (`CONFIG_A64_DE`), which enables the Display Engine Driver
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for Display Engine
`arch/arm64/src/a64/Make.defs`: Added the Display Engine Driver to the Makefile
`boards/arm64/a64/pinephone/configs/nsh/defconfig`: Removed Scheduler Debug Info (`CONFIG_DEBUG_SCHED_INFO`) from the PinePhone Board Config, because it garbles the Console Output.
`arch/arm64/src/a64/a64_de.c`, `a64_de.h`: Display Engine Driver for Allwinner A64
`platforms/arm/a64/boards/pinephone/index.rst`: Added Display Engine as supported peripheral for PinePhone
Flexcom working, DMA not looked at for SAMA5D2
Update sam_flexcom_spi.c
Update sam_flexcom_spi.h
Update sam_config.h
Update hardware/sam_flexcom_spi.h
pkarashchenko reviews
SAMA5 serial and flexcom serial corrections
This PR adds the driver for TCON0 (Timing Controller) on Allwinner A64 SoC. The TCON0 Driver will be used by the upcoming Display Driver for PINE64 PinePhone.
`arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > TCON0" (`CONFIG_A64_TCON0`), which enables the TCON0 Driver
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for TCON0
`arch/arm64/src/a64/Make.defs`: Added the TCON0 Driver to the Makefile
`arch/arm64/src/a64/a64_tcon0.c`, `a64_tcon0.h`: TCON0 Driver for Allwinner A64
`platforms/arm/a64/boards/pinephone/index.rst`: Added TCON0 as supported peripheral for PinePhone
"aes_cypher" is a function from NuttX crypto, so better use instead of
defining a new interface in the driver.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This PR adds the driver for Allwinner A64's MIPI Display Serial Interface (DSI) and MIPI Display Physical Layer (D-PHY).
This driver will be used by the upcoming Display Driver for PINE64 PinePhone.
- `include/nuttx/crc16.h`: Added 16-bit CRC-CCITT
- `libs/libc/misc/Make.defs`: Added 16-bit CRC-CCITT to Makefile
- `arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > MIPI DSI" (`CONFIG_A64_MIPI_DSI`), which enables the MIPI DSI Driver
- `arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for MIPI DSI
- `arch/arm64/src/a64/Make.defs`: Added the MIPI DSI Driver to the Makefile
- `libs/libc/misc/lib_crc16ccitt.c`: Compute 16-bit CRC-CCITT
- `arch/arm64/src/a64/mipi_dsi.c`, `mipi_dsi.h`: Compose MIPI DSI Packets (Long, Short, Short with Parameter)
- `arch/arm64/src/a64/a64_mipi_dsi.c`, `a64_mipi_dsi.h`: MIPI DSI Driver for Allwinner A64
- `arch/arm64/src/a64/a64_mipi_dphy.c`, `a64_mipi_dphy.h`: MIPI D-PHY Driver for Allwinner A64
- `platforms/arm/a64/boards/pinephone/index.rst`: Added MIPI DSI as supported peripheral for PinePhone
Co-Authored-By: Petro Karashchenko <petro.karashchenko@gmail.com>
The register definition comes from CMSIS
https: //github.com/ARM-software/CMSIS_5
commit id:10bf763a82318c0c852ff9ecc2d5cd8cebe7d761
file: Core/Include/pmu_armv8.h
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Registers S0-S15 (D0-D7, Q0-Q3) do not need to be preserved. They can be used for passing
arguments or returning results in standard procedure-call variants.
Registers D16-D31 (Q8-Q15), do not need to be preserved.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
