In order to make compilation warnings and errors easier to be found out,
this commit will disable the printing of the compilation process as much
as possible, and also if you want to restore the log information of the
compilation process, please enable verbose build on command line:
$ make V=0
OR
$ make V=1
| V=0: Exit silent mode
| V=1,2: Enable echo of commands
| V=2: Enable bug/verbose options in tools and scripts
Signed-off-by: chao an <anchao@xiaomi.com>
NuttX kernel should not use the syscall functions, especially after
enabling CONFIG_SCHED_INSTRUMENTATION_SYSCALL, all system functions
will be traced to backend, which will impact system performance.
Signed-off-by: chao an <anchao@xiaomi.com>
This is a follow-up to PR #6548, which added UART CTS/RTS support for
Tiva (TI TM4C12x) microcontrollers. This follow-up makes it possible,
when termios support is enabled with CONFIG_SERIAL_TERMIOS and CTS/RTS
support is enabled with CONFIG_SERIAL_OFLOWCONTROL and/or
CONFIG_SERIAL_IFLOWCONTROL, to query whether CTS/RTS are on/off at
runtime by utilizing ioctl TCGETS and to turn CTS/RTS on/off at runtime
by utilizing ioctl TCSETS.
* arch/arm/src/tiva/common/tiva_serial.c
(up_set_format): Because this function is called from ioctl TCSETS to
modify UART settings, and that IOCTL now respects CCTS_OFLOW and
CRTS_IFLOW, move setting/clearing of Tiva UART's CTL register's RTSEN
and CTSEN bits here...
(up_setup): ...from here.
(up_ioctl): For TCGETS, populate CCTS_OFLOW and CRTS_IFLOW bits as
appropriate. For TCSETS, populate priv's oflow and iflow from
supplied CCTS_OFLOW and CRTS_IFLOW bits.
Thanks to Petro Karashchenko for review and suggested fixes.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
The lower-half serial driver for Tiva (TI TM4C12x) microcontrollers supports
termios, but Kconfig never enabled this support because we were missing the
ARCH_HAVE_SERIAL_TERMIOS configs. This is now enabled, allowing termios support
to be enabled with CONFIG_SERIAL_TERMIOS.
* arch/arm/src/tiva/Kconfig
(config TIVA_UART0 thru TIVA_UART7): Select ARCH_HAVE_SERIAL_TERMIOS.
PWM driver for multiple peripherals supplied in gateware.
Only single channel frequency and duty cycle control is implemented. Pulse counting and multichannel features are not currently feasible.
Additions also include a new board configuration for arty-a7 which enables the PWM driver and example application.
Summary:
1. to enable Toolchain select Kconfig option, making something depend on
the opton to be configured with menuconfig
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
/usr/bin/ld: sim_hostusrsock.o: in function `host_usrsock_loop':
arch/sim/src/sim/posix/sim_hostusrsock.c:514: undefined reference to `usrsock_event_callback'
Signed-off-by: chao an <anchao@xiaomi.com>
When sending small number of bytes with larger CONFIG_USEC_PER_TICK
this function should return at least 1. Solve this by rounding
up the result.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This is preparation for moving address environments out of the group
structure into the tcb.
Why move ? Because the group is destroyed very early in the exit phase,
but the MMU mappings are needed until the context switch to the next
process is complete. Otherwise the MMU will lose its mappings and the
system will crash.
There were two issues with signal handling:
- With a kernel stack the "info" parameter was passed from kernel memory.
This is fixed by making a stack frame to the user stack and copying it
there.
- If the signal handler uses a system call, the kernel stack was completely
and unconditionally destroyed, resulting in a crash in the user application
There is also no need to check ustkptr, it is always NULL. Why ? Because
signal delivery is deferred when a system call is being executed.
The value printed by assert() cannot always be trusted to be correct,
as it relies on the stack / stack pointer not being corrupt.
The CPU register always points to the faulting instruction so print it
out in the exception handler.
MCUboot support is no longer behind EXPERIMENTAL for the following
chips:
- ESP32
- ESP32-S2
- ESP32-S3
- ESP32-C3
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Allow bootloader to select run-time whether the payload binary is booted with
SBI or directly by jumping to entrypoint address.
- Use just one bitmask to select sbi or direct boot for each hart
- Add mpfs_set_use_sbi function to allow selecting how to boot
- Initialize the bitmask by default according to the configuration flags
- Add a header file for including the function prototypes in bootloader code
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
SHM area is just mapped memory, the physical backup is not owned by the
process, so the process must not free it.
In ARM this is already handled as the regions are destroyed one by one,
while this implementation does a page directory walk instead.
This is unnecessary, the address environment is getting wiped anyway,
there is no need to remove the L1 references because they will get
wiped when the page directory is changed
/usr/bin/ld: nuttx.rel: in function `mallinfo_task':
nuttx/mm/umm_heap/umm_mallinfo.c:67: undefined reference to `mm_mallinfo_task'
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
do simple copy to instead of memset and memcpy operation because
they have been instrumented, if you access the posion area,
the system will crash.
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
When invalidate address is not aligned with cache line,
must align address and flush the cache line.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
The dual core STM32H747 / STM32H757 there is an additional option to
select SMPS rather than LDO as the power selection.
This commit adds this option to the STM32H747 config and the
stm32h7x7xx source.
Signed-off-by: Julian Oes <julian@oes.ch>
struct stm32_i2c_inst_s instance is allocated on every call to
stm32_i2cbus_initialize, and that instance is supposed to be deleted on every
call to stm32_i2cbus_uninitialize.
The "refs" counter just keeps track on when the last one is deleted, and
everything is unregisterd/disabled.
This reverts commit 8098c80338.
Summary:
- It is applicable to esp32 products and uses the himem part
of 8M psram by creating character devices.
Impact:
- None
Testing:
- Use esp32-wrover series products for more than 1000 functional verifications.
The dependency should be vice versa; the MM_SHM should depend on the
existence of the virtual memory range allocator.
Create a new CONFIG flag CONFIG_ARCH_VMA_MAPPING, which will define that
there is a virtual memory range allocator. Make MM_SHM select that flag
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Move `SIM_I2CBUS_ID` and `SIM_SPIDEV_NAME` from board to arch.
This allows you not to rely on board configuration.
Signed-off-by: xinbingnan <xinbingnan@xiaomi.com>
The current implementation of PIO Interrupt for Allwinner A64 is incomplete. This PR fixes the implementation of PIO Interrupt for all supported PIO Ports (PB, PG and PH).
### Modified Files
`arch/arm64/src/a64/a64_pio.c`, `a64_pio.h`: Add implementation of PIO Interrupt
`arch/arm64/include/a64/irq.h`: Add IRQ for PIO Port PH
`arch/arm64/src/a64/hardware/a64_pio.h`: Fix addresses of PIO Interrupt Registers
since mmap may exist in block_operations, but truncate may not,
moving mmap beforee truncate could make three struct more compatible
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
- Add mmap into file_operations and remove it from ioctl definitions.
- Add mm_map structure definitions to support future unmapping
- Modify all drivers to initialize the operations struct accordingly
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
- Add truncate into file_operations
- Move truncate to be common for mountpt_operations and file_operations
- Modify all drivers to initialize the operations struct accordingly
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
which is made by:
commit 87a1f69a3c
Author: Alan Carvalho de Assis <acassis@gmail.com>
Date: Fri Dec 16 15:23:39 2022 -0300
Modify the IRQ APIs to be compatible with ESP32/S2/S3
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This PR adds the driver for Xingbangda XBD599 LCD Panel (based on Sitronix ST7703 LCD Controller) on PINE64 PinePhone. This PR also includes:
- The driver for X-Powers AXP803 Power Mgmt IC, which calls our driver for Allwinner A64's Reduced Serial Bus. The PMIC Driver is needed to power on the MIPI DSI Interface for the LCD Panel.
- A simple Display Driver that renders a Test Pattern on the LCD Display at startup. It calls our Allwinner A64 drivers for Display Engine, Timing Controller TCON0 and MIPI Display Serial Interface.
The NuttX Frame Buffer Driver will be implemented in the next PR.
`arch/arm64/src/a64/a64_de.c`, `a64_de.h`: Changed the Frame Buffer pointer to `const` for Allwinner A64 Display Engine
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for PWM, for controlling the PWM Backlight
`boards/arm64/a64/pinephone/src/pinephone_bringup.c`: Call `fb_register()` to start the Display Driver at startup
`boards/arm64/a64/pinephone/src/Makefile`: Added LCD Driver, PMIC Driver and Display Driver to Makefile
`boards/arm64/a64/pinephone/Kconfig`: Added the Kconfig option for "PINE64 PinePhone > LCD Display" (`CONFIG_PINEPHONE_LCD`) which enables the LCD Driver, PMIC Driver and Display Driver
`boards/arm64/a64/pinephone/src/pinephone_lcd.c`, `pinephone_lcd.h`: Driver for Xingbangda XBD599 LCD Panel
`boards/arm64/a64/pinephone/src/pinephone_pmic.c`, `pinephone_pmic.h`: Driver for X-Powers AXP803 Power Mgmt IC
`boards/arm64/a64/pinephone/src/pinephone_display.c`: Simple Display Driver that renders a Test Pattern in `up_fbinitialize()`
`boards/arm64/a64/pinephone/configs/lcd/defconfig`: New PinePhone Board Configuration `pinephone:lcd` that enables the LCD Driver (`CONFIG_PINEPHONE_LCD`)
`platforms/arm/a64/boards/pinephone/index.rst`: Added PinePhone Board Configuration `pinephone:lcd` that enables the LCD Driver
Summary:
- I noticed that rv-virt:ksmp64 sometimes stops during boot.
- Finally, I found that it posts the Supervisor Software Interrupt
before the OS finishes hardware initialization.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This PR adds the driver for Reduced Serial Bus (RSB) on Allwinner A64 SoC. The RSB Driver will be called by the upcoming Power Mgmt IC Driver for PINE64 PinePhone, to power on the LCD Display.
`arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > RSB" (`CONFIG_A64_RSB`), which enables the RSB Driver
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for RSB
`arch/arm64/src/a64/Make.defs`: Added the RSB Driver to the Makefile
`arch/arm64/src/a64/a64_de.c`: Increase PLL Timeout for Allwinner A64 Display Engine
`boards/arm64/a64/pinephone/configs/nsh/defconfig`: Set PinePhone Board Config `CONFIG_BOARD_LOOPSPERMSEC` to the value computed by `calib_udelay`
`arch/arm64/src/a64/a64_rsb.c`, `a64_rsb.h`: RSB Driver for Allwinner A64
`platforms/arm/a64/boards/pinephone/index.rst`: Added RSB as supported peripheral for PinePhone
This PR adds the driver for Display Engine 2.0 on Allwinner A64 SoC. The Display Engine Driver will be called by the upcoming LCD Driver for PINE64 PinePhone.
`arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > DE" (`CONFIG_A64_DE`), which enables the Display Engine Driver
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for Display Engine
`arch/arm64/src/a64/Make.defs`: Added the Display Engine Driver to the Makefile
`boards/arm64/a64/pinephone/configs/nsh/defconfig`: Removed Scheduler Debug Info (`CONFIG_DEBUG_SCHED_INFO`) from the PinePhone Board Config, because it garbles the Console Output.
`arch/arm64/src/a64/a64_de.c`, `a64_de.h`: Display Engine Driver for Allwinner A64
`platforms/arm/a64/boards/pinephone/index.rst`: Added Display Engine as supported peripheral for PinePhone
Flexcom working, DMA not looked at for SAMA5D2
Update sam_flexcom_spi.c
Update sam_flexcom_spi.h
Update sam_config.h
Update hardware/sam_flexcom_spi.h
pkarashchenko reviews
SAMA5 serial and flexcom serial corrections
This PR adds the driver for TCON0 (Timing Controller) on Allwinner A64 SoC. The TCON0 Driver will be used by the upcoming Display Driver for PINE64 PinePhone.
`arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > TCON0" (`CONFIG_A64_TCON0`), which enables the TCON0 Driver
`arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for TCON0
`arch/arm64/src/a64/Make.defs`: Added the TCON0 Driver to the Makefile
`arch/arm64/src/a64/a64_tcon0.c`, `a64_tcon0.h`: TCON0 Driver for Allwinner A64
`platforms/arm/a64/boards/pinephone/index.rst`: Added TCON0 as supported peripheral for PinePhone
"aes_cypher" is a function from NuttX crypto, so better use instead of
defining a new interface in the driver.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This PR adds the driver for Allwinner A64's MIPI Display Serial Interface (DSI) and MIPI Display Physical Layer (D-PHY).
This driver will be used by the upcoming Display Driver for PINE64 PinePhone.
- `include/nuttx/crc16.h`: Added 16-bit CRC-CCITT
- `libs/libc/misc/Make.defs`: Added 16-bit CRC-CCITT to Makefile
- `arch/arm64/src/a64/Kconfig`: Added the Kconfig option for "A64 Peripheral Selection > MIPI DSI" (`CONFIG_A64_MIPI_DSI`), which enables the MIPI DSI Driver
- `arch/arm64/src/a64/hardware/a64_memorymap.h`: Added the Base Address for MIPI DSI
- `arch/arm64/src/a64/Make.defs`: Added the MIPI DSI Driver to the Makefile
- `libs/libc/misc/lib_crc16ccitt.c`: Compute 16-bit CRC-CCITT
- `arch/arm64/src/a64/mipi_dsi.c`, `mipi_dsi.h`: Compose MIPI DSI Packets (Long, Short, Short with Parameter)
- `arch/arm64/src/a64/a64_mipi_dsi.c`, `a64_mipi_dsi.h`: MIPI DSI Driver for Allwinner A64
- `arch/arm64/src/a64/a64_mipi_dphy.c`, `a64_mipi_dphy.h`: MIPI D-PHY Driver for Allwinner A64
- `platforms/arm/a64/boards/pinephone/index.rst`: Added MIPI DSI as supported peripheral for PinePhone
Co-Authored-By: Petro Karashchenko <petro.karashchenko@gmail.com>
The register definition comes from CMSIS
https: //github.com/ARM-software/CMSIS_5
commit id:10bf763a82318c0c852ff9ecc2d5cd8cebe7d761
file: Core/Include/pmu_armv8.h
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Registers S0-S15 (D0-D7, Q0-Q3) do not need to be preserved. They can be used for passing
arguments or returning results in standard procedure-call variants.
Registers D16-D31 (Q8-Q15), do not need to be preserved.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
This PR adds the drivers for Allwinner A64 PIO (Programmable I/O) and PinePhone LEDs (Red / Green / Blue).
The PIO Driver is based on the NuttX PIO Driver for Allwinner A10: [`arch/arm/src/a1x/a1x_pio.c`](https://github.com/apache/nuttx/blob/master/arch/arm/src/a1x/a1x_pio.c)
- `arch/arm64/src/a64/Make.defs`: Add PIO Driver to Makefile
- `boards/Kconfig`: Add `ARCH_HAVE_LEDS` to PinePhone
- `boards/arm64/a64/pinephone/src/pinephone.h`: Define PinePhone LEDs
- `boards/arm64/a64/pinephone/src/pinephone_boardinit.c`: Start Auto LEDs
- `boards/arm64/a64/pinephone/src/pinephone_bringup.c`: Start User LEDs
- `boards/arm64/a64/pinephone/src/Makefile`: Add LED Driver to Makefile
- `boards/arm64/a64/pinephone/configs/nsh/defconfig`: Add `CONFIG_USERLED` to `nsh` config
- `arch/arm64/src/a64/a64_pio.c`, `a64_pio.h`: Allwinner A64 PIO Driver
- `arch/arm64/src/a64/hardware/a64_memorymap.h`: PIO Memory Map
- `arch/arm64/src/a64/hardware/a64_pio.h`: PIO Definitions
- `boards/arm64/a64/pinephone/include/board.h`: Define PinePhone LEDs
- `boards/arm64/a64/pinephone/src/pinephone_autoleds.c`: Driver for Auto LEDs
- `boards/arm64/a64/pinephone/src/pinephone_userleds.c`: Driver for User LEDs
- `introduction/supported_platforms.rst`: Add Allwinner A64 as Supported Platform
- `platforms/arm/a64/boards/pinephone/index.rst`: Add PIO and LEDs to PinePhone
In file included from sim/sim_netdriver.c:73:
sim/sim_netdriver.c: In function ‘netdriver_ifup’:
sim/sim_netdriver.c:284:32: error: ‘struct net_driver_s’ has no member named ‘d_ipaddr’; did you mean ‘d_ipv6addr’?
284 | sim_netdev_ifup(devidx, dev->d_ipaddr);
| ^~~~~~~~
sim/sim_internal.h:279:67: note: in definition of macro ‘sim_netdev_ifup’
279 | # define sim_netdev_ifup(idx,ifaddr) sim_tapdev_ifup(idx,ifaddr)
|
Signed-off-by: chao an <anchao@xiaomi.com>
l3/l4 stack will decouple the reference of d_buf gradually, Only legacy
devices still retain d_buf support, new net devices will use d_iob
Signed-off-by: chao an <anchao@xiaomi.com>
The following changes omit the arm version:
| commit d321080351
| Author: chao an <anchao@xiaomi.com>
| Date: Fri Dec 2 02:52:18 2022 +0800
|
| arm/cortex-[a|r]: generating assemble code in ARM states by default
|
| Signed-off-by: chao an <anchao@xiaomi.com>
Signed-off-by: chao an <anchao@xiaomi.com>
Fix build break on thumb2 mode:
opus/celt/arm/celt_pitch_xcorr_arm-gnu.S: Assembler messages:
opus/celt/arm/celt_pitch_xcorr_arm-gnu.S:146: Error: thumb conditional instruction should be in IT block -- `movle pc,lr'
Reference:
https://developer.arm.com/documentation/100067/0612/armclang-Command-line-Options/-mimplicit-it
In A32 code, the integrated assembler accepts all conditional instructions
without giving an error or warning. In T32 code, the integrated assembler
outputs an implicit IT block when there is a conditional instruction
without an enclosing IT block. The integrated assembler does not give an
error or warning about this.
Signed-off-by: chao an <anchao@xiaomi.com>
The option '-mthumb' is only valid for C source files and it is not passed to the assembler.
If 'thumb' is not considered in some assembly projects, the system will generate
'undefined instructions' when running incompatible instruction:
arm_undefinedinsn: Undefined instruction at 0x380cfc98
This assembly file should be compiled with .thumb but it doesn't:
380cfc90 <hobot_i8_i32_gemm_nn_m4_n8_neon>:
380cfc90: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr}
380cfc94: ed2d8b10 vpush {d8-d15}
380cfc98: e59d4064 ldr r4, [sp, #100] ; 0x64 <-- Undefined instruction
380cfc9c: e59d5068 ldr r5, [sp, #104] ; 0x68
380cfca0: e59d606c ldr r6, [sp, #108] ; 0x6c
380cfca4: e59d7070 ldr r7, [sp, #112] ; 0x70
380cfca8: e1a08120 lsr r8, r0, #2
380cfcac: e1a091a1 lsr r9, r1, #3
380cfcb0: e1a0a122 lsr sl, r2, #2
After enable thumb:
.syntax unified
.thumb
or
-Wa,-mthumb
.Lhobot_i8_i32_gemm_nn_m4_n8_neon:
38001100: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
38001104: ed2d 8b10 vpush {d8-d15}
38001108: 9c19 ldr r4, [sp, #100] ; 0x64
3800110a: 9d1a ldr r5, [sp, #104] ; 0x68
3800110c: 9e1b ldr r6, [sp, #108] ; 0x6c
3800110e: 9f1c ldr r7, [sp, #112] ; 0x70
38001110: ea4f 0890 mov.w r8, r0, lsr #2
38001114: ea4f 09d1 mov.w r9, r1, lsr #3
38001118: ea4f 0a92 mov.w sl, r2, lsr #2
This commit will enable the thumb option of the assembly file by default,
so that when compiling the assembly file, the machine code and the system will be in a consistent state.
----------------------------------------------------------------
https://gcc.gnu.org/onlinedocs/gcc-4.5.2/gcc/ARM-Options.html
GCC Manual:
-mthumb
Generate code for the Thumb instruction set. The default is to use the 32-bit ARM
instruction set. This option automatically enables either 16-bit Thumb-1 or mixed 16/32-bit
Thumb-2 instructions based on the -mcpu=name and -march=name options.
** This option is not passed to the assembler. **
** If you want to force assembler files to be interpreted as Thumb code,
either add a `.thumb' directive to the source or pass the -mthumb option
directly to the assembler by prefixing it with -Wa. **
Signed-off-by: chao an <anchao@xiaomi.com>
Summary:
- I noticed that the nsh prompt can not be shown when disabling
debug features. Actually, the prompt will be shown when a user
input happens.
- This commit fixes this issue by adding uart_xmitchars() as
other serial drivers do.
Impact:
- None
Testing:
- Tested with qemu-armv8a:netnsh on QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that mtimer stops around 30min after boot.
- Finally, I found that nesc overflows in riscv_mtimer_current().
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with rv-virt:nsh on QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
arch/arm/src/sama5/Kconfig:819:error: recursive dependency detected!
For a resolution refer to Documentation/kbuild/kconfig-language.txt
subsection "Kconfig recursive dependency limitations"
arch/arm/src/sama5/Kconfig:819: choice <choice> contains symbol SAMA5_FLEXCOM0_USART
For a resolution refer to Documentation/kbuild/kconfig-language.txt
subsection "Kconfig recursive dependency limitations"
arch/arm/src/sama5/Kconfig:824: symbol SAMA5_FLEXCOM0_USART is part of choice SAMA5_FLEXCOM0_USART
For a resolution refer to Documentation/kbuild/kconfig-language.txt
subsection "Kconfig recursive dependency limitations"
arch/arm/src/sama5/Kconfig:824: symbol SAMA5_FLEXCOM0_USART is part of choice <choice>
Signed-off-by: chao an <anchao@xiaomi.com>
SAMA5Dx ADC and TSD fixes
Ensures ADC and TSD work together. TSD now works on SAMA5D2 and should be OK, still, for other SAMA5D familiy members
Fix CI error
checkpatch error
Update arch/arm/src/sama5/sam_tsd.h
Squash commits to arch/arm/src/sama5/hardware/sam_adc.h
Update arch/arm/src/sama5/hardware/sam_adc.h
Update arch/arm/src/sama5/hardware/sam_adc.h
Update arch/arm/src/sama5/hardware/sam_adc.h
Update arch/arm/src/sama5/hardware/sam_adc.h
Update arch/arm/src/sama5/hardware/sam_adc.h
Update arch/arm/src/sama5/hardware/sam_adc.h
Update arch/arm/src/sama5/hardware/sam_adc.h
Squash commits to arch/arm/src/sama5/sam_tsd.c
Update arch/arm/src/sama5/sam_tsd.c
Update arch/arm/src/sama5/sam_tsd.c
Update arch/arm/src/sama5/sam_tsd.c
Update sam_tsd.c
Fixes after feedback from PR and additional testing
Update sam_tc.c
checkpatch.sh error was missed when fixing someone else's error...
feedback corrections missed
Co-Authored-By: Xiang Xiao <xiaoxiang781216@gmail.com>
Co-Authored-By: Petro Karashchenko <petro.karashchenko@gmail.com>
squashed everything after 248072e02C
/arch/arm/src/libarch.a(stm32_flash.o): in function `up_progmem_write':
/arch/arm/src/chip/stm32_flash.c:419: undefined reference to `stm32_waste'
Seems like the symbol definition + declaration were completely missing
Use correct path to include mutex.h
Fixes:
chip/stm32_bbsram.c:42:10: fatal error: mutex.h: No such file or directory
42 | #include <mutex.h>
| ^~~~~~~~~
In order to turn longjmp context-switch safe, it's necessary
to disable interrupts before modifying windowbase and windowstart.
Otherwise, after a context switch, windowstart and windowbase
would be different, leading to a wrongly set windowstart bit due to
longjmp writing it based on the windowbase before the context switch.
This corrupts the registers at the next window overflow reaching
that wrongly set bit.
*Background:*
This PR is related to an issue first observed on ESP-IDF
https://github.com/espressif/esp-idf/issues/5229 and it was, then,
checked on NuttX using a test application.
*The test application:*
To check if the problem affects ESP32, ESP32-S2 and ESP32-S3 on
NuttX, it was created an application based on:
https://en.cppreference.com/w/c/program/longjmp
The application creates 16 tasks (`#define NUMBER_OF_TASKS 16`)
that implements the following daemon:
```
static int setjmp_longjmp_daemon(int argc, char *argv[])
{
for (int i = 0; i < NUMBER_OF_TASKS * 2; i++)
{
jmp_buf env;
volatile int count = 0;
if (setjmp(env) != UINT16_MAX)
{
foo(&env, ++count);
}
}
sem_post(&g_sem);
return EXIT_SUCCESS;
}
```
The main function also initializes a semaphore to avoid application
exiting before tasks return successfully:
```
sem_init(&g_sem, 0, -NUMBER_OF_TASKS);
```
Finally, the round-robin interval was lowered to 1ms to raise the
chances of the longjmp being interrupted by a context switch
(`CONFIG_RR_INTERVAL=1).
This setup was able to reproduce the problem prior to this patch
being applied.
It takes about 10 cycles to obtain the task list according to the task
status. In most cases, we know the task status, so we can directly
add the task from the specified task list to reduce time consuming.
It takes about 10 cycles to obtain the task list according to the task
status. In most cases, we know the task status, so we can directly
delete the task from the specified task list to reduce time consuming.
- Add ioctl method to enable allocating the apb buffer.
- Add RX methods to set data width, sample rate, channels and
for receiving data from the I2S peripheral.
- Update the i2schar defconfig to enable the I2S receiver.
- Add nxlooper defconfig to enable testing the RX interface.
- Add specific bindings on ESP32-S2 bringup to enable nxlooper
to work without the need of any specific codec.
After commit b7d2b38, the system suffers from -Warray-bounds warning with -Wall:
chip/mpfs_opensbi.c: In function 'mpfs_hart_to_scratch':
chip/mpfs_opensbi.c:251:26: warning: array subscript hartid is outside array bounds of 'sbi_scratch_holder_t[0]' {aka 'struct sbi_scratch_holder_s[]'} [-Warray-bounds]
251 | return (unsigned long)(&g_scratches[hartid].scratch);
Fix it by reverting back to what is was earlier. g_scratches shouldn't be in the bss
region that would be zeroed out.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Currently NuttX on Arm64 supports Generic Interrupt Controller (GIC) Versions 3 and 4: [`arm64_gicv3.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm64/src/common/arm64_gicv3.c), [`arm64_gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm64/src/common/arm64_gic.h). This PR adds support for GIC Version 2, which is needed by [Pine64 PinePhone](https://lupyuen.github.io/articles/interrupt) based on Allwinner A64 SoC.
This 64-bit implementation of GIC v2 is mostly identical to the existing GIC v2 for 32-bit Armv7-A ([`armv7-a/arm_gicv2.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/arm_gicv2.c), [`armv7-a/gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/gic.h)), with minor modifications to support 64-bit Registers (Interrupt Context).
- `arch/arm64/Kconfig`: Under "ARM64 Options", we added an integer option `ARM_GIC_VERSION` ("GIC version") that selects the GIC Version. Valid values are 2, 3 and 4, default is 3.
- `arch/arm64/src/common/arm64_gicv2.c`: Implements 64-bit GIC v2 based on 32-bit [`armv7-a/arm_gicv2.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/arm_gicv2.c) and [`armv7-a/gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/gic.h), modified to support 64-bit Registers (Interrupt Context).
Function and Macro Names have not been changed, for easier cross-referencing between the 32-bit and 64-bit implementations of GIC v2.
- `arch/arm64/src/common/arm64_gicv3.c`: Added Conditional Compilation for GIC v3. This file will not be compiled if `ARM_GIC_VERSION` is 2.
- `arch/arm64/src/common/arm64_gic.h`: Added the Version Identifier for GIC v2. At startup we read the GIC Version from hardware and verify that it matches `ARM_GIC_VERSION`.
- `arch/arm64/include/qemu/chip.h`: Added the QEMU Base Addresses for GIC v2.
- `arch/arm64/src/common/Make.defs`: Added the source file that implements GIC v2.
- `boards/arm64/qemu/qemu-armv8a/README.txt`: Added the documentation for testing GIC v2 with QEMU.
- `boards/arm64/qemu/qemu-armv8a/configs/nsh_gicv2/defconfig`: Added the Board Configuration `qemu-armv8a:nsh_gicv2` for testing GIC v2 with QEMU. Identical to `qemu-armv8a:nsh`, except that `ARM_GIC_VERSION` is 2.
- Add ioctl method to enable allocating the apb buffer.
- Add RX methods to set data width, sample rate, channels and
for receiving data from the I2S peripheral.
- Update the i2schar defconfig to enable the I2S receiver.
- Add nxlooper defconfig to enable testing the RX interface.
- Add specific bindings on ESP32 bringup to enable nxlooper
to work without the need of any specific codec.
After the commit b8b541f, the system would not start up properly
with certain coldboot conditions. For example, if the OpenSBI picked
hart4 as the coldboot hart in preference to hart3, the system would
get stuck due to stack corruption. OpenSBI uses a lottery mechanism
to pick the coldboot hart.
Also fix g_scratches area in such a manner than it will not get
initialized to zero. If several harts initialize the area to zero, there's
danger the stack pointer gets wiped out.
Now any coldboot hart works.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
chip/stm32_adc.c:2529:32: warning: shifting a negative signed value is undefined [-Wshift-negative-value]
setbits = ADC_CCR_DUAL_IND | ADC_CCR_DELAY(0) | ADC_CCR_MDMA_DISABLED |
^~~~~~~~~~~~~~~~
In the past, header file paths were generated by the incdir command
Now they are generated by concatenating environment variables
In this way, when executing makefile, no shell command will be executed,
it will improve the speed of executing makfile
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Currently the IHC (Inter Hart Communication) depends on OpenAMP and
rptun. However, the bootloader portion of the IHC doesn't need
either of them. Now they are wasting a lot of bootloader space.
Reorganize the bootloader portion into a separate file 'mpfs_ihc_sbi.c'.
This file contains the OpenSBI vendor extensions, or the only required
functionalities for the bootloader. On the other hand, 'mpfs_ihc.c'
contains the non-bootloader code.
This patch also makes it possible to utilize 2 RPMSG channels. This
has been tested so that 2 separate NuttXs on harts 1 and 2 communicate
with Linux kernel that runs on harts 3 and 4.
New configuration files are added as well:
- rpmsg-ch1: sample config for RPMSG
- rpmsg-ch2: sample config for another RPMSG channel
- rpmsg-sbi: sample bootloader config for RPMSG/OpenSBI
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This reverts commit ea9144bda8.
The commit made Icicle MPFS DDR useless. Revert the change for now.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
common/arm_backtrace_sp.c: In function 'up_backtrace':
common/arm_backtrace_sp.c:253:15: warning: assignment to 'long unsigned int' from 'uint8_t *' {aka 'unsigned char *'} makes integer from pointer without a cast [-Wint-conversion]
253 | top = g_intstacktop;
|
to fix the following clang warning:
Error: chip/eoss3_irq.c:138:47: error: format specifies type 'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned long') [-Werror,-Wformat]
_err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
~~~~ ^~~~~~~~~~~~~~~~~~~~~~
%08lx
/github/workspace/sources/nuttx/include/debug.h:126:57: note: expanded from macro '_err'
__arch_syslog(LOG_ERR, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
~~~~~~ ^~~~~~~~~~~
/github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:134:24: note: expanded from macro 'getreg32'
^~~~~~~~~~~~~~~~~~~~~~~~~~~
Error: chip/eoss3_irq.c:146:49: error: format specifies type 'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned long') [-Werror,-Wformat]
_err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
~~~~ ^~~~~~~~~~~~~~~~~~~~~~
%08lx
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
1.Don't check the return value of nxsem_init or nxmutex_init
2.Fix some style issue
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
