sergiotarxz/nuttx
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20129 Commits

Author SHA1 Message Date
anjiahao
bc30b294aa mm:add heap args to mm_malloc_size 
use malloc_size inside of where used mm_malloc_size

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
 2023-01-17 21:57:37 +08:00
dongjiuzhu1
8101978765 arch/sim: fix compile break when using mallinfo_task with custom mm manager 
/usr/bin/ld: nuttx.rel: in function `mallinfo_task':
nuttx/mm/umm_heap/umm_mallinfo.c:67: undefined reference to `mm_mallinfo_task'

Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
 2023-01-17 16:48:30 +08:00
luoyong1
a32124879d arch/arm/src/armv7-a/r: fix kconfig error of l2 cache latency 
fix the error of the config name and set latency config param bool to int

Signed-off-by: luoyong1 <luoyong1@xiaomi.com>
 2023-01-17 12:45:42 +09:00
Xiang Xiao
62c5afe655 Fix warning in file included from chip/sam_clockconfig.c:34: 
chip/sam_clockconfig.c: In function 'sam_usbclockconfig':
Error: /github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:51: error: 'regval' is used uninitialized [-Werror=uninitialized]
  135 | #define putreg32(v,a)  (*(volatile uint32_t *)(a) = (v))
      |                                                   ^
chip/sam_clockconfig.c:422:12: note: 'regval' was declared here
  422 |   uint32_t regval;
      |            ^~~~~~

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-01-16 18:59:44 -03:00
ligd
fedad91b0d sim/mem: don't let siwtch out when operated the host mem 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2023-01-17 01:18:03 +08:00
ligd
c08cc01c9d sim/oneshot: don't need sleep_until when open CONFIG_SIM_WALLTIME_SIGNAL 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2023-01-17 01:18:03 +08:00
Xiang Xiao
f64da13e9b libxx: Add CXX_STANDARD to select -std=c++?? 
and default to "c++17"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-01-16 15:41:57 +02:00
TimJTi
6b4da4ad6e Ensure SFR CKTRIM register correctly set, SAMA5D2/D3 only 2023-01-16 21:40:00 +08:00
Dong Heng
118222ba46 xtensa/esp32: Partition device supports encryption mode 2023-01-16 09:55:44 -03:00
dongjiuzhu1
7cd325f3be mm/mm_heap: remove kasan in MM_ADD_BACKTRACE 
do simple copy to instead of memset and memcpy operation because
they have been instrumented, if you access the posion area,
the system will crash.

Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
 2023-01-16 20:32:17 +08:00
chao an
415a09115d boards/sim/windows: enable custom options 
1. boards/sim: enable child status
2. boards/sim/windows: enable custom options
3. sim/windows: enable hostfs

Signed-off-by: chao an <anchao@xiaomi.com>
 2023-01-16 20:30:39 +08:00
zhangyuan21
806a2a8b8d arch/armv7-ar: flush dcache when addr is not aligned with cache line 
When invalidate address is not aligned with cache line,
must align address and flush the cache line.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
 2023-01-16 16:14:32 +08:00
zhangyuan21
4bb155db64 arch/arm: add barrier instruction for cache ops 
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
 2023-01-16 16:14:32 +08:00
Xiang Xiao
f783f5c384 arch/arm: Fix typo error in cp15_cacheops.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-01-16 16:14:32 +08:00
Xiang Xiao
1ea9db4ebe Fix error: implicit declaration of function 'cp15_invalidate_icache'; did you mean 'cp15_invalidate_dcache'? 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-01-16 16:14:32 +08:00
chenrun1
c61195bcc9 arch/armv7-a & armv7-r:Add invalidate icache behavior 
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
 2023-01-16 16:14:32 +08:00
ligd
7e4c5d3daa armv7a/r: cache function should depends on CONFIG_ARCH_XCACHE 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2023-01-16 16:14:32 +08:00
Julian Oes
22fa59074f stm32h7: add SMPS PWR option for STM32H7X7 
The dual core STM32H747 / STM32H757 there is an additional option to
select SMPS rather than LDO as the power selection.

This commit adds this option to the STM32H747 config and the
stm32h7x7xx source.

Signed-off-by: Julian Oes <julian@oes.ch>
 2023-01-16 13:31:23 +08:00
zhangyuan21
fc623949a3 arch/arm: move hard code macro to kconfig 
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
 2023-01-16 13:31:04 +08:00
luoyong1
6975bbb38d arch/arm/src: add pl310 l2cache's kconfig for latency 
Signed-off-by: luoyong1 <luoyong1@xiaomi.com>
 2023-01-16 13:31:04 +08:00
Alan Carvalho de Assis
97402f9121 esp32: Fix QEnconder reset position and small typo 
The PCNT RST bit needs to be set to zeroing the counter and then
this same bit needs to be cleared to returning counting.
 2023-01-16 09:41:46 +08:00
Jukka Laitinen
f9c8b4015f Revert "arch: Don't free the context if the reference doesn't equal zero" 
struct stm32_i2c_inst_s instance is allocated on every call to
stm32_i2cbus_initialize, and that instance is supposed to be deleted on every
call to stm32_i2cbus_uninitialize.

The "refs" counter just keeps track on when the last one is deleted, and
everything is unregisterd/disabled.

This reverts commit 8098c80338.
 2023-01-15 19:52:05 +08:00
ssssenai
077ad5b45f arch: xtensa/esp32: Add esp32_himem_chardev.c 
Summary:
- It is applicable to esp32 products and uses the himem part
  of 8M psram by creating character devices.

Impact:
- None

Testing:
- Use esp32-wrover series products for more than 1000 functional verifications.
 2023-01-14 14:07:46 +08:00
Janne Rosberg
246a677045 sama5/sam_flexcom_spi: enable DMA support 2023-01-14 13:40:14 +08:00
Janne Rosberg
f6d164bf9d sama5/dmac: add defines for ATSAMA5D2 
This allows xdma to be used on SAMA5D2x chips
 2023-01-14 13:40:14 +08:00
ptr_b
890f9ad2ed arch/sim: add arch/math.h 
To avoid introducing __GLIBC__ symbol which may affect others

Signed-off-by: ptr_b <bijunda1@xiaomi.com>
 2023-01-13 23:09:47 +08:00
W-Mai
bcb0abc05d sim/posix/sim_linuxspi.c: fix select not work and incorrect behaviour 
Fixed missing `SPI_SELECT` method and incorrect sending behavior in sim_linuxspi

Signed-off-by: xinbingnan <xinbingnan@xiaomi.com>
 2023-01-13 15:32:13 +08:00
Petro Karashchenko
45ed6f657c arch/arm/cxd56xx: do not clear enabled callback event on card insertion 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2023-01-13 12:18:36 +08:00
dongjiuzhu1
cf987238c0 sim/hci: add depends on config for SIM_HCISOCKET to fix compile break 
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
 2023-01-13 02:21:34 +08:00
Jukka Laitinen
70de321de3 arch/Kconfig: remove virtual memory allocator dependency from MM_SHM 
The dependency should be vice versa; the MM_SHM should depend on the
existence of the virtual memory range allocator.

Create a new CONFIG flag CONFIG_ARCH_VMA_MAPPING, which will define that
there is a virtual memory range allocator. Make MM_SHM select that flag

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2023-01-13 02:20:13 +08:00
Lucas Saavedra Vaz
674b480198 arch/xtensa/esp32s2: Add initial support for touch pad polling 2023-01-12 22:23:42 +08:00
Lucas Saavedra Vaz
749d0dfe84 arch/xtensa/esp32s2: Add RTC GPIOs configuration functions 2023-01-12 22:23:42 +08:00
Lucas Saavedra Vaz
cdd0787b54 arch/xtensa/esp32: Fix typo and check PU/PD registers 2023-01-12 22:23:42 +08:00
Lucas Saavedra Vaz
3dad6b273e arch/xtensa/esp32s2: Add missing SENS and RTCCNTL registers 2023-01-12 22:23:42 +08:00
xinbingnan
383458c64e sim/Kconfig: move some i2c,spi configs from board to arch 
Move `SIM_I2CBUS_ID` and `SIM_SPIDEV_NAME` from board to arch.
This allows you not to rely on board configuration.

Signed-off-by: xinbingnan <xinbingnan@xiaomi.com>
 2023-01-11 17:28:43 +08:00
Lucas Saavedra Vaz
2b7d8981e2 arch/xtensa/esp32s3: Add initial support for touch pad polling 2023-01-11 02:00:41 +08:00
Lucas Saavedra Vaz
24995f6918 arch/xtensa/esp32s3: Add RTC GPIOs configuration functions 2023-01-11 02:00:41 +08:00
Lucas Saavedra Vaz
c8dd4b068d arch/xtensa/esp32s3: Add missing registers and definitions 2023-01-11 02:00:41 +08:00
Dong Heng
07342f7957 xtensa/esp32: SPI support to configure as R/W/RW mode 2023-01-11 01:54:36 +08:00
raiden00pl
88dd705d27 stm32/stm32f7 CANv1: protect TX buffer during CAN error frame generation 
Follow up to eb240e0 (PR #8060)
 2023-01-11 01:53:49 +08:00
chao an
eef818e51f risc-v/esp32c3: correct receive buffer size 
1. correct receive buffer size, d_len should keep the l2 header size
2. fix race condition issue of de/enqueue rx queue

Signed-off-by: chao an <anchao@xiaomi.com>
 2023-01-10 11:28:06 -03:00
Carlos Sanchez
eb240e014c stm32: protect TX buffer during CAN error frame generation. 2023-01-10 13:33:35 +08:00
Petro Karashchenko
5f92c62874 boards/cxd56xx/spresense: add fs automount driver for SD Card 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2023-01-10 10:39:23 +09:00
Carlos Sanchez
78248183aa s32k1xx: reserve MSG_DATA extra space only when needed by config. 2023-01-09 21:06:56 +02:00
Carlos Sanchez
3c6d45fa99 s32k1xx: avoid buffer overflow when CAN time is used for non-FD CAN. 
s32k1xx: fix initialization of MAXMB field in MCR.
 2023-01-09 21:06:56 +02:00
Dong Heng
67ccee2c4f xtensa/esp32: ESP32 SPI Flash encryption supports 16-bytes align writing 2023-01-10 01:10:10 +08:00
Sergey Nikitenko
e0f99d93ac stm32wb: add i2c driver 2023-01-09 09:27:17 +08:00
chenwen@espressif.com
eed2cce3f2 xtensa/esp32: Optimize WLAN device buffer 2023-01-07 13:46:37 +08:00
chenwen@espressif.com
933d1a0a80 xtensa/esp32: Add Wi-Fi softap event 2023-01-06 12:25:36 -03:00
Dong Heng
f137a7b552 xtensa/esp32: Fix macro "CONFIG_NETDEV_IOCTL" control range error 2023-01-06 20:40:53 +08:00