Commit Graph

57 Commits

Author SHA1 Message Date
Masayuki Ishikawa
2f80a05eae arch: qemu-rv: Fix qemu_rv_mtimer_interrupt() for BUILD_KERNEL
Summary:
- I noticed that rv-virt:ksmp64 sometimes stops during boot.
- Finally, I found that it posts the Supervisor Software Interrupt
  before the OS finishes hardware initialization.
- This commit fixes this issue.

Impact:
- None

Testing:
- Tested with QEMU-7.1

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-12-24 11:25:39 -03:00
Masayuki Ishikawa
8053931d31 arch: qemu-rv: Add qemu_rv_virtio.c
Summary:
- This commit adds qemu_rv_virtio.c

Impact:
- None

Testing
- Tested with rv-virt:netnsh (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-11-29 13:16:44 +08:00
zhangyuan21
a8fa51e6bf arch: rename arch special function name 2022-11-22 16:27:56 +08:00
Xiang Xiao
6b31918b42 Remove the unnecessary cast for main_t, NULL and argv
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-18 08:51:45 +02:00
Masayuki Ishikawa
cb73e9a67d arch: qemu-rv: Refactor the entry point name for BUILD_KERNEL
Summary:
- This commit refactors the entry point name for BUILD_KERNEL
  to avoid misunderstanding the name

Impact:
- None

Testing:
- Tested with rv-virt:ksmp64

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-09 14:08:47 +08:00
Masayuki Ishikawa
4b6c9915fe arch: qemu-rv: Fix timer and IPI handling for BUILD_KERNEL+SMP
Summary:
- I noticed that the OS timer sometimes proceeds fast when
  a task is scheduled to run on CPUO via IPI.
- Actually, qemu-rv implementation shares supervisor software
  interrupt for both timer and IPI on CPU0.
- This commit fixes this issue.

Impact:
- qemu-rv only

Testing:
- Tested with qemu-6.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-08 17:19:51 +08:00
Masayuki Ishikawa
4e095d2e90 arch: risc-v: Add SMP support for BUILD_KERNEL
Summary:
- This commit adds SMP support for BUILD_KERNEL

Impact:
- RISC-V: BUILD_KERNEL + SMP only

Testing:
- Tested with rv-virt:ksmp64 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-08 09:25:41 +08:00
Masayuki Ishikawa
df6bf3e614 arch: risc-v: Introduce RISCV_IPI macro for SMP
Summary:
- This commit introduces RISCV_IPI macro for SMP
- Also, replace RISCV_IRQ_MSOFT with RISCV_IRQ_SOFT
- Remove duplicate irq_attach() from qemu_rv_irq.c

Impact:
- None

Testing:
- Tested with rv-virt:smp64 and maix-bit:smp on QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-07 14:49:29 +08:00
Masayuki Ishikawa
a7bca63b3b arch: qemu-rv: Fix build errors in chip.h for BUILD_KERNEL + SMP
Summary:
- This commit fixes build errors for BUILD_KERNEL + SMP

Impact:
- None

Testing:
- Tested with rv-virt:ksmp64 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-05 17:19:13 +08:00
Masayuki Ishikawa
2fa872e304 arch: qemu-rv: Add M-timer handling for BUILD_KERNEL
Summary:
- In RISC-V, BUILD_KERNEL uses S-mode and to use M-mode timer
  we need to handle it by using OpenSBI or self-implementation.
- This commit adds M-timer self-implementation for BUILD_KERNEL.

Impact:
- qemu-rv only

Testing:
- Tested with rv-virt:knsh64 on qemu-6.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-03 23:26:11 +08:00
Masayuki Ishikawa
b3e300f8e6 arch: qemu-rv: Fix qemu_rv_start_s() for S-mode
Summary:
- I found inappropriate SET_CSR() usage in the function.
- This PR fixes this issue.

Impact:
- None

Testing:
- tested with rv-virt:knsh64

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-02 22:32:07 +08:00
Xiang Xiao
bdeaea3742 Remove the unnessary empty line after label
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-30 17:54:56 +02:00
Xiang Xiao
70290b6e38 arch: Change the linker generated symbols from uint32_t to uint8_t *
and remove the duplicated declaration

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-24 21:26:56 +02:00
Xiang Xiao
3c1c29f2c4 arch: move non arm g_current_regs defintion to common place
to avoid the code duplicaiton

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-21 22:23:11 +02:00
Ville Juven
ff05cc593f risc-v/mmu: Fix L3 mappings for kernel, and mpfs protected mode userspace
The L3 mapping function was just way too simplistic. Depending on memory
configuration it either works or not.

Noticed that with icicle:pnsh the software crashes due to instruction
page fault, reason is the map_region() implementation that does not
work for regions that are not aligned to 2MB (the L2 page size).

Implemented an extremely simplistic page table allocator for the L3
references, that should once and for all get rid of the L3 mapping issue.

NOTE: gran_alloc() cannot be used at this point, it is too early for it.
2022-09-12 18:01:08 +09:00
Masayuki Ishikawa
548540eb13 arch: qemu-rv: Fix high CPU usage in SMP mode
Summary:
- I noticed that QEMU shows high CPU usage if the number of
  CPUs does not match the kernel configuration. (e.g. -smp 8
  and CONFIG_SMP_NCPUS=2)
- This commit fixes this issue.

Impact:
- qemu-rv only

Testing:
- Tested with the following configs
  - rv-virt:smp64 (CONFIG_NCPUS=1/2/8)
  - rv-virt:nsh64

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-08-13 22:41:42 +03:00
Ville Juven
31bb362aab risc-v: Fix kernel MMU mapping for L3 table
The L3 table address was calculated incorrectly. For every 2MiB of
mapped memory, an offset of 4KiB is needed from the base of the L3
table. The old calculation failed if paddr was not aligned to a 2MiB
boundary.
2022-08-09 23:14:46 +08:00
Nathan Hartman
20bdd44e7b Remove executable permission from source and build files. 2022-08-04 12:48:18 -03:00
Ville Juven
cfebb5a5c1 risc-v: Move common memory map to its own file from riscv_internal
Move the linker defined symbols to a separate file, so they can be
accessed without pulling in everything from riscv_internal.h and
whatever it includes (e.g. syscall.h drags in a lot).
2022-06-28 14:41:56 +03:00
Huang Qi
9d9d591b93 arch/risc-v: Unify common source include
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-05-31 07:59:33 +03:00
Huang Qi
eb02528a39 arch/risc-v/qemu-rv: Fix a typo in Make.defs 2022-05-30 19:58:43 +08:00
chao.an
3f65b562bb arch: inline up_interrupt_context()
inline the up_interrupt_context() to avoid unnecessary stack pushes

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-05-26 04:36:07 +08:00
Masayuki Ishikawa
3193aa3c97 arch: risc-v: Add MMU support for qemu-rv
Summary:
- This commit adds MMU support for qemu-rv
- Please note that mtimer is disabled for S-mode because
  the mtimer needs to be accessed in M-mode

Impact:
- qemu-rv only

Testing:
- Tested with rv-virt:knsh64 (will be pushed later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-13 04:14:01 +08:00
Masayuki Ishikawa
5a9b2920e8 arch: risc-v: Add support for semihosting and hostfs
Summary:
- This commit adds support for semihosting and hostfs

Impact:
- None

Testing:
- Tested with nsh and nsh64 (defconfig will be updated later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-02 19:46:58 +08:00
Ville Juven
a014daf44f RISC-V: Add implementation for vfork 2022-04-25 15:44:32 +08:00
chao.an
29005bd79f board/arch_fpu*: move arch_[get|cmp]fpu to common arch
rename the arch api:
arch_getfpu  -> up_saveusercontext
arch_cmpfpu  -> up_cmpfpu

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-18 22:22:16 +08:00
chao.an
5bdfae66ce arch/arm: export arm_saveusercontext()
rename arm_saveusercontext() -> up_arm_saveusercontext()

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-18 22:22:16 +08:00
Ville Juven
370152f3ba RISC-V: Move mhartid to own assembly macro+function
Hartid and cpuindex are not the same thing. Hartid is needed regardless
of SMP, for external interrupt handling etc.

SMP needs cpuindex which might not be index == hartid, so both are
needed. IMO it is clearer to provide separate API for both.

Currently the implementation of up_cpu_index is done a bit lazily,
because it assumes hartid == cpu index, but this is not 100% accurate,
so it is still missing some logic.
2022-04-13 12:00:40 +02:00
Huang Qi
1975878835 arch/risc-v: Apply common mtime driver to mtime based chps
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-12 12:14:40 +03:00
Ville Juven
2670f143b5 RISC-V: Add setintstack for k210 and qemu
This fixes CI issue, and I think the old implementation with SMP
shared 1 IRQ stack for multiple CPUs.
2022-04-12 01:59:35 +08:00
Ville Juven
b0a71ce3e7 RISC-V: Remove riscv_cpuindex.c from platforms that don't need it
riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.

Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
2022-04-12 01:59:35 +08:00
Huang Qi
9284770f75 arch/risc-v: Move epc adjustment to riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-10 00:52:04 +08:00
Huang Qi
833211680a arch/risc-v: Attach exception handler in common place
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-10 00:52:04 +08:00
Huang Qi
36bc8d2131 arch/risc-v: Align prototype of riscv_exception with xcpt_t
Thus we can attach it to irq handler without any cast.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-10 00:52:04 +08:00
Xiang Xiao
3a26cf6a02 arch/risc-v: Remove the unnecessary inclusion of board header files
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-07 11:25:12 +03:00
Huang Qi
53fef8d9c4 arch/risc-v: Replace riscv_fault with riscv_exception
Remove riscv_fault since its code is duplicated with riscv_exception,
and there are textual excpetion reason in riscv_exception.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-06 22:48:46 +08:00
Ville Juven
c15b6701ce RISC-V: Implement option to run NuttX in supervisor mode (S-mode)
- Add config "ARCH_USE_S_MODE" which controls whether the kernel
  runs in M-mode or S-mode
- Add more MSTATUS and most of the SSTATUS register definitions
- Add more MIP flags for interrupt delegation
- Add handling of interrupts from S-mode
- Add handling of FPU from S-mode
- Add new context handling functions that are not dependent on the trap
  handlers / ecall

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
      thus S-mode is not usable as is, yet.
2022-04-01 16:19:42 -03:00
Petro Karashchenko
870ca12146 arch/risc-v: get wider visibility for arch instruction macros
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-04-01 10:31:24 +08:00
Petro Karashchenko
36b0b95eb1 arch/risc-v: include csr.h indirectly through nuttx/irq.h
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-31 19:34:52 +08:00
Petro Karashchenko
5d856971db arch/risc-v: move REGLOAD/REGSTORE macro to riscv_internal.h
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-31 19:34:52 +08:00
Huang Qi
32fe25278a arch/risc-v: Merge duplicated logic by riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00
Huang Qi
904f7aabda arch/risc-v: Use riscv_fpuconfig to enable FPU
Use common function instead of chip specified code.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-30 01:33:04 +08:00
Huang Qi
35f9265483 arch/risc-v: Move fpu [re]store to common place
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-28 13:41:57 +08:00
Huang Qi
494230a841 arch/risc-v: Improve performance of context switch
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-26 07:19:09 +09:00
Petro Karashchenko
7afedda89e arch/risc-v: improve style consistency accross chip variants
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-25 10:26:15 -03:00
Huang Qi
f09ea317c1 risc-v/qemu-rv: Restore FPU context after context switch
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-23 19:30:04 +08:00
Huang Qi
00efcd3308 arch/risc-v: Merge riscv_getnewintctx into common
And also mask the bits which should be preserved (from ISA spec)

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-19 17:38:18 +08:00
Huang Qi
807304f283 arch/risc-v: Rework riscv_get_newintctx
Some fields of mstatus were marked as Reserved Writes Preserve Values, Reads Ignore Values (WPRI),
so we must keep its origin value with addition flags.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-17 15:43:30 +08:00
Xiang Xiao
54e630e14d arch: Merge up_arch.h into up_internal.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-14 09:32:17 +02:00
Huang Qi
e383439dda risc-v: Replace all inline assembly with macro
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-03 19:55:54 +08:00