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50 Commits

Author SHA1 Message Date
zhangyuan21
7d34ebdd4e armv7-a: add l2 page mapping interface 2022-10-12 22:00:06 +08:00
zhangyuan21
466635a5e0 armv7-a: set normal memory shareable in smp mode 2022-10-12 19:54:09 +08:00
Fotis Panagiotopoulos
bbf3f2866d Fixed non-UTF8 characters. 2022-09-28 09:38:55 +08:00
ligd
c866b6be9a armv7a/r: add common operation CP15_SET/GET() 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-09-21 18:07:03 +08:00
Oki Minabe
f0fb530eaa arch: imx6: add support kernel build and smp 
Summary:
- add support BUILD_KERNEL and SMP for imx6
- prepare page tables of cpu1,2,3
- add sabre-6quad:knsh_smp config

Impact:
- imx6

Testing:
- getprime, smp on sabre-6quad:knsh_smp w/ qemu

Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
 2022-05-27 01:31:58 +08:00
Oki Minabe
3983efa47e armv7-a: smp: allocate page table for each cpu 
Summary:
- In case of SMP and ADDRENV, allocate the page table for each cpu
- Each cpu holds separated addrenv and MMU setting

Impact:
- armv7-a

Testing:
- sabre-6quad:smp w/ qemu
- sabre-6quad:knsh w/ qemu
- sabre-6quad:knsh_smp w/ qemu (WIP)

Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
 2022-05-06 18:30:20 +09:00
Oki Minabe
4fa21c4719 armv7-a: Inner Shareable TLB maintenance operations 
Summary:
- Use Inner Shareable for TLB maintenance operations
- Add config option as CONFIG_ARM_HAVE_MPCORE
- This PR is in preparation for smp with kernel build

Impact:
- armv7-a

Testing:
- sabre-6quad:smp w/ qemu
- sabre-6quad:knsh_smp w/ qemu (WIP)

Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
 2022-05-06 15:26:59 +09:00
Alin Jerpelea
3ea545e7f3 arch: arm: armv7-a: fix nxstyle errors 
Fix nxstyle errors to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-03-25 19:42:44 -07:00
Alin Jerpelea
1d1da330da arch: arm: armv7-a: Author Gregory Nutt: update licenses to Apache 
Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-03-25 19:42:44 -07:00
Masayuki Ishikawa
a20463642e arch: armv7-a: Fix MMU settings for SDRAM in SMP mode 
Summary:
- This commit fixes armv7-a deadlocks with D-cache in SMP mode.
- In SMP mode, MMU for SDRAM area must be set to shareable

Impact:
- SMP only

Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2020-11-14 16:40:01 -08:00
Masayuki Ishikawa
812257d058 arch: armv7-a: Fix style warnings in mmu.h 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2020-11-14 16:40:01 -08:00
Xiang Xiao
cde88cabcc Run codespell -w with the latest dictonary again 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-02-23 22:27:46 +01:00
Xiang Xiao
80277d1630
Refine the preprocessor conditional guard style (#190) 2020-01-31 19:07:39 +01:00
zhangyuan7
471a18ee4d arch/arm: Add the initial cortex-a7 archtiecture support 2019-03-19 11:51:29 -06:00
Xiang Xiao
cc1595f232 arm/armv7-a: Add mmu_l1_map_regions() to remove the code duplication. 2019-03-19 11:30:37 -06:00
Bilal Wasim
1690f2ca8b arch/arm/src/armv7-a/mmu.h: pdating the cp15_wrttb and cp15_wrdacr functions to use inline assembly in the correct way. The incorrect method was generating errors as ARMv7-a expects the MCR/MRC instructions to provide registers as an argument(MRC p15, 0, <Rt>, c2, c0, 0) and the code was providing a constant value(and hence the build error). 2019-03-14 17:14:56 -06:00
Petro Karashchenko
5e48ca91fc arch/arm/src/armv7-a/mmu.h: Fix some typos; Use TLBIMVA vs TLBIMVAAIS to invalidate the Cortex-A8 cache. 2019-01-06 07:49:21 -06:00
Gregory Nutt
7cf88d7dbd Make sure that labeling is used consistently in all function headers. 2018-02-01 10:00:02 -06:00
Gregory Nutt
26560cb9e1 i.MX6: Remove non-cached, inter-cpu memory region. Not a useful concept. 2016-12-13 16:59:50 -06:00
Gregory Nutt
b2ba12e02a SMP: Basic function 2016-11-26 14:23:23 -06:00
Gregory Nutt
785ed5faf2 SMP: A few more compile/link issues. Still problems. 2016-11-26 13:20:11 -06:00
Gregory Nutt
aae306e942 i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region. 2016-11-26 12:04:02 -06:00
Gregory Nutt
130bfa3f6b Remove a assertion condition that appears to rarely cause false-alarm assertions. Teported by Petteri Aimonen 2016-11-21 14:43:56 -06:00
Gregory Nutt
edecfc2dac ARMv7-A: Cosmetic changes 2015-12-14 08:42:39 -06:00
Gregory Nutt
36726b1bc4 Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
Gregory Nutt
29136e51cc Clean up and review of header files for conformance to standards 2015-06-12 19:26:01 -06:00
Gregory Nutt
8b64dc003e SAMA5D4-EK: In kernel build with address environment, need logic to map user virtual addresses to physical addresses, and vice versa 2014-09-07 19:25:30 -06:00
Gregory Nutt
4fa5b52e43 Cortex-A address environments: Fix issue with page privileges 2014-08-28 11:00:41 -06:00
Gregory Nutt
b3473bfa26 Cortex-A address environment: Fix some section mapping and address increments 2014-08-26 06:33:26 -06:00
Gregory Nutt
a593729cb2 ARMv7-A: Use of write back might be unpredictable 2014-08-25 16:34:22 -06:00
Gregory Nutt
699a54a022 Misc changed to get the SAMA5 ELF configuration with address environments working 2014-08-25 13:28:13 -06:00
Gregory Nutt
8907616478 Cortex-A/SAMA5 address environment support is code complete (untested) 2014-08-25 11:18:32 -06:00
Gregory Nutt
e4fd434a60 Cosmetic update to comments and README files 2014-04-24 12:44:30 -06:00
Gregory Nutt
0d2e525bd4 Updated comments; minor correction in some naming 2014-04-23 14:46:39 -06:00
Gregory Nutt
78607a7ea9 SAMA5: Don't use MMU PMD bufferable bit to try to control write-through vs write-back. It does not work that way 2014-04-04 16:05:20 -06:00
Gregory Nutt
d28622a628 Replace explicit hex MMU value with definition 2013-12-18 12:47:43 -06:00
Gregory Nutt
98ffd096a0 SAMA5 LCDC: Correct how framebuffer memory was being mapped; Remove options to get framebuffer memory in various. Because of the mapping and aligment requirements, those options really cannot be supported 2013-10-13 13:08:05 -06:00
Gregory Nutt
b00d72a7f2 SAMA5: More MMU-related changes to properly initialize SDRAM 2013-08-02 11:11:57 -06:00
Gregory Nutt
547f9be80f SAMA5: More cache and mmu inline utility functions 2013-07-29 19:57:15 -06:00
Gregory Nutt
7dfabf3507 SAMA5: Correct a clock configuration bug; clarify some MMU memory types 2013-07-28 12:44:06 -06:00
Gregory Nutt
ae6ed8ca52 SAMA5: Fix heap allocation bugs 2013-07-27 11:28:31 -06:00
Gregory Nutt
14093ef76a Add a hello world configuration to help with the SAMA5 bringup 2013-07-26 15:28:01 -06:00
Gregory Nutt
f87963accd SAMA5: If the page table is in high memory, make sure that it is excluded from the heap 2013-07-26 09:16:46 -06:00
Gregory Nutt
696f6d0482 Misc Cortex-A5 MMU-related fix -- still does not boot 2013-07-25 16:37:55 -06:00
Gregory Nutt
cb3f394d53 Improve some ARMv7-A/M floating point register save time; Add floating point register save logic for ARMv7-A 2013-07-23 17:52:06 -06:00
Gregory Nutt
0b46176b43 A few more Cortex-A5 and SAMA5 files 2013-07-21 12:52:38 -06:00
Gregory Nutt
0d9250fae5 Misc Cortex-A5 changes include new file for cache operations 2013-07-20 13:06:00 -06:00
Gregory Nutt
6f0e07d071 A few more SAMA5D3 files 2013-07-19 17:45:28 -06:00
Gregory Nutt
c294e9b374 More ARMv7-A files that are just copies of the ARMv4/5 files for now 2013-07-19 11:43:04 -06:00
Gregory Nutt
28a90ba46d Some initial frame for Cortex-A5 support. No much yet 2013-07-18 15:20:47 -06:00