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Author SHA1 Message Date
Huang Qi
d846bb0235 arch/risc-v: Remove dupped irq code from mpfs 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-21 00:44:43 +08:00
Huang Qi
6dc4dd207f arch/risc-v: Remove dupped irq code from rv32m1 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-21 00:44:43 +08:00
Huang Qi
089dc2e090 arch/risc-v: Remove dupped irq code from litex 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-21 00:44:43 +08:00
Huang Qi
d1edd887d5 arch/risc-v: Remove dupped irq code from c906 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-21 00:44:43 +08:00
Huang Qi
bd57229f3c arch/risc-v: Remove dupped irq code from bl602 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-21 00:44:43 +08:00
Huang Qi
8532feda78 arch/risc-v: Remove dupped irq code from fe310 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-21 00:44:43 +08:00
Huang Qi
e81439a367 arch/risc-v: Remove dupped irq code from k210 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-21 00:44:43 +08:00
Huang Qi
7738bb98fc arch/risc-v: Remove dupped irq code from qemu-rv 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-21 00:44:43 +08:00
Huang Qi
f43d677c2e arch/risc-v: Unify common irq code to arch/irq.h 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-21 00:44:43 +08:00
Xiang Xiao
2935751bfd Fix error: implicit declaration of function 'up_cpu_index' 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 23:21:21 +08:00
Xiang Xiao
aa2cdcd848 xtensa/esp32: Change "cpu <= CONFIG_SMP_NCPUS" to "cpu < CONFIG_SMP_NCPUS" 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 23:21:21 +08:00
Xiang Xiao
77792a1598 sched: Define CONFIG_SMP_NCPUS to 1 in no SMP case 
to simplify the SMP related code logic

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 23:21:21 +08:00
Xiang Xiao
04297c3ca3 board: Remove -fno-omit-frame-pointer from Make.defs 
except sim arch, since this flag is set inside Toolschain.defs now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 16:00:48 +01:00
Xiang Xiao
c5c50acb93 board: Remove -fstrict-volatile-bitfields 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 16:00:48 +01:00
Xiang Xiao
3e28192b2f board/bl602: Remove -fshort-enums 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 16:00:48 +01:00
Xiang Xiao
a9e4c6ace1 libc: backtrace_malloc change sprintf to snprintf 
since snprintf can handle NULL pointer but sprintf can't.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 14:33:29 +01:00
Ville Juven
0a1a1e9b79 Fix user PGT flags (don't map them globally) 
A global mapping means it exists in all address environments. Only
kernel mappings should be mapped as global.
 2022-01-20 20:30:13 +08:00
Ville Juven
56ade25f31 Add pte getter to RISC-V MMU driver 
Like the title says, a getter to read one PTE.
 2022-01-20 20:30:13 +08:00
Ville Juven
c4b3672937 RISC-V MMU driver: fix region setting for L1/L2 page tables 
The region setting worked for L3 (Sv39) entries only. This fixes the
procedure so that L1 (Gigapages) or L2 (Megapages) can be also set
with it.
 2022-01-20 20:30:13 +08:00
Ville Juven
e676d2985d Present common MMU flags in common MMU driver header 
Flags to use for intermediate page tables, as well as leaf entries
 2022-01-20 20:30:13 +08:00
Ville Juven
33435e76da Changes to Sv39 MMU driver public header 
- Define RV_MMU_PT_LEVELS as the arch max
- Add way to find the PPN from a PTE
- Make utility function to create a satp register value, instead of
  combining this to mmu_enable
- Add function to read the current satp value
- Add function to write the satp register, also fix the fence instruction
 2022-01-20 20:30:13 +08:00
Ville Juven
926a19217e Add simple MMU driver for RISC-V (Sv39) 
Sv39 is the only mode supported for now. However, it should be trivial
to extend the driver to support the other modes (including Sv32) as well.

The driver is tested with mpfs only, but it should work with any riscv
implementation.
 2022-01-20 20:30:13 +08:00
Juha Niskanen
2b63b811e0 libs/libc/misc/lib_execinfo.c: fix bad memory access 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2022-01-20 18:58:40 +08:00
Alexander Lunev
64dd669749 net/tcp/sendfile: retransmit only one the earliest not acknowledged segment 
(according to RFC 6298 (5.4)). The issue is the same as it was in tcp_send_unbuffered.c.
 2022-01-20 18:37:39 +08:00
Eero Nurkkala
133faf203d risc-v/mpfs: don't reset uart1 while entering OpenSBI 
u-boot/kernel may use any uart, not just uart1, depending
on the device tree configuration. They will also reset the
corresponding uarts as well. It doesn't need to be done
here.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-01-20 18:37:08 +08:00
Eero Nurkkala
54a4eb01ce risc-v/mpfs: avoid OpenSBI redefinition conflicts 
This drops the dependency to riscv_internal.h which ensures
less redefinition conflicts. OpenSBI declares some of the
variables again which are spread in many NuttX files.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-01-20 18:37:08 +08:00
Xiang Xiao
9c74380b11 tools/ci: Enable build sim:cxxtest 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 18:01:54 +08:00
Xiang Xiao
67fc54dd3d boards/sim: Change CONFIG_LIBCXX to CONFIG_HAVE_CXXINITIALIZE 
since the contructor is required with other libc++ implementation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 16:20:41 +08:00
Xiang Xiao
af7fd718cc arch/sim: Don't add -lc++abi to STDLIBS 
link libs/libxx/libcxxabi instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 16:20:41 +08:00
YAMAMOTO Takashi
10f7ad85e6 arch/sim/src/nuttx-names.in: Add mprotect and sysconf 
For up_macho_init.c.
 2022-01-20 15:09:17 +08:00
YAMAMOTO Takashi
f0acf8e62a arch/sim/src/sim/up_macho_init.c: Add a workaround for Monterey 2022-01-20 15:09:17 +08:00
Xiang Xiao
2763f67640 tools/ci: Remove testlist/all.dat 
since it isn't used anymore and mismatch with other *.dat

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 14:46:56 +08:00
Alexander Lunev
ea6141e01b Documentation: added "Testing / capturing TCP network traffic" section, including packet loss emulation 2022-01-20 14:15:33 +08:00
Petro Karashchenko
08043fb5bc net: unify FAR keyword usage for all net buffer memory mapped buffers 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-20 01:42:56 +08:00
Jukka Laitinen
fc3167b584 boards/riscv/mpfs: Remove reference to .vectors in linker scripts 
There is no such section. Instead, place the object mpfs_head.o at the start of
the text.

Put mpfs_head.o directly into the arch library; there is no need to define
it separately in HEAD_ASRC.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-01-20 01:37:34 +08:00
Jukka Laitinen
6428c1fdc4 arch/riscv/mpfs: Switch to use riscv_exception_common 
Clean up mpfs port by using the common code

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-01-20 01:37:34 +08:00
Jukka Laitinen
7b8eec3fa4 arch/risc-v/src/common/riscv_exception_common.S: Add support for > 2 CPUs 
Add a new configuration for CONFIG_N_IRQ_STACKS, whcih defaults to
CONFIG_SMP_NCPUS or 1
- this allows configuring multiple IRQ stacks also in the case where SMP
  support is not needed
- this is specifically needed in mpfs target, where "bootloader" build boots
  only on one hart, but the startup code executes on all harts and handles SW IRQs

Also don't store/restore GP if RISCV_SAVE_GP is not defined. If the GP is not
stored in fork, it can't be restored for new tasks

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-01-20 01:37:34 +08:00
Petro Karashchenko
767cf282c7 boards/arm/samv7: move HSMCI interface to common 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-20 01:24:14 +08:00
yinshengkai
face0514b6 touchscreen: update sim_touchscreen, using touch_upperhalf 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2022-01-20 01:22:25 +08:00
yinshengkai
3bb4e053fe driver/uinput: add uinput button support 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2022-01-20 01:20:19 +08:00
yinshengkai
377c15955e driver: add uinput support 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2022-01-20 01:20:19 +08:00
yinshengkai
676b735c4a driver/touchscreen: Add support for write operations 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2022-01-20 01:20:19 +08:00
YAMAMOTO Takashi
ec54c4e30d tools/ci/testlist/sim-01.dat: Enable libcxxtest for macOS 2022-01-20 01:16:56 +08:00
YAMAMOTO Takashi
a3c96a520f task_startup: Implement cxx_initialize for sim/macOS 2022-01-20 01:16:56 +08:00
YAMAMOTO Takashi
a94c52b204 sim: Postpone constructor calls on macOS 
For Linux, we rename the section so that they are not invoked.
However, it doesn't work for macOS.

Notes:

* Renaming the sections (as the Linux version does) doesn't work
  because the section is looked by its flags, not by its names.

* No convenient tools available to alter the relevant bit in
  the section flags.

* The constructors are invoked before the program entry point.
 2022-01-20 01:16:56 +08:00
ligd
dd08815991 idle: remove heap & stack check in idle thread 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-01-20 01:14:56 +08:00
Daniel Agar
12c8a9626c stm32f7 serial fix PM_CONFIG build 2022-01-20 01:08:06 +08:00
zhuyanlin
793ec6c909 arch:xtensa:vectors:fix bugs in a0 save 
Use right EXCSAVE_X

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00
zhuyanlin
a1a9ce3d1e arch:xtensa_panic: use right interrupt pointer in xtensa_panic 
When enable interrupt stack, use a12 instead of sp

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00
zhuyanlin
88f5a209ce xtensa: move a3 save in handler instead of _xtensa_context_save 
As in _xtensa_syscall_handler, a3 was save and reused before
_xtensa_context_save, a3 save in _xtensa_context_save will generate
error.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00