Commit Graph

288 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
d87274c123 risc-v/esp32c3: Release stuck I2C slaves on Reset 2021-03-11 19:32:03 -03:00
Gustavo Henrique Nihei
cb1c415b46 risc-v/esp32c3: Add support for I2C tracing 2021-03-11 19:32:03 -03:00
Gustavo Henrique Nihei
0f508c1a5f risc-v/esp32c3: Fix erroneous index for I2C IRQ 2021-03-11 19:32:03 -03:00
Gustavo Henrique Nihei
0b672b9c57 risc-v/esp32c3: Fix I2C timeout register mask 2021-03-11 19:32:03 -03:00
Gustavo Henrique Nihei
11b1f0f9dd risc-v/esp32c3: Add driver for I2C peripheral 2021-03-11 19:32:03 -03:00
Xiang Xiao
c047c1412f Remove all gap8(risc-v) arch and board source code
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-03-11 10:51:11 -08:00
Xiang Xiao
c54d617f2c Remove nr5m100(risc-v) arch and board source code
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-03-11 10:51:11 -08:00
hotislandn
d898bc445c arch:rv64:c906:enable DP FPU support.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-03-11 10:34:47 +08:00
hotislandn
5e50938726 arch:riscv64:basic porting for C906.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-03-10 19:23:24 +08:00
Virus.V
c34667b450 risc-v/bl602:fix bl602_flash_erase to erase the wrong block 2021-03-09 07:56:00 -08:00
Gustavo Henrique Nihei
330eff36d7 sourcefiles: Fix relative path in file header 2021-03-09 23:18:28 +08:00
Gustavo Henrique Nihei
47cb41c92f makefiles: Fix relative path in file header 2021-03-09 23:18:28 +08:00
Sara Souza
c885e718a7 risc-v/esp32-c3: complements serial driver 2021-03-09 11:17:10 -03:00
Sara Souza
85a93be5d7 risc-v/esp32-c3: Adds timer driver 2021-03-09 11:16:53 -03:00
Sara Souza
d00e97cbca risc-v/esp32-c3:free cpu in case it was preallocated in wdt driver 2021-03-09 10:57:58 +00:00
Gustavo Henrique Nihei
fa36897541 risc-v/esp32c3: Fix Kconfig file formatting 2021-03-04 16:31:51 +00:00
Gustavo Henrique Nihei
b1b4190802 risc-v/esp32c3: Fix default GPIO function when no option is provided 2021-03-03 18:46:43 -08:00
Gustavo Henrique Nihei
bc335009d9 risc-v/esp32c3: Allow pin to be configured as Input and Output simultaneously 2021-03-03 18:46:43 -08:00
Abdelatif Guettouche
85620c3c1a risc-v/esp32c3: Add more flash options to esptool.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-03 18:28:18 -08:00
ligd
f9d20ea4d2 sigdeliver: fix system block when kill signal to idle in SMP
Bug description:

CONFIG_SMP=y

Suppose we have 2 cores in SMP, here is the ps return:

PID GROUP CPU PRI POLICY TYPE    NPX STATE     STACK   USED  FILLED COMMAND
  0     0   0   0 FIFO   Kthread N-- Assigned 004076 000748  18.3%  CPU0 IDLE
  1     0   1   0 FIFO   Kthread N-- Running  004096 000540  13.1%  CPU1 IDLE

nsh> kill -4 0
or:
nsh> kill -4 1

system blocked.

Reason:

In func xx_sigdeliver() restore stage, when saved_irqcount == 0, that means
rtcb NOT in critical_section before switch to xx_sigdeliver(), then we need
reset the critical_section state before swith back.

Fix:

Add condition to cover saved_irqcount == 0.

Change-Id: I4af7f95e47f6d78a4094c3757d39b01ac9d533b3
Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-03-03 15:03:32 +00:00
Abdelatif Guettouche
39016f6d68 risc-v/esp32c3: Configure clock and call board initialize at startup.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-25 22:13:26 -08:00
hotislandn
651b905b99 arch:rv64:add API up_copyfullstate for later FPU support.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-02-25 11:26:27 -08:00
Gustavo Henrique Nihei
7fe096c65e risc-v: Fix typos reported by codespell 2021-02-25 16:25:47 +00:00
hotislandn
30cb7d3983 arch:rv32:up_sigdeliver missing fpu contexts.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-02-24 23:42:18 -08:00
Gustavo Henrique Nihei
6edeb9ebd9 risc-v/esp32c3: Free CPU interrupt if irq_attach fails 2021-02-24 15:56:26 +00:00
Gustavo Henrique Nihei
5c24c98880 risc-v/esp32c3: Invalidate CPU interrupt number after free 2021-02-24 15:56:26 +00:00
Abdelatif Guettouche
fb68a4b777 esp32c3: Add system reset.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-23 18:13:02 -08:00
Gustavo Henrique Nihei
48ff647fe9 risc-v/esp32c3: Fix erroneous references to ESP32-C3 2021-02-23 18:12:16 -08:00
Gustavo Henrique Nihei
af8e71d9e9 risc-v/esp32c3: Fix inconsistent guard comment 2021-02-22 09:24:14 -08:00
Gustavo Henrique Nihei
628e2288aa risc-v/esp32c3: Add missing header guard for lowputc 2021-02-22 09:24:14 -08:00
Gustavo Henrique Nihei
ca30c1db69 risc-v/esp32c3: Build serial driver only when selected 2021-02-22 09:24:14 -08:00
Abdelatif Guettouche
491a4c1ed2 risc-v/esp32c3: Don't reserve any vectors for any special use.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-22 09:21:24 -08:00
Gustavo Henrique Nihei
291a5755cc risc-v/esp32c3: Add support for MWDT0 and MWDT1 2021-02-22 17:18:01 +00:00
Abdelatif Guettouche
067da56d0c esp32c3: Some cosmetics and style fixes.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-21 10:29:43 -03:00
Abdelatif Guettouche
10822799fb esp32c3: Add GPIO IRQ support.
The GPIO example was also extended to include testing an interrupt pin.

Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Co-authored-by: Alan Carvalho <alan.carvalho@espressif.com>
2021-02-21 10:29:43 -03:00
Alan Carvalho
4a42998f36 esp32-c3: Add the GPIO driver.
This commits adds support for the ESP32-C3 IO Mux and GPIO Matrix.  It
also includes necessary board logic to run the GPIO example with 2
outputs.

Co-authored-by: Alan Carvalho <alan.carvalho@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-21 10:29:43 -03:00
Abdelatif Guettouche
4c3412faaa risc-v/esp32c3: Add clock configuration
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-18 01:21:53 -08:00
Sara Souza
998f7e5d4c risc-v/esp32c3: Add basic UART support for console 2021-02-18 01:21:53 -08:00
Dong Heng
b11a5ca8b2 risc-v/esp32c3: Add ESP32-C3 basic support
Co-authored-by: Dong Heng <dongheng@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-18 01:21:53 -08:00
David Jablonski
41bddc8461 litex: fix mtime and mtimecmp register address 2021-02-13 15:24:28 -08:00
David Jablonski
11167857c3 litex: nsh working 2021-02-13 15:24:28 -08:00
jpeng
af42079cc7 fix spi bug 2021-02-13 10:31:25 -08:00
liang
5914af84c7 arch/risc-v/bl602: spi_master support. 2021-02-13 10:31:25 -08:00
hotislandn
84daebf2cc arch:risc-v:bl602: enable FPU for this target. 2021-02-08 00:29:34 -08:00
Masayuki Ishikawa
d87f350831 arch, boards, drivers, include, sched, wireless: Change spinlock APIs.
Summary:
- This commit changes spinlock APIs (spin_lock_irqsave/spin_unlock_irqrestore)
- In the previous implementation, the global spinlock (i.e. g_irq_spin) was used.
- This commit allows to use caller specific spinlock but also supports to use
  g_irq_spin for backword compatibility (In this case, NULL must be specified)

Impact:
- None

Testing:
- Tested with the following configurations
- spresnse:wifi, spresense:wifi_smp
- esp32-devkitc:smp (QEMU), sabre6-quad:smp (QEMU)
- maxi-bit:smp (QEMU), sim:smp
- stm32f4discovery:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-07 21:28:56 -08:00
Abdelatif Guettouche
6547c3df55 arch/riscv: Fix file names in headers that were still using the old 'up_' prefix.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-05 21:19:20 -03:00
Abdelatif Guettouche
5447f28742 riscv: Remove the nx_start prototype from riscv_internal.h
This function is already declared in include/nuttx/init.h include this
file instead.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-02 17:48:40 -03:00
Abdelatif Guettouche
db2a8f0dc5 arch/risc-v: Remove incorrect ARM references.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-02 17:48:06 -03:00
Abdelatif Guettouche
37b93bd498 arch/risc-v: Don't declare riscv_addregion if CONFIG_MM_REGIONS is < 1.
Don't declare riscv_addregion if CONFIG_MM_REGIONS is < 1, so we won't
have to provide a dummy stub for every chip.
Also rename the function from up_addregion to riscv_addregion since it's
not exported outside the arch directory.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-01 18:45:25 -08:00
Abdelatif Guettouche
52b4c73a61 arch/riscv: Remove references to MIPS.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-01-30 15:46:38 -08:00