Commit Graph

20757 Commits

Author SHA1 Message Date
Xiang Xiao
da5e978341 mm: Correct the callsite of mm_mallinfo
forget to update in https://github.com/apache/nuttx/pull/9488

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-06-11 19:37:04 +03:00
Xiang Xiao
d920bfba10 mm: include malloc.h in mm/mm.h
to remove the forward declaration of mallinfo and mallinfo_task

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-06-11 19:37:04 +03:00
Petro Karashchenko
509a808e84 arch/arm/stm32f7: fix typo
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-06-11 12:55:29 +08:00
Petro Karashchenko
1b801a5bbc style: remove extra spaces and align parameters
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-06-11 12:55:29 +08:00
Petro Karashchenko
2a38c38b03 style: fix style issues found during code review
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-06-11 12:54:52 +08:00
Ville Juven
37bf542c9e mpfs/mpfs_shead.S: Remove MMU mappings and flush TLB upon boot
This fixes warm reset crash when trying to access memory via old stale
MMU mappings
2023-06-10 01:36:59 +08:00
Ville Juven
7bc8e59cce riscv/kernel_stack: Use kernel stack to store the user context
If a kernel stack exists, use that whenever the user process is in
privileged mode, i.e. running an exception or in system call. Previously
the exception context was stored into the user's stack, which is not ideal.

Why?

1. Because the exception entry status (REG_INT_CTX) is needed by the
   kernel, and this is now in user memory which requires that the correct
   user mappings are active when it is accessed.

2. The user must currently account for the exception stack frame (which
   is BIG) in its own stack allocation. Moving the exception context save
   to the kernel stack offloads this responsibility from the user to the
   kernel, which is IMO the correct behavior.

3. The kernel access to user memory is currently allowed without condition,
   however this is not ideal either. The privileged mode status CSR allows
   blocking access to user memory via the STATUS_SUM-bit, which should be
   disabled by default and only enabled when access to user space is really
   needed. This patch allows implementing such features.
2023-06-09 13:53:27 +08:00
Ville Juven
a636edcbe4 addrenv/kstack: Allocate the kernel stack before initializing tcb
This is preparation to use kernel stack for everything when the user
process enters the kernel. Now the user stack is in use when the user
process runs a system call, which might not be the safest option.
2023-06-09 13:53:27 +08:00
anjiahao
7732791cd6 mempool:Add mail_info support for multiple pools
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-06-08 23:56:40 +08:00
Fotis Panagiotopoulos
b89215a11f Fixed Kconfig options for the obsolete GD32F4_TICKLESS_SYSTICK & STM32WB_TICKLESS_SYSTICK options. 2023-06-07 11:10:34 -06:00
SunJ
ad4e2f0922 arch/riscv: Fixed FPU context save/restore error
Always save/restore FPU context if the current thread use FPU

Signed-off-by: SunJ <jsun@bouffalolab.com>
2023-06-07 16:39:51 +03:00
Fotis Panagiotopoulos
a57cd563d5 stm32: Removed unused Kconfig option.
The option STM32_TICKLESS_SYSTICK is not used anywhere and the
stm32 arch does not have the capability to use systick as a
tickless timer.
2023-06-07 09:40:55 -03:00
chenwen@espressif.com
617927f27c xtensa/esp32: Support multiple PHY init data bin
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2023-06-07 16:44:26 +08:00
GD32-MCU
fdfc25cf56 add sdio driver for GD32F4 2023-06-07 16:43:55 +08:00
Ville Juven
0a9279f672 MPFS: Use NuttX SBI for Kernel mode 2023-06-07 01:48:15 +08:00
Ville Juven
2525c10729 RISC-V: bind NuttX native SBI to SBI glue logic 2023-06-07 01:48:15 +08:00
Ville Juven
ae64f28344 RISC-V: Implement simple and native NuttX SBI
This is a minimalistic SBI implementation for NuttX.

Provides a single service for now:
- Access to machine timer

Provides a start trampoline to start NuttX in S-mode:
- Exceptions / faults are delegated to S-mode.
- External interrupts are delegated to S-mode.

Machine mode timer is used as follows:
- The timer compare match register reload happens in M-mode, via
  call gate "riscv_sbi_set_timer"
- The compare match event is dispatched to S-mode ISR, which will
  notify the kernel to advance time
- Clearing the STIP interrupt does not work from S-mode,
  so the call gate does this from M-mode

The only supported (tested) target for now is MPFS.
2023-06-07 01:48:15 +08:00
chao an
76e5204a80 risc-v/backtrace: correct stack pointer if enable ARCH_KERNEL_STACK
Signed-off-by: chao an <anchao@xiaomi.com>
2023-06-07 01:44:28 +08:00
chao an
b7b3c3c550 arm/backtrace: validate PC register before process unwind
Signed-off-by: chao an <anchao@xiaomi.com>
2023-06-07 01:40:30 +08:00
Ville Juven
a41f752ecc kmm/kmm_map: Add missing FAR qualifiers 2023-06-05 12:03:37 +03:00
Xiang Xiao
add569d0e5 arch/sim: Replace uart_[xmit|recv]chars_dma with uart_dma[txavail|rxfree]
to follow the original dma design

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-06-05 09:25:31 +02:00
Alexander Merkle
961a68b4cf arch/arm: initial FPU support for armv8r aarch32
CortexR52 can have a optional FPU.
- VFPv3 with FP16
- Option 1: 16 x double-prevision registers - -mfpu=vfpv3-d16-fp16
- Option 1: 32 x double-prevision registers - -mfpu=vfpv3-fp16
2023-06-04 16:49:34 -03:00
Alexander Merkle
2b6209147e arch/arm: cleanup arm_head.S for armv8-r aarch32 2023-06-04 16:49:34 -03:00
Ville Juven
d193c50947 mpfs_corespi: Change default motorola mode to MODE3 2023-06-02 11:13:02 -03:00
Ville Juven
4d49f80e16 mpfs_corespi: Fix DEBUGASSERT() for clk divider
Valid range is 0...255, not 2...512
2023-06-02 11:13:02 -03:00
Peter Bee
59450bf9a9 arch/arm64: use adrp instead adr in bss init code
To support address offset larger than 1MB

Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
2023-06-02 11:02:14 -03:00
Masayuki Ishikawa
ec788d9398 arch: fvp-v8r: Fix warning when configuring fvp-armv8r:nsh_smp
Summary:
- I noticed that ./tools/configure.sh fvp-armv8r:nsh_smp shows
  warning: (ARCH_CHIP_FVP_R52 && ARCH_CHIP_FVP_R82) selects ARMV8R_HAVE_GICv3 which has unmet direct dependencies (ARCH_ARM && ARCH_ARMV8R)
- I think ARMV8R_HAVE_GICv3 is only used for aarch32.
- This commit fixes this issue.

Impact:
- None

Testing:
- Tested with nsh_smp on FVP

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-06-02 12:08:27 +08:00
Ville Juven
f28ac98de0 arch/risc-v: Add riscv_addrenv_pgmap
This is the counterpart for the kernel mapping functionality, i.e. it
implements the up_addrenv_xx functions needed by kmm_map
2023-06-02 10:50:26 +08:00
Ville Juven
1387c35213 arch/risc-v: Add method to extract PPN from SATP value
This makes it possible to get the physical page number (PPN) from any
SATP value, not only the currently active SATP register.
2023-06-02 10:50:26 +08:00
Ville Juven
376874d88b arch/risc-v: Add maximum user addrenv size and end boundary
Also in riscv_uservaddr() check the end boundary
2023-06-02 10:50:26 +08:00
Ville Juven
783f3f4c92 arch/risc-v: Move ARCH_ADDRENV_VBASE to addrenv.h
Move the user address environment base address to a public header and
add riscv_uservaddr query
2023-06-02 10:50:26 +08:00
Ville Juven
0476e30a6d mm/kmm_map: Add support to dynamically map pages into kernel virtual memory
This adds functionality to map pages dynamically into kernel virtual
memory. This allows implementing I/O remap for example, which is a useful
(future) feature.

Now, the first target is to support mapping user pages for the kernel.

Why? There are some userspace structures that might be needed when the
userspace process is not running. Semaphores are one such example. Signals
and the WDT timeout both need access to the user semaphore to work
properly. Even though for this only obtaining the kernel addressable
page pool virtual address is needed, for completeness a procedure is
provided to map several pages.
2023-06-02 10:50:26 +08:00
Tiago Medicci Serrano
118a127771 esp32_start: use up_putc instead up_puts in showprogress define
During initialization it isn't possible to use up_puts once it's
protected against concurrent access through a mutex lock. Instead,
using up_putc makes it similar to ESP32S2 and ESP32S3 and perfectly
fits for showprogress usage.
2023-06-02 10:17:54 +08:00
simbit18
7f551aa33f Fix Kconfig style
Remove TABs from Kconfig files
2023-06-01 23:45:42 +08:00
Alexander Merkle
c661e26e86 board: add CortexR52 FVP AEMv8R platform
see board/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/scripts/readme.txt

Port is highly based on fvp-v8r AARCH32 port.
2023-06-01 09:51:03 -03:00
Alexander Merkle
f6695738e1 arch/arm: add ARMv8-r(Cortex-R52) support
Basic work required for uniprocessor CortexR52 (ARMv8R AARCH32) using
GICv3 and CP15 mapped arch timer.

Tested on ARM FVP 11.20.

Port is based on ARMv8R AARCH64 and ARMv7R code. Excuse possible copy-paste leftovers.
2023-06-01 09:51:03 -03:00
raiden00pl
66c2d2ecc4 arch/nrf53/Kconfig: move GPIO configuration menu to match nrf52 2023-05-31 22:28:50 +03:00
raiden00pl
5f814b1da8 arch/{nrf52|nrf53}/Kconfig: hide SPI_MASTER options if SPI_MASTER not enabled 2023-05-31 22:28:50 +03:00
raiden00pl
81b0ae064c arch/{nrf52|nrf53}/Kconfig: hide I2C_MASTER options if I2C_MASTER not enabled 2023-05-31 22:28:50 +03:00
raiden00pl
a3b91bc183 arch/{nrf52|nrf53}/Kconfig: hide PWM options if PWM not enabled 2023-05-31 22:28:50 +03:00
Ville Juven
7c2930c3df mpfs/mpfs_corespi: Optimize TX / RX FIFO handling
Remove unnecessary reading of the status register when loading / unloading
the FIFOs. Reading from the IP block is slow due to BUS synchronization and
this basically makes the SPI busy loop for no reason at all, destroying the
CPU usage.

The overall benefit of these changes is approx. 25%-points, which is a
MASSIVE improvement.
2023-05-31 15:52:56 -03:00
Ville Juven
fc5e8ff8f8 mpfs/CoreSPI: Fix bug when waiting for last character to arrive
The logic for rx_fifo_empty is wrong, needs a loop for the retry to work
2023-05-31 15:52:56 -03:00
Jukka Laitinen
8d646fc49c arch/risc-v/src/mpfs/mpfs_corespi.c: Fix the usage of MPFS_CORESPI_INSTANCES macro
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-05-31 15:52:56 -03:00
Ville Juven
4b6166548b mpfs/mpfs_corespi: Add Kconfig for instance/irq offsets
Also change the defaults
2023-05-31 15:52:56 -03:00
Ville Juven
223cc6d1f4 mpfs/corespi: Add driver for CoreSPI
Adds a driver for an FPGA fabric / CoreSPI implementation.

Supports multiple instances, assuming they reside in some base address,
offsettable by a constant value.
2023-05-31 15:52:56 -03:00
raiden00pl
2d56197792 arch/{nrf52|nrf53}: validate if EasyDMA transfer is possible
Add an interface that validate if EasyDMA transfer is possible.
EasyDMA cannot access flash memory which can cause hard to detect silent bugs.
This feature is enabled if CONFIG_DEBUG_FEATURES=y and CONFIG_DEBUG_ASSERTIONS=y.
2023-06-01 00:40:17 +08:00
raiden00pl
b98acb9a44 arch/nrf53: add progmem support 2023-05-31 23:12:21 +08:00
Ville Juven
d566b7e2c7 mpfs_usb: Add mpfs_vbus_detect
External function to query vbus status. Reading from the block requires
the clock, but if no devices are open -> vbus detect does not work.

This creates a chicken / egg problem, if vbus detect is used to start
the usb device.
2023-05-31 22:59:25 +08:00
Filipe Cavalcanti
3fea2923d7 arch/arm/src/tiva: start FPU before gpio config 2023-05-31 22:47:55 +08:00
raiden00pl
1facea635b nrf52: add MCUboot support 2023-05-31 10:44:08 +08:00