Sebastien Lorquet
db24f237d7
STM32L4: Correct USART1/2 definitions. Use default mbed UART4 settings
2016-12-01 09:00:59 -06:00
Alan Carvalho de Assis
8b3a6d1eca
LPC43 SD/MMC: Correct some git definitions on SMMC control register in lpc43_sdmmc.h
2016-11-30 14:50:32 -06:00
Janne Rosberg
a03d26e88d
stm32_otghshost: if STM32F446 increase number of channels to 16
2016-11-30 12:17:12 -06:00
Gregory Nutt
44668c00a0
LPC17 Ethernet: Tiny, trivial, cosmetic spacing change
2016-11-30 12:16:21 -06:00
Gregory Nutt
934aded293
arch/: Adapt all Ethernet drivers to work as though CONFIG_NET_MULTIBUFFER were set. Remove all references to CONFIG_NET_MULTIBUFFER
2016-11-29 16:06:48 -06:00
Gregory Nutt
f06d521c10
Minor extensions to some comments
2016-11-29 10:01:38 -06:00
Gregory Nutt
79bb895073
i.MX6: Don't output the alphabet if CONFIG_DEBUG_FEATURES is not set.
2016-11-29 08:34:22 -06:00
Gregory Nutt
a8b69c3efe
Back out a debug change that was included in commit
2016-11-29 07:51:49 -06:00
Marc Rechté
3f91bd6056
STM32 DAC: Fix shift value whenever there are is a DAC2 and, hence, up to three interfaces.
2016-11-29 07:03:54 -06:00
Gregory Nutt
d65be718c2
sched_note: Extend OS instrumentation to include some SMP events.
2016-11-27 17:14:57 -06:00
Gregory Nutt
cbf98ae0a0
ARMv7 GIC: SGIs are non-maskable but go through the same path as other, maskable interrupts. Added logic to serialize SGI processing when necessary.
2016-11-27 13:18:34 -06:00
Gregory Nutt
21e42d18c1
ARMv7-A/i.MX6 SMP: Move SMP coherernt cache setup to earlier in initialization of CPUn, n>0
2016-11-27 11:28:24 -06:00
Gregory Nutt
cd54c71dc1
ARMv7-A/i.MX6: Modify handling of the SMP cache coherency configuration so that it is identical to the steps from the TRM. Makes no differenct, however.
2016-11-27 10:21:46 -06:00
Gregory Nutt
278d8330d6
arm_scu.c edited online with Bitbucket. Fux some typos.
2016-11-27 02:59:42 +00:00
Gregory Nutt
3f6eadc238
ARMv7-A: Fix some SCU SMP logic
2016-11-26 18:41:48 -06:00
Gregory Nutt
546e352830
i.MX6: Add some controls to enable SMP cache coherency in SMP mode
2016-11-26 17:46:20 -06:00
Gregory Nutt
3353d9280f
i.MX6: Disable non-cached region support. Add SCU register definitions.
2016-11-26 17:03:57 -06:00
Gregory Nutt
8dc79bb7ef
Update comments and README file
2016-11-26 16:02:37 -06:00
Gregory Nutt
b2ba12e02a
SMP: Basic function
2016-11-26 14:23:23 -06:00
Gregory Nutt
785ed5faf2
SMP: A few more compile/link issues. Still problems.
2016-11-26 13:20:11 -06:00
Gregory Nutt
6ff6da083f
Fix a few compile related issues from the last commit
2016-11-26 12:23:09 -06:00
Gregory Nutt
aae306e942
i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region.
2016-11-26 12:04:02 -06:00
Gregory Nutt
dda0ac8b21
Update comments
2016-11-26 11:06:24 -06:00
Gregory Nutt
9376296e99
Merge remote-tracking branch 'origin/master' into imx6-smp
2016-11-26 11:02:55 -06:00
Gregory Nutt
8bacb1e426
Update comments
2016-11-26 11:02:21 -06:00
Gregory Nutt
bdf570ea08
Fix typos in comments
2016-11-26 10:42:25 -06:00
Gregory Nutt
2fba04f752
i.MX6 SMP: Beginning of non-cacheable region (incomplete)
2016-11-26 10:37:06 -06:00
Gregory Nutt
61b45a8544
i.MX6: Add some comments
2016-11-26 09:27:29 -06:00
Gregory Nutt
e3fe320e08
SMP: Add support for linking spinlocks into a special, non-cached memory region.
2016-11-26 08:47:03 -06:00
Maciej Wójcik
0d0b1b64e2
Fix for F1 RTC Clock, tested on F103
2016-11-25 06:17:18 +01:00
Gregory Nutt
b08fb33c28
SMP: Fix typos in some conditional compilation
2016-11-24 17:59:45 -06:00
Gregory Nutt
7f636f2280
SMP: Add spin_trylock(). Use this in conditions where other CPUs need to stopped but we cannot call enter_critical_section.
2016-11-24 13:33:43 -06:00
Gregory Nutt
f77dcdf323
ARMv7-A SMP: Add a little logic to signal handling.
2016-11-24 11:45:05 -06:00
Gregory Nutt
c03d126da6
arm_cpupause.c edited online with Bitbucke. What was I thinking... Back out previous change.
2016-11-24 04:45:07 +00:00
Gregory Nutt
19e7f2210e
arm_cpupause.c edited online with Bitbucket. Fix a typo in a comment.
2016-11-24 04:24:40 +00:00
Gregory Nutt
4b0bbf41ca
SMP: Fix backward condition in test.
2016-11-23 22:24:14 -06:00
Alan Carvalho de Assis
7dbc25b02b
LPC43xx: Add timer driver; configs/bambino-200e: Add support for timer driver
2016-11-23 13:33:51 -06:00
Gregory Nutt
f90525a5d1
SMP: Update some comments; trivial improvement by inlining static function.
2016-11-22 16:48:57 -06:00
Gregory Nutt
12f830ffd5
SAM3/4: Name of method is now setcallback, not sethandler
2016-11-22 12:06:07 -06:00
Gregory Nutt
bac7153609
SMP: Add logic to avoid a deadlock condition when CPU1 is hung waiting for g_cpu_irqlock and CPU0 is waitin for g_cpu_paused
2016-11-22 11:34:16 -06:00
Sebastien Lorquet
ec586ab350
implementation of dumpgpio for stm32l4, was required for pwm debug.
2016-11-22 07:57:21 -06:00
Gregory Nutt
130bfa3f6b
Remove a assertion condition that appears to rarely cause false-alarm assertions. Teported by Petteri Aimonen
2016-11-21 14:43:56 -06:00
Gregory Nutt
0804286ad3
arch/: Add option to use low-priority work queue to all Ethernet drivers in arch that support CONFIG_NET_NOINTS.
2016-11-19 09:20:01 -06:00
Gregory Nutt
0db99b8c89
Trivial fix from review of last PR
2016-11-19 06:52:51 -06:00
Gregory Nutt
8705ce816a
Merged in gnagflow/nuttx (pull request #173 )
...
Master
2016-11-19 12:49:56 +00:00
Wolfgang Reißnegger
b23c1f8817
Typo fix in sam_udp.c
2016-11-18 17:23:22 -08:00
Wolfgang Reißnegger
d135246a7d
SAM3/4: Remove 'stalled' flag in UDP driver.
...
The flag is not necessary. The state of the endpoint can be determined
using 'epstate' instead.
2016-11-18 17:23:21 -08:00
Wolfgang Reißnegger
9e349f4335
SAM3/4: Remove unused 'halted' flag in UDP driver.
2016-11-18 17:23:21 -08:00
Wolfgang Reißnegger
c7ef82c546
SAM3/4: Add delay between setting and clearing the endpoint RESET bit in sam_ep_resume().
...
We need to add a delay between setting and clearing the endpoint reset
bit in SAM_UDP_RSTEP. Without the delay the USB controller will (may?)
not reset the endpoint.
If the endpoint is not being reset, the Data Toggle (DTGLE) bit will
not to be cleared which will cause the next transaction to fail if
DTGLE is 1. If that happens the host will time-out and reset the bus.
Adding this delay may also fix the USBMSC_STALL_RACEWAR in
usbmsc_scsi.c, however this has not been verified yet.
2016-11-18 17:23:21 -08:00
Paul A. Patience
8d9804d57b
STM32: STM32F303xB and STM32F303xC chips have 4 ADCs
2016-11-18 19:28:09 -05:00