If using flow control with a high CTS the thread may be
blocked forever on the second transmit attempt due to waiting
on the txdma semaphore. The calling thread can then never
make progress and release any resources it has taken, thus
may cause a deadlock in other parts of the system.
The implementation differs in behavior from interrupt-driven
TX. It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to
do next.
If using flow control with a high CTS the thread may be
blocked forever on the second transmit attempt due to waiting
on the txdma semaphore. The calling thread can then never
make progress and release any resources it has taken, thus
may cause a deadlock in other parts of the system.
The implementation differs in behavior from interrupt-driven
TX. It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to
do next.
If using flow control with a high CTS the thread may be
blocked forever on the second transmit attempt due to waiting
on the txdma semaphore. The calling thread can then never
make progress and release any resources it has taken, thus
may cause a deadlock in other parts of the system.
The implementation differs in behavior from interrupt-driven
TX. It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to
do next.
If using flow control with a high CTS the thread may be blocked forever
on the second transmit attempt due to waiting on the txdma semaphore.
The calling thread can then never make progress and release any
resources it has taken, thus may cause a deadlock in other parts of the
system.
The implementation differs in behavior from interrupt-driven TX and the
STM32F7 TXDMA . It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to do next.
Some APIs are implemented both in common code and CHIP-specific code,
and the link needs to be based on the implementation in CHIP, so move
NUTTX_CHIP_ABS_DIR before common src.
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
These flags are not used in the code.
SERIAL_HAVE_RXDMA and SERIAL_HAVE_TXDMA flags are used instead.
STM32_UART_TXDMA flag is not even defined in Kconfig
With TCD set to loop, there is a window where the
DMA has raised Done, but not reloaded the TCD, resetting
count and clearing Done.
In this window imxrt_dmach_getcount could then return 0.
Resulting in imxrt_dma_nextrx returning RXDMA_BUFFER_SIZE.
Which is not a valid index in the FIFO.
Since the count will be set to RXDMA_BUFFER_SIZE. When the DMA
engine completes the TCD reload. The imxrt_dma_nextrx would
return 0. Therefore:
(RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE
accomplishes this.
With TCD set to loop, there is a window where the
DMA has raised Done, but not reloaded the TCD, resetting
count and clearing Done.
In this window imxrt_dmach_getcount could then return 0.
Resulting in imxrt_dma_nextrx returning RXDMA_BUFFER_SIZE.
Which is not a valid index in the FIFO.
Since the count will be set to RXDMA_BUFFER_SIZE. When the DMA
engine completes the TCD reload. The imxrt_dma_nextrx would
return 0. Therefore:
(RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE
accomplishes this.
With TCD set to loop, there is a window where the
DMA has raised Done, but not reloaded the TCD, resetting
count and clearing Done.
In this window imxrt_dmach_getcount could then return 0.
Resulting in imxrt_dma_nextrx returning RXDMA_BUFFER_SIZE.
Which is not a valid index in the FIFO.
Since the count will be set to RXDMA_BUFFER_SIZE. When the DMA
engine completes the TCD reload. The imxrt_dma_nextrx would
return 0. Therefore:
(RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE
accomplishes this.
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
The DMA can bring in more rx data, than the number of
DMA completions call backs. The call back happen on
idle, 1/2 and full events. But in between these events
the DMA can write more data to the buffers memory that
need to be brought in to the cache. (invalidate)
We do the invalidate on the reads from the fifo memory
if the the DMA as commited since the last read.
The BIT macro is widely used in NuttX,
and to achieve a unified strategy,
we have placed the implementation of the BIT macro
in bits.h to simplify code implementation.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
When we build NuttX on macOS, it shows many `sed` messages (and the build still completes successfully):
```text
$ tools/configure.sh pinephone:nsh
$ make
sed: illegal option -- r
```
This is due to the Makefiles executing `sed -r` which is not a valid option on macOS.
This PR proposes to change `sed -r` to `sed -E` because:
- `sed -E` on macOS is equivalent to `sed -r` on Linux
- `sed -E` and `sed -r` are aliases according to the GNU `sed` Manual
- `sed -E` is already used in nuttx_add_romfs.cmake, nuttx_add_symtab.cmake and process_config.sh
stm32_ifdown() holds critical section when calling stm32_ethreset().
That function used to call up_mdelay(10) while waiting for the ethernet
peripheral reset to complete. This resulted in excessively long
critical section time with interrupts disabled.
The actual expected delay is a few clock ticks of the 50 MHz clock domain.
This commit changes polling interval to 1us and maximum to 10us.
This commit adds support for 1 wire interface over serial driver. SAMv7
MCU does not have build in one wire support therefore external hardware
still has to be used (connection of RX/TX for example).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
UART/USART peripheral can be used for more than just standard serial
driver. It can for example be used for 1 wire interface communication
(with external circuitry added). This changes the Kconfig for SAMv7 to
allow future implementation of these drivers. Now user can select
what kind of a driver he wants on UART/USART (serial or something else).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
When unwind instruction is 0xb2,the subsequent instructions
are uleb128 bytes.
For now,it uses only the first uleb128 byte in code.
For vsp increments of 0x204~0x400,use one uleb128 byte like below:
0xc06a00e4 <unwind_test_work>: 0x80b27fac
Compact model index: 0
0xb2 0x7f vsp = vsp + 1024
0xac pop {r4, r5, r6, r7, r8, r14}
For vsp increments larger than 0x400,use two uleb128 bytes like below:
0xc06a00e4 <unwind_test_work>: @0xc0cc9e0c
Compact model index: 1
0xb2 0x81 0x01 vsp = vsp + 1032
0xac pop {r4, r5, r6, r7, r8, r14}
The unwind works well since the decoded uleb128 byte is also 0x81.
For vsp increments larger than 0x600,use two uleb128 bytes like below:
0xc06a00e4 <unwind_test_work>: @0xc0cc9e0c
Compact model index: 1
0xb2 0x81 0x02 vsp = vsp + 1544
0xac pop {r4, r5, r6, r7, r8, r14}
In this case,the decoded uleb128 result is 0x101(vsp=0x204+(0x101<<2)).
While the uleb128 used in code is 0x81(vsp=0x204+(0x81<<2)).
The unwind aborts at this frame since it gets incorrect vsp.
To fix this, add uleb128 decode to cover all the above case.
Signed-off-by: chao an <anchao@xiaomi.com>
Summary
include/arch/syscall.h: Assembler messages:
include/arch/syscall.h:133: Error: bad instruction `struct arm_smccc_res'
include/arch/syscall.h:134: Error: junk at end of line, first unrecognized character is `{'
include/arch/syscall.h:135: Error: bad instruction `unsigned long a0'
include/arch/syscall.h:136: Error: bad instruction `unsigned long a1'
include/arch/syscall.h:137: Error: bad instruction `unsigned long a2'
include/arch/syscall.h:138: Error: bad instruction `unsigned long a3'
include/arch/syscall.h:139: Error: bad instruction `unsigned long a4'
include/arch/syscall.h:140: Error: bad instruction `unsigned long a5'
include/arch/syscall.h:141: Error: bad instruction `unsigned long a6'
include/arch/syscall.h:142: Error: bad instruction `unsigned long a7'
include/arch/syscall.h:143: Error: junk at end of line, first unrecognized character is `}'
include/arch/syscall.h:145: Error: bad instruction `typedef struct arm_smccc_res
Signed-off-by: wangming9 <wangming9@xiaomi.com>
The typo s/.timid/.tcid prevents to compile NuttX with
quadrature encoder configured for timer1 (CONFIG_SAMV7_TC1_QE)
and s/SAM_TC789_BASE/SAM_TC678_BASE prevented use of the
of the timer 2.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
In an implementation that supports the ARM Security Extensions, only
software executing in a Secure PL1 mode can write to CNTFRQ
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Summary:
Adding virtual evaluate platform GoldFish. Which is based on
Android Goldfish Emulator, it's a ARM virt board but Android
enhance it with more featue.
The patch set goldfish as a arm chip.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
In an implementation that supports the ARM Security Extensions, only
software executing in a Secure PL1 mode can write to CNTFRQ
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This change fixes the issue when SAMv7 GMAC sometimes does not start packet
transmission. The issue is that EMAC_NCR_TSTART is written to EMAC_NCR register
while tx descriptor is not delivered to memory.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
According to the current implementation, "cxd56_cpu1siguninit" will only
be called once during the NuttX startup phase,
and it won't involve scenarios of multi-threaded concurrent access.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Some SD card connectors do not have separate card detection pin. In that
case card detection has to be done on CD/DAT3 data line. This means
software (i.e. architecture level driver) has to take care of pin
configuration switching (pin has to be set as data pin in case of
transfer and as interrupt card detection pin when there is no action
on data line).
This commit adds CD/DAT3 line card detection support for SAMv7 MCU.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Current implementation of QSPI in SPI mode was available only for MCUs
that do not have standard SPI at all. MCUs with both QSPI and SPI can
however also use QSPI in SPI mode and thus have one more SPI bus. This
commit adds required defines and config options to support QSPI in SPI
mode for all SAMv7 MCUs.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit adds function pwm_set_polarity() that setups channel
polarity based on input info from application layer.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
