Update internal reference to get the most updated Espressif's
libraries. Those libraries are based on branch `release/v5.1` of
the ESP-IDF and include `v5.1.4` version of it.
sim/posix/sim_alsa.c:728:24: runtime error: member
access within null pointer of type 'const struct sim_codec_ops_s'
Signed-off-by: jinxiuxu <jinxiuxu@xiaomi.com>
In a multicore task scenario, there may be a situation where the task runs on different cores at different time slices (when the task is not bound to a particular core).
When the task calls cache clean/flush(range > cache size), depending on the optimization, clean_all, flush_all are called. however, at this point, there may be dirty data or incomplete data profiles in the cache on the kernel that is running the task, which may result in dirty data being flushed into memory or make the application think that the flushed data should be successfully flushed into memory, leading to unknown consequences.
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
In a multicore task scenario, there may be a situation where the task runs on different cores at different time slices (when the task is not bound to a particular core).
When the task calls cache clean/flush(range > cache size), depending on the optimization, clean_all, flush_all are called. however, at this point, there may be dirty data or incomplete data profiles in the cache on the kernel that is running the task, which may result in dirty data being flushed into memory or make the application think that the flushed data should be successfully flushed into memory, leading to unknown consequences.
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Execute data and instruction sync barriers after writing MPU register,
to ensure MPU setting take effects that the new changes are seen.
testing in lm3s6965-ek:qemu-protected
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
when the vsync comes, fb drivers should call fb_vsync_pollnotify to notify POLLPRI, so that users can catch the synchronization time of vsync and do something.
Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
According to the current design on the armv7-a platform,
only fiq is processed in TEE, while irq and fiq are processed
in REE.
If we enable the irq function in TEE, when we process
some signal-related scenarios in TEE,
such as the ostest sighand testcase, this testcase will
call up_irq_enable() to enable irq interrupt in the
arm_sigdeliver() function. After the signal processing
logic is executed, irq will be disabled again.
During the interval of enabling irq, some external device
irq interrupts will be enabled, but these external device
irqs do not have corresponding handlers registered in TEE,
so an "unexpected irq isr exception" will be triggered.
Therefore, a better implementation is to keep the original
implementation of the up_irq_enable() function, that is,
to enable only fiq in TEE and to enable irq and fiq in REE.
Then for vendor-specific requirements, such as the need to
briefly enable irq during the TEE initialization process
and then disable irq before starting APz in TEE, we directly
provide a separate implementation of enabling irq in the
vendor, without modifying the implementation of the public
up_enable_irq() function.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
==263401==ERROR: AddressSanitizer: stack-use-after-return on address 0xf515f260 at pc 0x042434f0 bp 0x9ac24e78 sp 0x9ac24e68
WRITE of size 4 at 0xf515f260 thread T0
#0 0x42434ef in nxsem_get_value semaphore/sem_getvalue.c:65
#1 0x413110d in work_thread wqueue/kwork_thread.c:195
#2 0x412c4f6 in nxtask_start task/task_start.c:129
#3 0x427b1fc in pre_start sim/sim_initialstate.c:52
Address 0xf515f260 is located in stack of thread T0 at offset 32 in frame
#0 0x928c9e3 in host_settimer sim/posix/sim_hosttime.c:104
This frame has 1 object(s):
[32, 48) 'it' (line 105) <== Memory access at offset 32 is inside this variable
HINT: this may be a false positive if your program uses some custom stack unwind mechanism, swapcontext or vfork
(longjmp and C++ exceptions *are* supported)
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
arch/xtensa/src/esp32s3/hardware/esp32s3_sdmmc.h|esp32s3_soc.h,
boards/xtensa/esp32s3/common/include/esp32s3_board_sdmmc.h,
boards/xtensa/esp32s3/common/src/Make.defs|esp32s3_board_sdmmc.c,
boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c: add SD/mmc driver
Support 1-bit bus width and 4-bit bus width. Support eMMC high speed SDR mode.
Support transfer data with DMA. Support SD clock frequency up to 40MHZ.
Signed-off-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
Reviewed-by: Yuezhang Mo <Yuezhang.Mo@sony.com>
Reviewed-by: Jacky Cao <Jacky.Cao@sony.com>
Tested-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
CC: unistd/lib_setregid.c "/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 53: warning #193-D:
zero used for undefined preprocessing identifier "NR_IRQS"
# if NR_IRQS <= 256
^
"/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 82: warning #193-D:
zero used for undefined preprocessing identifier "NR_IRQS"
#if NR_IRQS <= 256
CC: mount/fs_umount2.c "/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 72: warning #193-D:
zero used for undefined preprocessing identifier "NR_IRQS"
#if NR_IRQS <= 256
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
the greenhills compiler provide its own implementation of va_start,
va_end, va_arg, va_copy. so if we are build vela with greenhills
compiler, we should using the stdarg implementation provided by
greenhills, not our own
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Enabling CONFIG_PRIORITY_INHERITANCE config causes a build error
Based on Nuttx OS reserve memory for mutex struct.
Pass build based on
- CONFIG_PRIORITY_INHERITANCE y
- CONFIG_SEM_PREALLOCHOLDERS 0/8
Pass CP15_CACHE_INVALIDATE argument with r1 register to cp15_dcache_op_level.
cache level is 0(L1 D-Cache) with r0 register.
prototype:
void cp15_dcache_op_level(uint32_t level, int op)
Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
argument to macro is empty
SP_DSB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
argument to macro is empty
SP_DMB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
argument to macro is empty
SP_DSB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
argument to macro is empty
SP_DMB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 296: warning #76-D:
argument to macro is empty
SP_DSB();
^
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
according to armv6-m/armv7-m arch reference manual:
the three ISB {<opt>}, DSB {<opt>}, DMB {<opt>} instructions <opt>
field are defined as:
Specifies an optional limitation on the ISB/DSB/DMB operation. Allowered
values are:
Full system ISB/DSB/DMB operation, encoded as option=='1111'. Can be
omitted.
All other encodings of the options are RESERVED.
the "#opt" field of "isb #opt"
So we could remove the options field in Armv7-m platform.
The following are the build error with greenhills compiler:
CC: common/arm_exit.c [asarm] (error #2071) /tmp/gh_001h70j1.si 92: bad parameter
isb 15
------^
[asarm] (error #2071) /tmp/gh_001h70j1.si 112: bad parameter
isb 15
------^
[asarm] (error) errors during processing
According to armv8-m arch reference manual:
the ISB/DMB instruction's "opt" encoding rule is same as
armv6-m/armv7-m, but the "DSB" instruction is different, in armv8-m, the
"DSB {<opt>}" field has two valid encoding options: 0b0000, 0b0100.
and all other encoding options are reserved.
In Armv7-a/Armv8-a, the dsb/dmb option field has 8 valid state value.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
The following are the compile error that reported
by GreenHills compiler:
"/mnt/yang/qixinwei_commit/nuttx/include/arch/syscall.h", line 156 (col. 17): error #2036-D:
cannot allocate "reg0" to specified caller-saved register
"/mnt/yang/qixinwei_commit/nuttx/include/arch/syscall.h", line 157 (col. 17): error #2036-D:
cannot allocate "reg1" to specified caller-saved register
Then we fix this greenhills compilation error by explicitly specifying
the registers in the clobber list in the inline assembly code.
This fix is successful in compiling on the
nuttx/boards/arm/mps/mps2-an500/configs/nsh platform and passes
the ostest test.
However, if we keep the implementation the same for both the default
and Greenhills compilers, the default compiler will report the
following two issues:
1. the "sys_call6" function will report compile error when
compiling on "./vendor/qemu/boards/smartspeaker/configs/smartspeaker-knsh"
platform, the detailed error info:
CC: proxies/PROXY_mq_getattr.c In file included from /home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/sys/syscall.h:35,
from /home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/syscall.h:30,
from proxies/PROXY_mmap.c:5:
In function 'sys_call6',
inlined from 'mmap' at proxies/PROXY_mmap.c:9:22:
/home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/arch/syscall.h:297:3: error: 'asm' operand has impossible constraints
297 | __asm__ __volatile__
| ^~~~~~~
2. when running on qemu-armv7-a platform, the modification to
"smh_call()" function will make the system fail to boot up, so
we need to keep the default compiler implementation and greenhills
compiler implementation separate
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
(cherry picked from commit cb48b749b1c9cad8cfb96bff7c5e9b6ebf20fc8a)
Some multicore RV chips (mpfs, jh7110 etc) have hart clusters
and globally numbered mhartids. Clusters with single hart or
SMP support can be managed by one NuttX instance. Currently
NuttX expects to use cluster-local ids.
This allows us to get local ids by offsetting mhartids with a
base value.
Note that there are chips (e.g. k230) that use cluster-local
ids directly, so this is not needed for them.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
1. For some reasons, the bootloader will set CPU source to BBPLL and enable it,
but there are calibration issues, so we need turn off the BBPLL and do calibration again to fix the issue.
2. Corresponding issue link: 89cc9084ab
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
This generalizes the in-kernel syscall approach from KERNEL mode to
all build modes so that to unify in-kernel syscall invocations. As
a result, machine mode ECALL and the supervisor folder are no longer
needed.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This commit adds missing add_link_options to specify sanitizers
also during linking stage.
Signed-off-by: Daniel Jasinski <jasinskidaniel95szcz@gmail.com>
When executing fork() via a system call, the parent's stack gets corrupted
by the child, as during exception return the child loads the parent's
stack pointer from the context save area.
This happens because the full parent stack (including what has been pushed
during the system call) is copied to the child. What should be copied, is
only the user stack of the parent (the kernel stack is not interesting).
Fix this by only copying the parent's user stack to the child; and make
the child return directly to userspace (not via dispatch_syscall).
Simplifies the implementation of dispatch_syscall, making it easier to
understand and maintain. Let the C-compiler do most of the work, instead
of doing everything as inline assembly.
This adds the necessary defines to set the USARTs' kernel clock source
selection.
This is required for a configuration where the bootloader (running
before NuttX) changes the USARTs' clock selection, so they need to be
restored on board init.
This is according to the reference manual RM0399 page 448.
Create version.h
chip/intel64_irq.c:78:34: error: conflicting type qualifiers for ‘g_irq_spin’
78 | static spinlock_t g_irq_spin;
| ^~~~~~~~~~
In file included from chip/intel64_irq.c:40:
include/nuttx/spinlock.h:168:28: note: previous declaration of ‘g_irq_spin’ with type ‘spinlock_t’ {aka ‘volatile unsigned char’}
168 | extern volatile spinlock_t g_irq_spin;
| ^~~~~~~~~~
chip/intel64_cpu.c: In function ‘x86_64_cpu_ready_set’:
chip/intel64_cpu.c:314:3: warning: implicit declaration of function ‘spin_lock’ [-Wimplicit-function-declaration]
314 | spin_lock(&g_ap_boot);
| ^~~~~~~~~
chip/intel64_cpu.c:322:3: warning: implicit declaration of function ‘spin_unlock’; did you mean ‘sched_unlock’? [-Wimplicit-function-declaration]
322 | spin_unlock(&g_ap_boot);
| ^~~~~~~~~~~
Signed-off-by: chao an <anchao@lixiang.com>
This revises PROTECTED build for qemu-rv mainly to avoid hard-coded
addresses in linker scripts. It also added rv32 support, cleaned up
config `pnsh64` and added config `pnsh`.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This adds explicit `void mm_free_delaylist(heap)` interface so that
to force freeing the heap's delaylist.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This adds NuttSBI support for rv-virt device so that to enable CI
checks for NuttSBI later. It allows using `-bios nuttx` option to
run NuttX with QEMU v6.2 w/o OpenSBI.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This adjusts sbi_start behavior so that if SBI late initialization hook
is defined, PMP setting is assumed to be fully done in the hook, because
the default PMP operation may fail for various reasons such as lacking
free entries or the default setting doesn't work on devices like QEMU
v6.2.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
These symbols only used in esp_spi.c and too simple
to conflict with others, so mark them as static:
- cfg
- ctx
- dev_cfg
- timing_param
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Fixes regression from https://github.com/apache/nuttx/pull/12220
Error: chip/k230_start.c:80:13: error: 'k230_copy_init_data' defined but not used [-Werror=unused-function]
80 | static void k230_copy_init_data(void)
| ^~~~~~~~~~~~~~~~~~~
HPET can be used as system clock for x86_64
to set HPET as system clock you have to enable:
CONFIG_ONESHOT=y
CONFIG_ALARM_ARCH=y
CONFIG_INTEL64_ONESHOT=y
CONFIG_ARCH_INTEL64_HPET_ALARM=y
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Other ESP32-S3 modules (with embedded flash and PSRAM) were added.
Also, the `help` section of the Kconfig was updated to better
describe the modules' flash and PSRAM sizes.
Steppoint can be implemented by icount(instruction count)
from RISC-V debug extension, but it may not implemented in all RISC-V cores.
Unfortunately, the currently supported RISC-V cores do not implement it.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Provide `up_copy_section` function that enables copying data using
the data bus. If the memory destination address is accessible
through the instruction bus, the data is copied using the
correspondent address accessible through the data bus.
rename _rdtsc macro to rdtsc to avoid conflict with external code
rename rdtsc macro to rdtscp to be the same as asm instruction used
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
The buffer initialization function (`i2s_buf_initialize`) calls
`i2s_buf_free`, which performs buffer initialization within a
critical section (`spin_lock_irqsave`). If this function is called
under the same critical section (same spinlock), initialization
will hang.
This change implements a driver for the two watchdog timers on the BL808, and enables it as part of the timer config. The driver is based on the GP timer driver.
arch/xtensa: add support for capture driver on ESP32 and ESP32|S3|
Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed
Basic bring up ready. New Kconfig options for motor.
Good motor registration
Working on enabling pwm generators
Working on enabling pwm generators
Added fops functions
Success on PWM 50%
stable pwm operation for bdc
Added loopback option for testing
Improved rules on fsm
Working motor direction control
Testing new ISR for fault handling
Issues on fault ISR
Removed fault implementation (not working)
Added support for esp32s3
Documentation improvements
Added default motor spin direction
Added parameter change while running
Review fixes
arch/xtensa: add support for fault signal on motor control
Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed
Basic bring up ready. New Kconfig options for motor.
Good motor registration
Working on enabling pwm generators
Working on enabling pwm generators
Added fops functions
Success on PWM 50%
stable pwm operation for bdc
Added loopback option for testing
Improved rules on fsm
Working motor direction control
Testing new ISR for fault handling
Issues on fault ISR
Removed fault implementation (not working)
Added support for esp32s3
Documentation improvements
Added default motor spin direction
Added parameter change while running
Got responsive fault indicator
Working brakes - still need to work on starting isr
Fixed single-time ISR initializiation
Working soft brake on fault
Improved KConfig for BDC and BLDC
Kconfig fixed at board level
when the thread to backtrace is exiting, get_tcb and up_backtrace in
different critical section may cause try to dump invalid pointer, have
to ensure the nxsched_get_tcb and up_backtrace inside same critical
section procedure.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
This fixes the always zero time in NuttSBI case as the `error` field
contains the correct timestamp. This in turn also fixes the block of
`up_udelay()` which further leads to boot failure of `canmv230:master`
config.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Correctly releasing channels after using QSPI is crucial
to prevent issues caused by multiple requests that may lead
to DMA channel resource conflicts.
The common `up_allocate_heap` is a strong symbol, which leads to
error when building with CONFIG_DEBUG_LINK_WHOLE_ARCHIVE. Make
`up_allocate_heap` weak function to mitigate this problem.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
This PR configures the BL808 and SG2000 MMU (inside T-Head C906) to cache the the Kernel Text, Data and Heap. We set the MMU Flags (Shareable, Bufferable and Cacheable) as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906
This PR fixes the Slow Memory Access for NuttX Kernel in BL808 and SG2000: https://github.com/apache/nuttx/issues/12696
In the next PR, we will fix the Slow Memory Access for NuttX Apps, by caching the User Text and Data.
arch/risc-v/src/bl808/bl808_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for BL808 Kernel Text, Data and Heap
arch/risc-v/src/sg2000/sg2000_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for SG2000 Kernel Text, Data and Heap
This fixes stack pointer restore logic to avoid parent stack corruption
by forked child in PROTECTED build.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This fixes `tp` value of forked child in PROTECTED build to support
vfork. Why? the optimized `dispatch_syscall` requires `tp` to hold
the task TCB since commit e6973c764c.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
tc3xx/tc3xx_timerisr.c: In function ‘up_timer_initialize’:
tc3xx/tc3xx_timerisr.c:58:39: warning: passing argument 1 of ‘tricore_systimer_initialize’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
58 | lower = tricore_systimer_initialize(&MODULE_STM0, 192, SCU_FREQUENCY);
In file included from tc3xx/tc3xx_timerisr.c:31:
nuttx/arch/tricore/src/common/tricore_internal.h:252:35: note: expected ‘void *’ but argument is of type ‘volatile Ifx_STM *’ {aka ‘volatile struct _Ifx_STM *’}
252 | tricore_systimer_initialize(void *tbase, int irq, uint64_t freq);
| ~~~~~~^~~~~
tc3xx/tc3xx_serial.c:177:16: warning: initialization discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
177 | .uartbase = &MODULE_ASCLIN0,
| ^
tc3xx/tc3xx_serial.c:178:16: warning: initialization discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
178 | .pins = &g_uart0_pins,
| ^
common/tricore_trapcall.c: In function ‘tricore_trapcall’:
common/tricore_trapcall.c:66:3: warning: passing argument 4 of ‘_assert’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
66 | PANIC_WITH_REGS("Trap", CURRENT_REGS);
| ^~~~~~~~~~~~~~~
In file included from common/tricore_trapcall.c:29:
nuttx/include/assert.h:189:45: note: expected ‘void *’ but argument is of type ‘volatile uintptr_t *’ {aka ‘volatile long unsigned int *’}
189 | FAR const char *msg, FAR void *regs);
Signed-off-by: chao an <anchao@lixiang.com>
This fixes the following issue when configuring canmv230:master
with Ubuntu stock toolchain and cmake 3.22:
```
CMake Error at .../arch/risc-v/src/cmake/Toolchain.cmake:218 (if):
if given arguments:
"STREQUAL" "GNU_RVG"
Unknown arguments specified
```
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
