Commit Graph

42 Commits

Author SHA1 Message Date
Alan C. Assis
867c6d0636 esp32: Add initial support to Bluetooth Low Energy
Co-authored-by: saramonteiro <saramonteirosouza44@gmail.com>
Co-authored-by: Gustavo Henrique Nihei <gustavonihei@gmail.com>
2021-10-04 15:10:37 -03:00
Abdelatif Guettouche
1385ea7673 arch/esp32: Properly handle GPIO interrupt in SMP.
The PRO CPU and APP CPU have different peripherals for GPIO interrupts.
Each CPU needs to allocate an interrupt and attach it to its GPIO
peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-27 13:24:00 +09:00
Abdelatif Guettouche
fc594c5d25 esp32_irq.c: Extend the CPU interrupt/peripheral map to include the
status of the interrupt (enabled/disabled).

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
810ed19b8f arch/xtensa/esp32_irq.c: Enable/disable interrupts using the Interrupt
Matrix.

This allows manipulating interrupts from both CPUs.  Internal interrupts
however, still need to be disabled/enabled by each CPU.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
a7abd56448 arch/xtensa: Move the Xtensa specific part of interrupts to
xtensa/include/irq.h

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
470799b0b3 arch/xtensa/esp32_irq: Remove the map/unmap IRQ functions they are used
only inside this file.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
04cd520293 arch/xtensa/esp32: Merge esp32_intdecode with esp32_irq.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
79cc12c034 arch/xtesna/esp32: Merge the contents of esp32_cpuint and esp32_irq.
They do the same thing (manipulate interrupts) keeping them separated
was making things harder.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
02c17c3169 arch/esp32: Simplify the interrupt allocation process.
Allocating and attaching interrupts were both exported outside, however
these two move hand in hand and we don't have to expose these details.
Also, the parameters passed are saved and will be used to retrieve
information about the interrupt and the attached peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
eefe7ebe5f xtensa/esp32_cpuint: export only one function to allocate a CPU
interrupt.

That function will have a parameter to decide whether to allocate a
level sensitive interrupt or an edge sensitive interrupt.

All the drivers are also updated with this API change.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
5d626f7267 xtensa/esp32_irq.c: Hard code special IRQs in the IRQ map. These IRQs
are do not go through the regular process where we attache the CPU
interrupt to a peripheral and update our map, also, they are fixed and a
have reserved CPU interrupt, thus hard code their values at startup.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
56a7f3b651 arch/xtensa/esp32: Update the drivers regarding the API change in IRQ
handling.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
5be9f24fe5 arch/xtensa/esp32: Disable the CPU interrupt right when it's alloacted.
At this point we are in a critical section and have all the necessary
information to disable the interrupt properly (CPU, and CPU interrupt).
Leaving it to the drivers will complicate things as converting from IRQs
to CPU interrupts could be tricky in SMP mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
97dca8fe10 arch/xtensa/esp32: Use the same g_intenable shadows in cpuint.c and
irq.c

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
633cdf8e27 arch/xtensa/esp32: Map NuttX's IRQs to ESP32 CPU interrupts.
This map also keeps track of the CPU that attached the IRQ.  This will
be used to properly disable the interrupt in the correct CPU in SMP
mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-08-20 13:17:25 -03:00
Xiang Xiao
2e54df0f35 Don't include assert.h from public header file
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-03 08:36:03 -07:00
Xiang Xiao
8640d82ce0 arch: Rename g_intstackbase to g_intstacktop
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-16 12:41:41 +09:00
Alin Jerpelea
778f050102 arch: xtensa: Author Gregory Nutt: update licenses to Apache
Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-04-02 03:14:31 -05:00
Abdelatif Guettouche
58655d1efd arch/xtensa/src/esp32: SMP case of interruptstack.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-10-27 07:44:20 +09:00
Abdelatif Guettouche
c97d11aa7b arch/xtensa: Add the optional interrupt stack.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-10-27 07:44:20 +09:00
Abdelatif Guettouche
769d68a762 arch/xtensa: Fix some typos and correct some comments.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-09-30 13:55:28 -03:00
Ouss4
99d3317329 arch/xtensa/src/esp32/esp32_irq.c: Include esp32_gpio.h to avoid
implicit declaration warning.
2020-08-27 14:12:34 +08:00
Xiang Xiao
cde88cabcc Run codespell -w with the latest dictonary again
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-02-23 22:27:46 +01:00
Xiang Xiao
76bbed07a4 Call up_irqinitialize from irq subsystem
Call up_irqinitialize from irq subsystem to make the irq ready for use as soon as possible
2020-02-08 07:39:22 -06:00
Xiang Xiao
6a3c2aded6 Fix wait loop and void cast (#24)
* Simplify EINTR/ECANCEL error handling

1. Add semaphore uninterruptible wait function
2 .Replace semaphore wait loop with a single uninterruptible wait
3. Replace all sem_xxx to nxsem_xxx

* Unify the void cast usage

1. Remove void cast for function because many place ignore the returned value witout cast
2. Replace void cast for variable with UNUSED macro
2020-01-02 10:54:43 -06:00
Mark Schulte
b3222bbc8a irq_dispatch: Add argument pointer to irq_dispatch
Provide a user defined callback context for irq's, such that when
registering a callback users can provide a pointer that will get
passed back when the isr is called.
2017-02-27 06:27:56 -06:00
Gregory Nutt
586f0aab50 Fix context save logic when called in window ABI configuration. Add an IDLE stack. Don't depend on the mystery stack received from the bootloader. 2016-12-18 10:08:08 -06:00
Gregory Nutt
d4ad5f04d3 Xtensa ESP32: Minor rearchitecting of how CPU interrupts are enabled. MOre to come. 2016-12-16 14:13:09 -06:00
Gregory Nutt
aa5a8b0ca2 Xtensa: Make sure that all C callable assembly functions includes ENTRY prologue and RET epilogue. 2016-12-15 14:02:19 -06:00
Gregory Nutt
4d0b0e44f1 Xtensa/ESP32: Add up_cpu_idlestack() and fix some compile issues. 2016-10-31 14:56:48 -06:00
Gregory Nutt
28d1478480 Xtensa/ESP32: Add CPU1 startup logic 2016-10-31 13:15:15 -06:00
Gregory Nutt
a787a99071 ESP32: Add inter-cpu interrupts 2016-10-31 08:29:28 -06:00
Gregory Nutt
63d5ab5b67 Add logic to attach inter-CPU interrupts. Fix some compilation errors. 2016-10-30 16:15:04 -06:00
Gregory Nutt
afcda29646 ESP32: Fix some warnings 2016-10-27 16:46:34 -06:00
Gregory Nutt
0a96f3a8c8 ESP32: Fix some compilation issues 2016-10-26 12:50:10 -06:00
Gregory Nutt
650757bbf0 ESP32: Add GPIO support 2016-10-26 12:11:24 -06:00
Gregory Nutt
fef7b414c5 Add logic to attach peripheral interrupt sources to CPU interrupts 2016-10-25 15:19:29 -06:00
Gregory Nutt
2a59205ffa ESP32: Add CPU interrupt managmement logic; improve level interrupt decoding. 2016-10-25 12:02:53 -06:00
Gregory Nutt
4cf60022ca Xtensa: Correct some compile issues 2016-10-23 16:25:55 -06:00
Gregory Nutt
c3d76d56bc Xtensa: Fix some compilation issues 2016-10-23 10:06:30 -06:00
Gregory Nutt
112b62a14e Xtensa: Correct variou compilation issues 2016-10-23 08:04:57 -06:00
Gregory Nutt
a9a4f6384d Xtensa: Add interrupt enable/disable controls. Add dummy timer and IRQ initialization. 2016-10-23 08:00:17 -06:00